arm_adi_v5: Update DP (Debug Port) registers defined in ADIv5.2.

Note:
WCR (Wire Control Register) is replaced by DLCR (Data Link Control
Register). And only TURNROUND field is modifiable.

[andreas.fritiofson@gmail.com]:

Rename DP_IDCODE to DP_DPIDR as well.

Sort list by address and align it using spaces instead of tabs. Add
comments about supporting DP versions.

Remove non-functional wcr command completely.

Change-Id: Ic6b781b07c8eead8b0237d497846d0da060cb1ba
Signed-off-by: Alamy Liu <alamy.liu@gmail.com>
Signed-off-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Reviewed-on: http://openocd.zylin.com/3244
Tested-by: jenkins

diff --git a/src/target/adi_v5_swd.c b/src/target/adi_v5_swd.c
index 771b46090e175c2d91b694fda67517afb08e286b..d1a4870334ad9770e74323be5cfebd1f9781ca3d 100644 (file)
--- a/src/target/adi_v5_swd.c
+++ b/src/target/adi_v5_swd.c
@@ -99,14 +99,14 @@ static int swd_run_inner(struct adiv5_dap *dap)
 
 static int swd_connect(struct adiv5_dap *dap)
 {
-       uint32_t idcode;
+       uint32_t dpidr;
        int status;
 
        /* FIXME validate transport config ... is the
         * configured DAP present (check IDCODE)?
         * Is *only* one DAP configured?
         *
-        * MUST READ IDCODE
+        * MUST READ DPIDR
         */
 
        /* Note, debugport_init() does setup too */
@@ -116,7 +116,7 @@ static int swd_connect(struct adiv5_dap *dap)
        dap->do_reconnect = false;
        dap->select = DP_SELECT_INVALID;
 
-       swd_queue_dp_read(dap, DP_IDCODE, &idcode);
+       swd_queue_dp_read(dap, DP_DPIDR, &dpidr);
 
        /* force clear all sticky faults */
        swd_clear_sticky_errors(dap);
@@ -124,7 +124,7 @@ static int swd_connect(struct adiv5_dap *dap)
        status = swd_run_inner(dap);
 
        if (status == ERROR_OK) {
-               LOG_INFO("SWD IDCODE %#8.8" PRIx32, idcode);
+               LOG_INFO("SWD DPIDR %#8.8" PRIx32, dpidr);
                dap->do_reconnect = false;
        } else
                dap->do_reconnect = true;
@@ -342,61 +342,6 @@ int dap_to_swd(struct target *target)
        return retval;
 }
 
-COMMAND_HANDLER(handle_swd_wcr)
-{
-       int retval;
-       struct target *target = get_current_target(CMD_CTX);
-       struct arm *arm = target_to_arm(target);
-       struct adiv5_dap *dap = arm->dap;
-       uint32_t wcr;
-       unsigned trn, scale = 0;
-
-       switch (CMD_ARGC) {
-       /* no-args: just dump state */
-       case 0:
-               /*retval = swd_queue_dp_read(dap, DP_WCR, &wcr); */
-               retval = dap_queue_dp_read(dap, DP_WCR, &wcr);
-               if (retval == ERROR_OK)
-                       dap->ops->run(dap);
-               if (retval != ERROR_OK) {
-                       LOG_ERROR("can't read WCR?");
-                       return retval;
-               }
-
-               command_print(CMD_CTX,
-                       "turnaround=%" PRIu32 ", prescale=%" PRIu32,
-                       WCR_TO_TRN(wcr),
-                       WCR_TO_PRESCALE(wcr));
-       return ERROR_OK;
-
-       case 2:         /* TRN and prescale */
-               COMMAND_PARSE_NUMBER(uint, CMD_ARGV[1], scale);
-               if (scale > 7) {
-                       LOG_ERROR("prescale %d is too big", scale);
-                       return ERROR_FAIL;
-               }
-               /* FALL THROUGH */
-
-       case 1:         /* TRN only */
-               COMMAND_PARSE_NUMBER(uint, CMD_ARGV[0], trn);
-               if (trn < 1 || trn > 4) {
-                       LOG_ERROR("turnaround %d is invalid", trn);
-                       return ERROR_FAIL;
-               }
-
-               wcr = ((trn - 1) << 8) | scale;
-               /* FIXME
-                * write WCR ...
-                * then, re-init adapter with new TRN
-                */
-               LOG_ERROR("can't yet modify WCR");
-               return ERROR_FAIL;
-
-       default:        /* too many arguments */
-               return ERROR_COMMAND_SYNTAX_ERROR;
-       }
-}
-
 static const struct command_registration swd_commands[] = {
        {
                /*
@@ -411,15 +356,6 @@ static const struct command_registration swd_commands[] = {
                .mode = COMMAND_CONFIG,
                .help = "declare a new SWD DAP"
        },
-       {
-               .name = "wcr",
-               .handler = handle_swd_wcr,
-               .mode = COMMAND_ANY,
-               .help = "display or update DAP's WCR register",
-               .usage = "turnaround (1..4), prescale (0..7)",
-       },
-
-       /* REVISIT -- add a command for SWV trace on/off */
        COMMAND_REGISTRATION_DONE
 };
 

diff --git a/src/target/arm_adi_v5.h b/src/target/arm_adi_v5.h
index 7c27d609411c447a6a1eaf76287c3f8757b4bc4f..13ced9f7ca78f1c5a5d21bfb7fbc1ae87cb9434f 100644 (file)
--- a/src/target/arm_adi_v5.h
+++ b/src/target/arm_adi_v5.h
@@ -47,18 +47,21 @@
 /* A[3:0] for DP registers; A[1:0] are always zero.
  * - JTAG accesses all of these via JTAG_DP_DPACC, except for
  *   IDCODE (JTAG_DP_IDCODE) and ABORT (JTAG_DP_ABORT).
- * - SWD accesses these directly, sometimes needing SELECT.CTRLSEL
+ * - SWD accesses these directly, sometimes needing SELECT.DPBANKSEL
  */
-#define DP_IDCODE              BANK_REG(0x0, 0x0)      /* SWD: read */
-#define DP_ABORT               BANK_REG(0x0, 0x0)      /* SWD: write */
-#define DP_CTRL_STAT           BANK_REG(0x0, 0x4)      /* r/w */
-#define DP_RESEND              BANK_REG(0x0, 0x8)      /* SWD: read */
-#define DP_SELECT              BANK_REG(0x0, 0x8)      /* JTAG: r/w; SWD: write */
-#define DP_RDBUFF              BANK_REG(0x0, 0xC)      /* read-only */
-#define DP_WCR                 BANK_REG(0x1, 0x4)      /* SWD: r/w */
-
-#define WCR_TO_TRN(wcr) ((uint32_t)(1 + (3 & ((wcr)) >> 8)))   /* 1..4 clocks */
-#define WCR_TO_PRESCALE(wcr) ((uint32_t)(7 & ((wcr))))         /* impl defined */
+#define DP_DPIDR        BANK_REG(0x0, 0x0) /* DPv1+: ro */
+#define DP_ABORT        BANK_REG(0x0, 0x0) /* DPv1+: SWD: wo */
+#define DP_CTRL_STAT    BANK_REG(0x0, 0x4) /* DPv0+: rw */
+#define DP_DLCR         BANK_REG(0x1, 0x4) /* DPv1+: SWD: rw */
+#define DP_TARGETID     BANK_REG(0x2, 0x4) /* DPv2: ro */
+#define DP_DLPIDR       BANK_REG(0x3, 0x4) /* DPv2: ro */
+#define DP_EVENTSTAT    BANK_REG(0x4, 0x4) /* DPv2: ro */
+#define DP_RESEND       BANK_REG(0x0, 0x8) /* DPv1+: SWD: ro */
+#define DP_SELECT       BANK_REG(0x0, 0x8) /* DPv0+: JTAG: rw; SWD: wo */
+#define DP_RDBUFF       BANK_REG(0x0, 0xC) /* DPv0+: ro */
+#define DP_TARGETSEL    BANK_REG(0x0, 0xC) /* DPv2: SWD: wo */
+
+#define DLCR_TO_TRN(dlcr) ((uint32_t)(1 + ((3 & (dlcr)) >> 8))) /* 1..4 clocks */
 
 /* Fields of the DP's AP ABORT register */
 #define DAPABORT        (1UL << 0)