Remove misleading typedef and redundant suffix from struct target.
static int aduc702x_build_sector_list(struct flash_bank_s *bank);
-static int aduc702x_check_flash_completion(target_t* target, unsigned int timeout_ms);
-static int aduc702x_set_write_enable(target_t *target, int enable);
+static int aduc702x_check_flash_completion(struct target* target, unsigned int timeout_ms);
+static int aduc702x_set_write_enable(struct target *target, int enable);
#define ADUC702x_FLASH 0xfffff800
#define ADUC702x_FLASH_FEESTA (0*4)
int x;
int count;
//uint32_t v;
- target_t *target = bank->target;
+ struct target *target = bank->target;
aduc702x_set_write_enable(target, 1);
static int aduc702x_write_block(struct flash_bank_s *bank, uint8_t *buffer, uint32_t offset, uint32_t count)
{
struct aduc702x_flash_bank *aduc702x_info = bank->driver_priv;
- target_t *target = bank->target;
+ struct target *target = bank->target;
uint32_t buffer_size = 7000;
struct working_area *source;
uint32_t address = bank->base + offset;
{
uint32_t x;
uint8_t b;
- target_t *target = bank->target;
+ struct target *target = bank->target;
aduc702x_set_write_enable(target, 1);
/* sets FEEMOD bit 3
* enable = 1 enables writes & erases, 0 disables them */
-static int aduc702x_set_write_enable(target_t *target, int enable)
+static int aduc702x_set_write_enable(struct target *target, int enable)
{
// don't bother to preserve int enable bit here
target_write_u16(target, ADUC702x_FLASH + ADUC702x_FLASH_FEEMOD, enable ? 8 : 0);
*
* this function sleeps 1ms between checks (after the first one),
* so in some cases may slow things down without a usleep after the first read */
-static int aduc702x_check_flash_completion(target_t* target, unsigned int timeout_ms)
+static int aduc702x_check_flash_completion(struct target* target, unsigned int timeout_ms)
{
uint8_t v = 4;
*/
int arm_nandwrite(struct arm_nand_data *nand, uint8_t *data, int size)
{
- target_t *target = nand->target;
+ struct target *target = nand->target;
struct armv4_5_algorithm algo;
struct arm *armv4_5 = target->arch_info;
struct reg_param reg_params[3];
struct arm_nand_data {
/* target is proxy for some ARM core */
- struct target_s *target;
+ struct target *target;
/* copy_area holds write-to-NAND loop and data to write */
struct working_area *copy_area;
// this is "initialized" from the global const structure
struct sam3_chip_details details;
- target_t *target;
+ struct target *target;
struct sam3_cfg cfg;
struct membuf *mbuf;
static struct sam3_chip *
get_current_sam3(struct command_context_s *cmd_ctx)
{
- target_t *t;
+ struct target *t;
static struct sam3_chip *p;
t = get_current_target(cmd_ctx);
#if 0
static struct sam3_chip *
-target2sam3(target_t *pTarget)
+target2sam3(struct target *pTarget)
{
struct sam3_chip *pChip;
static int at91sam7_protect_check(struct flash_bank_s *bank);
static int at91sam7_write(struct flash_bank_s *bank, uint8_t *buffer, uint32_t offset, uint32_t count);
-static uint32_t at91sam7_get_flash_status(target_t *target, int bank_number);
-static void at91sam7_set_flash_mode(flash_bank_t *bank, int mode);
-static uint32_t at91sam7_wait_status_busy(flash_bank_t *bank, uint32_t waitbits, int timeout);
+static uint32_t at91sam7_get_flash_status(struct target *target, int bank_number);
+static void at91sam7_set_flash_mode(struct flash_bank_s *bank, int mode);
+static uint32_t at91sam7_wait_status_busy(struct flash_bank_s *bank, uint32_t waitbits, int timeout);
static int at91sam7_flash_command(struct flash_bank_s *bank, uint8_t cmd, uint16_t pagen);
static uint32_t MC_FMR[4] = { 0xFFFFFF60, 0xFFFFFF70, 0xFFFFFF80, 0xFFFFFF90 };
#endif
-static uint32_t at91sam7_get_flash_status(target_t *target, int bank_number)
+static uint32_t at91sam7_get_flash_status(struct target *target, int bank_number)
{
uint32_t fsr;
target_read_u32(target, MC_FSR[bank_number], &fsr);
static void at91sam7_read_clock_info(flash_bank_t *bank)
{
struct at91sam7_flash_bank *at91sam7_info = bank->driver_priv;
- target_t *target = bank->target;
+ struct target *target = bank->target;
uint32_t mckr, mcfr, pllr, mor;
unsigned long tmp = 0, mainfreq;
{
uint32_t fmr, fmcn = 0, fws = 0;
struct at91sam7_flash_bank *at91sam7_info = bank->driver_priv;
- target_t *target = bank->target;
+ struct target *target = bank->target;
if (mode && (mode != at91sam7_info->flashmode))
{
{
uint32_t fcr;
struct at91sam7_flash_bank *at91sam7_info = bank->driver_priv;
- target_t *target = bank->target;
+ struct target *target = bank->target;
fcr = (0x5A << 24) | ((pagen&0x3FF) << 8) | cmd;
target_write_u32(target, MC_FCR[bank->bank_number], fcr);
{
flash_bank_t *t_bank = bank;
struct at91sam7_flash_bank *at91sam7_info;
- target_t *target = t_bank->target;
+ struct target *target = t_bank->target;
uint16_t bnk, sec;
uint16_t arch;
static int at91sam7_erase_check(struct flash_bank_s *bank)
{
- target_t *target = bank->target;
+ struct target *target = bank->target;
uint16_t retval;
uint32_t blank;
uint16_t fast_check;
{
flash_bank_t *t_bank = bank;
struct at91sam7_flash_bank *at91sam7_info;
- target_t *target = t_bank->target;
+ struct target *target = t_bank->target;
uint32_t base_address;
uint32_t bank_size;
{
int retval;
struct at91sam7_flash_bank *at91sam7_info = bank->driver_priv;
- target_t *target = bank->target;
+ struct target *target = bank->target;
uint32_t dst_min_alignment, wcount, bytes_remaining = count;
uint32_t first_page, last_page, pagen, buffer_pos;
static int avrf_write(struct flash_bank_s *bank, uint8_t *buffer, uint32_t offset, uint32_t count)
{
- target_t *target = bank->target;
+ struct target *target = bank->target;
struct avr_common *avr = target->arch_info;
uint32_t cur_size, cur_buffer_size, page_size;
#define EXTRACT_VER(X) (((X) & 0xf0000000) >> 28)
static int avrf_probe(struct flash_bank_s *bank)
{
- target_t *target = bank->target;
+ struct target *target = bank->target;
struct avrf_flash_bank *avrf_info = bank->driver_priv;
struct avr_common *avr = target->arch_info;
struct avrf_type *avr_info = NULL;
static int avrf_info(struct flash_bank_s *bank, char *buf, int buf_size)
{
- target_t *target = bank->target;
+ struct target *target = bank->target;
struct avr_common *avr = target->arch_info;
struct avrf_type *avr_info = NULL;
int i;
static int avrf_mass_erase(struct flash_bank_s *bank)
{
- target_t *target = bank->target;
+ struct target *target = bank->target;
struct avr_common *avr = target->arch_info;
if (target->state != TARGET_HALTED)
*/
static uint8_t cfi_query_u8(flash_bank_t *bank, int sector, uint32_t offset)
{
- target_t *target = bank->target;
+ struct target *target = bank->target;
uint8_t data[CFI_MAX_BUS_WIDTH];
target_read_memory(target, flash_address(bank, sector, offset), bank->bus_width, 1, data);
*/
static uint8_t cfi_get_u8(flash_bank_t *bank, int sector, uint32_t offset)
{
- target_t *target = bank->target;
+ struct target *target = bank->target;
uint8_t data[CFI_MAX_BUS_WIDTH];
int i;
static uint16_t cfi_query_u16(flash_bank_t *bank, int sector, uint32_t offset)
{
- target_t *target = bank->target;
+ struct target *target = bank->target;
struct cfi_flash_bank *cfi_info = bank->driver_priv;
uint8_t data[CFI_MAX_BUS_WIDTH * 2];
static uint32_t cfi_query_u32(flash_bank_t *bank, int sector, uint32_t offset)
{
- target_t *target = bank->target;
+ struct target *target = bank->target;
struct cfi_flash_bank *cfi_info = bank->driver_priv;
uint8_t data[CFI_MAX_BUS_WIDTH * 4];
static void cfi_intel_clear_status_register(flash_bank_t *bank)
{
- target_t *target = bank->target;
+ struct target *target = bank->target;
uint8_t command[8];
if (target->state != TARGET_HALTED)
int retval;
struct cfi_flash_bank *cfi_info = bank->driver_priv;
struct cfi_intel_pri_ext *pri_ext = malloc(sizeof(struct cfi_intel_pri_ext));
- target_t *target = bank->target;
+ struct target *target = bank->target;
uint8_t command[8];
cfi_info->pri_ext = pri_ext;
int retval;
struct cfi_flash_bank *cfi_info = bank->driver_priv;
struct cfi_spansion_pri_ext *pri_ext = malloc(sizeof(struct cfi_spansion_pri_ext));
- target_t *target = bank->target;
+ struct target *target = bank->target;
uint8_t command[8];
cfi_info->pri_ext = pri_ext;
struct cfi_atmel_pri_ext atmel_pri_ext;
struct cfi_flash_bank *cfi_info = bank->driver_priv;
struct cfi_spansion_pri_ext *pri_ext = malloc(sizeof(struct cfi_spansion_pri_ext));
- target_t *target = bank->target;
+ struct target *target = bank->target;
uint8_t command[8];
/* ATMEL devices use the same CFI primary command set (0x2) as AMD/Spansion,
{
int retval;
struct cfi_flash_bank *cfi_info = bank->driver_priv;
- target_t *target = bank->target;
+ struct target *target = bank->target;
uint8_t command[8];
int i;
int retval;
struct cfi_flash_bank *cfi_info = bank->driver_priv;
struct cfi_spansion_pri_ext *pri_ext = cfi_info->pri_ext;
- target_t *target = bank->target;
+ struct target *target = bank->target;
uint8_t command[8];
int i;
int retval;
struct cfi_flash_bank *cfi_info = bank->driver_priv;
struct cfi_intel_pri_ext *pri_ext = cfi_info->pri_ext;
- target_t *target = bank->target;
+ struct target *target = bank->target;
uint8_t command[8];
int retry = 0;
int i;
/* FIXME Replace this by a simple memcpy() - still unsure about sideeffects */
static void cfi_add_byte(struct flash_bank_s *bank, uint8_t *word, uint8_t byte)
{
- /* target_t *target = bank->target; */
+ /* struct target *target = bank->target; */
int i;
/* Convert code image to target endian */
/* FIXME create general block conversion fcts in target.c?) */
-static void cfi_fix_code_endian(target_t *target, uint8_t *dest, const uint32_t *src, uint32_t count)
+static void cfi_fix_code_endian(struct target *target, uint8_t *dest, const uint32_t *src, uint32_t count)
{
uint32_t i;
for (i = 0; i< count; i++)
static uint32_t cfi_command_val(flash_bank_t *bank, uint8_t cmd)
{
- target_t *target = bank->target;
+ struct target *target = bank->target;
uint8_t buf[CFI_MAX_BUS_WIDTH];
cfi_command(bank, cmd, buf);
static int cfi_intel_write_block(struct flash_bank_s *bank, uint8_t *buffer, uint32_t address, uint32_t count)
{
struct cfi_flash_bank *cfi_info = bank->driver_priv;
- target_t *target = bank->target;
+ struct target *target = bank->target;
struct reg_param reg_params[7];
struct armv4_5_algorithm armv4_5_info;
struct working_area *source;
{
struct cfi_flash_bank *cfi_info = bank->driver_priv;
struct cfi_spansion_pri_ext *pri_ext = cfi_info->pri_ext;
- target_t *target = bank->target;
+ struct target *target = bank->target;
struct reg_param reg_params[10];
struct armv4_5_algorithm armv4_5_info;
struct working_area *source;
{
int retval;
struct cfi_flash_bank *cfi_info = bank->driver_priv;
- target_t *target = bank->target;
+ struct target *target = bank->target;
uint8_t command[8];
cfi_intel_clear_status_register(bank);
{
int retval;
struct cfi_flash_bank *cfi_info = bank->driver_priv;
- target_t *target = bank->target;
+ struct target *target = bank->target;
uint8_t command[8];
/* Calculate buffer size and boundary mask */
int retval;
struct cfi_flash_bank *cfi_info = bank->driver_priv;
struct cfi_spansion_pri_ext *pri_ext = cfi_info->pri_ext;
- target_t *target = bank->target;
+ struct target *target = bank->target;
uint8_t command[8];
cfi_command(bank, 0xaa, command);
{
int retval;
struct cfi_flash_bank *cfi_info = bank->driver_priv;
- target_t *target = bank->target;
+ struct target *target = bank->target;
uint8_t command[8];
struct cfi_spansion_pri_ext *pri_ext = cfi_info->pri_ext;
int cfi_write(struct flash_bank_s *bank, uint8_t *buffer, uint32_t offset, uint32_t count)
{
struct cfi_flash_bank *cfi_info = bank->driver_priv;
- target_t *target = bank->target;
+ struct target *target = bank->target;
uint32_t address = bank->base + offset; /* address of first byte to be programmed */
uint32_t write_p, copy_p;
int align; /* number of unaligned bytes */
static int cfi_query_string(struct flash_bank_s *bank, int address)
{
struct cfi_flash_bank *cfi_info = bank->driver_priv;
- target_t *target = bank->target;
+ struct target *target = bank->target;
int retval;
uint8_t command[8];
static int cfi_probe(struct flash_bank_s *bank)
{
struct cfi_flash_bank *cfi_info = bank->driver_priv;
- target_t *target = bank->target;
+ struct target *target = bank->target;
uint8_t command[8];
int num_sectors = 0;
int i;
int retval;
struct cfi_flash_bank *cfi_info = bank->driver_priv;
struct cfi_intel_pri_ext *pri_ext = cfi_info->pri_ext;
- target_t *target = bank->target;
+ struct target *target = bank->target;
uint8_t command[CFI_MAX_BUS_WIDTH];
int i;
int retval;
struct cfi_flash_bank *cfi_info = bank->driver_priv;
struct cfi_spansion_pri_ext *pri_ext = cfi_info->pri_ext;
- target_t *target = bank->target;
+ struct target *target = bank->target;
uint8_t command[8];
int i;
};
struct davinci_nand {
- target_t *target;
+ struct target *target;
uint8_t chipsel; /* chipselect 0..3 == CS2..CS5 */
uint8_t eccmode;
#define NANDERRADDR 0xd0 /* 4-bit ECC err addr, 1st of 2 */
#define NANDERRVAL 0xd8 /* 4-bit ECC err value, 1st of 2 */
-static int halted(target_t *target, const char *label)
+static int halted(struct target *target, const char *label)
{
if (target->state == TARGET_HALTED)
return true;
static int davinci_init(struct nand_device_s *nand)
{
struct davinci_nand *info = nand->controller_priv;
- target_t *target = info->target;
+ struct target *target = info->target;
uint32_t nandfcr;
if (!halted(target, "init"))
static int davinci_nand_ready(struct nand_device_s *nand, int timeout)
{
struct davinci_nand *info = nand->controller_priv;
- target_t *target = info->target;
+ struct target *target = info->target;
uint32_t nandfsr;
/* NOTE: return code is zero/error, else success; not ERROR_* */
static int davinci_command(struct nand_device_s *nand, uint8_t command)
{
struct davinci_nand *info = nand->controller_priv;
- target_t *target = info->target;
+ struct target *target = info->target;
if (!halted(target, "command"))
return ERROR_NAND_OPERATION_FAILED;
static int davinci_address(struct nand_device_s *nand, uint8_t address)
{
struct davinci_nand *info = nand->controller_priv;
- target_t *target = info->target;
+ struct target *target = info->target;
if (!halted(target, "address"))
return ERROR_NAND_OPERATION_FAILED;
static int davinci_write_data(struct nand_device_s *nand, uint16_t data)
{
struct davinci_nand *info = nand->controller_priv;
- target_t *target = info->target;
+ struct target *target = info->target;
if (!halted(target, "write_data"))
return ERROR_NAND_OPERATION_FAILED;
static int davinci_read_data(struct nand_device_s *nand, void *data)
{
struct davinci_nand *info = nand->controller_priv;
- target_t *target = info->target;
+ struct target *target = info->target;
if (!halted(target, "read_data"))
return ERROR_NAND_OPERATION_FAILED;
uint8_t *data, int data_size)
{
struct davinci_nand *info = nand->controller_priv;
- target_t *target = info->target;
+ struct target *target = info->target;
uint32_t nfdata = info->data;
uint32_t tmp;
uint8_t *data, int data_size)
{
struct davinci_nand *info = nand->controller_priv;
- target_t *target = info->target;
+ struct target *target = info->target;
uint32_t nfdata = info->data;
uint32_t tmp;
int status;
static void davinci_write_pagecmd(struct nand_device_s *nand, uint8_t cmd, uint32_t page)
{
struct davinci_nand *info = nand->controller_priv;
- target_t *target = info->target;
+ struct target *target = info->target;
int page3 = nand->address_cycles - (nand->page_size == 512);
/* write command ({page,otp}x{read,program} */
uint8_t *oob, uint32_t oob_size)
{
struct davinci_nand *info = nand->controller_priv;
- target_t *target = info->target;
+ struct target *target = info->target;
uint8_t status;
if (oob_size)
{
unsigned oob_offset;
struct davinci_nand *info = nand->controller_priv;
- target_t *target = info->target;
+ struct target *target = info->target;
const uint32_t fcr_addr = info->aemif + NANDFCR;
const uint32_t ecc1_addr = info->aemif + NANDFECC + (4 * info->chipsel);
uint32_t fcr, ecc1;
struct davinci_nand *info = nand->controller_priv;
const uint8_t *l;
- target_t *target = info->target;
+ struct target *target = info->target;
const uint32_t fcr_addr = info->aemif + NANDFCR;
const uint32_t ecc4_addr = info->aemif + NAND4BITECC;
uint32_t fcr, ecc4;
uint8_t *data, uint32_t data_size, uint8_t *oob, uint32_t oob_size)
{
struct davinci_nand *info = nand->controller_priv;
- target_t *target = info->target;
+ struct target *target = info->target;
const uint32_t fcr_addr = info->aemif + NANDFCR;
const uint32_t ecc4_addr = info->aemif + NAND4BITECC;
uint32_t fcr, ecc4;
NAND_DEVICE_COMMAND_HANDLER(davinci_nand_device_command)
{
struct davinci_nand *info;
- target_t *target;
+ struct target *target;
unsigned long chip, aemif;
enum ecc eccmode;
int chipsel;
struct ecosflash_flash_bank
{
- struct target_s *target;
+ struct target *target;
struct working_area *write_algorithm;
struct working_area *erase_check_algorithm;
char *driverPath;
image.base_address_set = 0;
image.start_address_set = 0;
- target_t *target = info->target;
+ struct target *target = info->target;
int retval;
if ((retval = image_open(&image, info->driverPath, NULL)) != ERROR_OK)
/* timeout in ms */
int timeout)
{
- target_t *target = info->target;
+ struct target *target = info->target;
struct reg_param reg_params[3];
struct armv4_5_algorithm armv4_5_info;
static int eCosBoard_flash(struct ecosflash_flash_bank *info, void *data, uint32_t address, uint32_t len)
{
- target_t *target = info->target;
+ struct target *target = info->target;
const int chunk = 8192;
int retval = ERROR_OK;
int timeout = (chunk / 20480 + 1) * 1000; /*asume 20 KB/s + 1 second*/
struct faux_flash_bank
{
- struct target_s *target;
+ struct target *target;
uint8_t *memory;
uint32_t start_address;
};
#include "image.h"
#include "time_support.h"
-static int flash_write_unlock(target_t *target, struct image *image, uint32_t *written, int erase, bool unlock);
+static int flash_write_unlock(struct target *target, struct image *image, uint32_t *written, int erase, bool unlock);
/* flash drivers
*/
int retval;
int i;
int found = 0;
- target_t *target;
+ struct target *target;
if (argc < 6)
{
int address;
int length;
- target_t *target = get_current_target(cmd_ctx);
+ struct target *target = get_current_target(cmd_ctx);
if (argc != 2)
return ERROR_COMMAND_SYNTAX_ERROR;
COMMAND_HANDLER(handle_flash_write_image_command)
{
- target_t *target = get_current_target(cmd_ctx);
+ struct target *target = get_current_target(cmd_ctx);
struct image image;
uint32_t written;
uint32_t wrote = 0;
uint32_t cur_size = 0;
uint32_t chunk_count;
- target_t *target = get_current_target(cmd_ctx);
+ struct target *target = get_current_target(cmd_ctx);
uint32_t i;
uint32_t wordsize;
}
/* lookup flash bank by address */
-flash_bank_t *get_flash_bank_by_addr(target_t *target, uint32_t addr)
+struct flash_bank_s *get_flash_bank_by_addr(struct target *target, uint32_t addr)
{
flash_bank_t *c;
}
/* erase given flash region, selects proper bank according to target and address */
-static int flash_iterate_address_range(target_t *target, uint32_t addr, uint32_t length,
+static int flash_iterate_address_range(struct target *target, uint32_t addr, uint32_t length,
int (*callback)(struct flash_bank_s *bank, int first, int last))
{
flash_bank_t *c;
-int flash_erase_address_range(target_t *target, uint32_t addr, uint32_t length)
+int flash_erase_address_range(struct target *target, uint32_t addr, uint32_t length)
{
return flash_iterate_address_range(target, addr, length, &flash_driver_erase);
}
return flash_driver_protect(bank, 0, first, last);
}
-static int flash_unlock_address_range(target_t *target, uint32_t addr, uint32_t length)
+static int flash_unlock_address_range(struct target *target, uint32_t addr, uint32_t length)
{
return flash_iterate_address_range(target, addr, length, &flash_driver_unprotect);
}
/* write (optional verify) an image to flash memory of the given target */
-static int flash_write_unlock(target_t *target, struct image *image, uint32_t *written, int erase, bool unlock)
+static int flash_write_unlock(struct target *target, struct image *image, uint32_t *written, int erase, bool unlock)
{
int retval = ERROR_OK;
return retval;
}
-int flash_write(target_t *target, struct image *image, uint32_t *written, int erase)
+int flash_write(struct target *target, struct image *image, uint32_t *written, int erase)
{
return flash_write_unlock(target, image, written, erase, false);
}
int default_flash_mem_blank_check(struct flash_bank_s *bank)
{
- target_t *target = bank->target;
+ struct target *target = bank->target;
uint8_t buffer[1024];
int buffer_size = sizeof(buffer);
int i;
int default_flash_blank_check(struct flash_bank_s *bank)
{
- target_t *target = bank->target;
+ struct target *target = bank->target;
int i;
int retval;
int fast_check = 0;
*/
typedef struct flash_bank_s
{
- struct target_s *target; /**< Target to which this bank belongs. */
+ struct target *target; /**< Target to which this bank belongs. */
struct flash_driver *driver; /**< Driver for this bank. */
void *driver_priv; /**< Private driver storage pointer */
* Erases @a length bytes in the @a target flash, starting at @a addr.
* @returns ERROR_OK if successful; otherwise, an error code.
*/
-int flash_erase_address_range(struct target_s *target,
+int flash_erase_address_range(struct target *target,
uint32_t addr, uint32_t length);
/**
* Writes @a image into the @a target flash. The @a written parameter
* erase the corresponding banks or sectors before programming.
* @returns ERROR_OK if successful; otherwise, an error code.
*/
-int flash_write(struct target_s *target,
+int flash_write(struct target *target,
struct image *image, uint32_t *written, int erase);
/**
* Forces targets to re-examine their erase/protection state.
* @param addr An address that is within the range of the bank.
* @returns The flash_bank_t located at @a addr, or NULL.
*/
-flash_bank_t *get_flash_bank_by_addr(struct target_s *target, uint32_t addr);
+struct flash_bank_s *get_flash_bank_by_addr(struct target *target, uint32_t addr);
#define ERROR_FLASH_BANK_INVALID (-900)
#define ERROR_FLASH_SECTOR_INVALID (-901)
{
int retval;
struct lpc2000_flash_bank *lpc2000_info = bank->driver_priv;
- target_t *target = bank->target;
+ struct target *target = bank->target;
struct mem_param mem_params[2];
struct reg_param reg_params[5];
struct armv4_5_algorithm armv4_5_info; /* for LPC2000 */
static int lpc2000_write(struct flash_bank_s *bank, uint8_t *buffer, uint32_t offset, uint32_t count)
{
struct lpc2000_flash_bank *lpc2000_info = bank->driver_priv;
- target_t *target = bank->target;
+ struct target *target = bank->target;
uint32_t dst_min_alignment;
uint32_t bytes_remaining = count;
uint32_t bytes_written = 0;
/* F_CLK_TIME */
#define FCT_CLK_DIV_MASK 0x0FFF
-static uint32_t lpc288x_wait_status_busy(flash_bank_t *bank, int timeout);
-static void lpc288x_load_timer(int erase, struct target_s *target);
+static uint32_t lpc288x_wait_status_busy(struct flash_bank_s *bank, int timeout);
+static void lpc288x_load_timer(int erase, struct target *target);
static void lpc288x_set_flash_clk(struct flash_bank_s *bank);
static uint32_t lpc288x_system_ready(struct flash_bank_s *bank);
static uint32_t lpc288x_wait_status_busy(flash_bank_t *bank, int timeout)
{
uint32_t status;
- target_t *target = bank->target;
+ struct target *target = bank->target;
do
{
alive_sleep(1);
static int lpc288x_read_part_info(struct flash_bank_s *bank)
{
struct lpc288x_flash_bank *lpc288x_info = bank->driver_priv;
- target_t *target = bank->target;
+ struct target *target = bank->target;
uint32_t cidr;
int i = 0;
* LOAD_TIMER_WRITE FPT_TIME = ((1,000,000 / AHB tcyc (in ns)) - 2) / 512
* = 23 (75) (AN10548 72 - is this wrong?)
* TODO: Sort out timing calcs ;) */
-static void lpc288x_load_timer(int erase, struct target_s *target)
+static void lpc288x_load_timer(int erase, struct target *target)
{
if (erase == LOAD_TIMER_ERASE)
{
{
uint32_t status;
int sector;
- target_t *target = bank->target;
+ struct target *target = bank->target;
status = lpc288x_system_ready(bank); /* probed? halted? */
if (status != ERROR_OK)
{
uint8_t page_buffer[FLASH_PAGE_SIZE];
uint32_t status, source_offset,dest_offset;
- target_t *target = bank->target;
+ struct target *target = bank->target;
uint32_t bytes_remaining = count;
uint32_t first_sector, last_sector, sector, page;
int i;
{
int lockregion, status;
uint32_t value;
- target_t *target = bank->target;
+ struct target *target = bank->target;
/* probed? halted? */
status = lpc288x_system_ready(bank);
int timeout )
{
uint32_t int_status;
- target_t *target = bank->target;
+ struct target *target = bank->target;
do
return status;
}
- target_t *target = bank->target;
+ struct target *target = bank->target;
/* Enable ISS access */
target_write_u32(target, FCTR, FCTR_FS_CS | FCTR_FS_WEB | FCTR_FS_ISS);
uint32_t addr_to,
uint32_t (*signature)[4] )
{
- target_t *target = bank->target;
+ struct target *target = bank->target;
/* Clear END_OF_MISR interrupt status */
target_write_u32( target, INT_CLR_STATUS, INTSRC_END_OF_MISR );
}
/* Get target, and check if it's halted */
- target_t *target = bank->target;
+ struct target *target = bank->target;
if( target->state != TARGET_HALTED )
{
LOG_ERROR( "Target not halted" );
lpc2900_info->risky = 0;
/* Get target, and check if it's halted */
- target_t *target = bank->target;
+ struct target *target = bank->target;
if( target->state != TARGET_HALTED )
{
LOG_ERROR( "Target not halted" );
lpc2900_info->risky = 0;
/* Get target, and check if it's halted */
- target_t *target = bank->target;
+ struct target *target = bank->target;
if (target->state != TARGET_HALTED)
{
LOG_ERROR("Target not halted");
uint32_t status;
int sector;
int last_unsecured_sector;
- target_t *target = bank->target;
+ struct target *target = bank->target;
struct lpc2900_flash_bank *lpc2900_info = bank->driver_priv;
uint8_t page[FLASH_PAGE_SIZE];
uint32_t status;
uint32_t num_bytes;
- target_t *target = bank->target;
+ struct target *target = bank->target;
struct lpc2900_flash_bank *lpc2900_info = bank->driver_priv;
int sector;
int retval;
static int lpc2900_probe(struct flash_bank_s *bank)
{
struct lpc2900_flash_bank *lpc2900_info = bank->driver_priv;
- target_t *target = bank->target;
+ struct target *target = bank->target;
int i = 0;
uint32_t offset;
return ERROR_FLASH_BANK_INVALID;
}
- target_t *target = get_target(args[1]);
+ struct target *target = get_target(args[1]);
if (NULL == target)
{
LOG_ERROR("target '%s' not defined", args[1]);
static float lpc3180_cycle_time(struct lpc3180_nand_controller *lpc3180_info)
{
- target_t *target = lpc3180_info->target;
+ struct target *target = lpc3180_info->target;
uint32_t sysclk_ctrl, pwr_ctrl, hclkdiv_ctrl, hclkpll_ctrl;
int sysclk;
int hclk;
static int lpc3180_init(struct nand_device_s *nand)
{
struct lpc3180_nand_controller *lpc3180_info = nand->controller_priv;
- target_t *target = lpc3180_info->target;
+ struct target *target = lpc3180_info->target;
int bus_width = nand->bus_width ? : 8;
int address_cycles = nand->address_cycles ? : 3;
int page_size = nand->page_size ? : 512;
static int lpc3180_reset(struct nand_device_s *nand)
{
struct lpc3180_nand_controller *lpc3180_info = nand->controller_priv;
- target_t *target = lpc3180_info->target;
+ struct target *target = lpc3180_info->target;
if (target->state != TARGET_HALTED)
{
static int lpc3180_command(struct nand_device_s *nand, uint8_t command)
{
struct lpc3180_nand_controller *lpc3180_info = nand->controller_priv;
- target_t *target = lpc3180_info->target;
+ struct target *target = lpc3180_info->target;
if (target->state != TARGET_HALTED)
{
static int lpc3180_address(struct nand_device_s *nand, uint8_t address)
{
struct lpc3180_nand_controller *lpc3180_info = nand->controller_priv;
- target_t *target = lpc3180_info->target;
+ struct target *target = lpc3180_info->target;
if (target->state != TARGET_HALTED)
{
static int lpc3180_write_data(struct nand_device_s *nand, uint16_t data)
{
struct lpc3180_nand_controller *lpc3180_info = nand->controller_priv;
- target_t *target = lpc3180_info->target;
+ struct target *target = lpc3180_info->target;
if (target->state != TARGET_HALTED)
{
static int lpc3180_read_data(struct nand_device_s *nand, void *data)
{
struct lpc3180_nand_controller *lpc3180_info = nand->controller_priv;
- target_t *target = lpc3180_info->target;
+ struct target *target = lpc3180_info->target;
if (target->state != TARGET_HALTED)
{
static int lpc3180_write_page(struct nand_device_s *nand, uint32_t page, uint8_t *data, uint32_t data_size, uint8_t *oob, uint32_t oob_size)
{
struct lpc3180_nand_controller *lpc3180_info = nand->controller_priv;
- target_t *target = lpc3180_info->target;
+ struct target *target = lpc3180_info->target;
int retval;
uint8_t status;
static int lpc3180_read_page(struct nand_device_s *nand, uint32_t page, uint8_t *data, uint32_t data_size, uint8_t *oob, uint32_t oob_size)
{
struct lpc3180_nand_controller *lpc3180_info = nand->controller_priv;
- target_t *target = lpc3180_info->target;
+ struct target *target = lpc3180_info->target;
if (target->state != TARGET_HALTED)
{
static int lpc3180_controller_ready(struct nand_device_s *nand, int timeout)
{
struct lpc3180_nand_controller *lpc3180_info = nand->controller_priv;
- target_t *target = lpc3180_info->target;
+ struct target *target = lpc3180_info->target;
uint8_t status = 0x0;
if (target->state != TARGET_HALTED)
static int lpc3180_nand_ready(struct nand_device_s *nand, int timeout)
{
struct lpc3180_nand_controller *lpc3180_info = nand->controller_priv;
- target_t *target = lpc3180_info->target;
+ struct target *target = lpc3180_info->target;
if (target->state != TARGET_HALTED)
{
struct lpc3180_nand_controller
{
- struct target_s *target;
+ struct target *target;
int osc_freq;
enum lpc3180_selected_controller selected_controller;
int sw_write_protection;
static int pxa270_set_gpio_to_output (struct mflash_gpio_num gpio)
{
uint32_t addr, value, mask;
- target_t *target = mflash_bank->target;
+ struct target *target = mflash_bank->target;
int ret;
/* remove alternate function. */
static int pxa270_set_gpio_output_val (struct mflash_gpio_num gpio, uint8_t val)
{
uint32_t addr, value, mask;
- target_t *target = mflash_bank->target;
+ struct target *target = mflash_bank->target;
int ret;
mask = 0x1u << (gpio.num & 0x1F);
static int s3c2440_set_gpio_to_output (struct mflash_gpio_num gpio)
{
uint32_t data, mask, gpio_con;
- target_t *target = mflash_bank->target;
+ struct target *target = mflash_bank->target;
int ret;
if (gpio.port[0] >= 'a' && gpio.port[0] <= 'h') {
static int s3c2440_set_gpio_output_val (struct mflash_gpio_num gpio, uint8_t val)
{
uint32_t data, mask, gpio_dat;
- target_t *target = mflash_bank->target;
+ struct target *target = mflash_bank->target;
int ret;
if (gpio.port[0] >= 'a' && gpio.port[0] <= 'h') {
static int mg_dsk_wait(mg_io_type_wait wait, uint32_t time)
{
uint8_t status, error;
- target_t *target = mflash_bank->target;
+ struct target *target = mflash_bank->target;
uint32_t mg_task_reg = mflash_bank->base + MG_REG_OFFSET;
int ret;
long long t = 0;
static int mg_dsk_srst(uint8_t on)
{
- target_t *target = mflash_bank->target;
+ struct target *target = mflash_bank->target;
uint32_t mg_task_reg = mflash_bank->base + MG_REG_OFFSET;
uint8_t value;
int ret;
static int mg_dsk_io_cmd(uint32_t sect_num, uint32_t cnt, uint8_t cmd)
{
- target_t *target = mflash_bank->target;
+ struct target *target = mflash_bank->target;
uint32_t mg_task_reg = mflash_bank->base + MG_REG_OFFSET;
uint8_t value;
int ret;
static int mg_dsk_drv_info(void)
{
- target_t *target = mflash_bank->target;
+ struct target *target = mflash_bank->target;
uint32_t mg_buff = mflash_bank->base + MG_BUFFER_OFFSET;
int ret;
{
uint32_t i, address;
int ret;
- target_t *target = mflash_bank->target;
+ struct target *target = mflash_bank->target;
uint8_t *buff_ptr = buff;
if ((ret = mg_dsk_io_cmd(sect_num, sect_cnt, mg_io_cmd_read)) != ERROR_OK)
{
uint32_t i, address;
int ret;
- target_t *target = mflash_bank->target;
+ struct target *target = mflash_bank->target;
uint8_t *buff_ptr = buff;
if ((ret = mg_dsk_io_cmd(sect_num, sect_cnt, cmd)) != ERROR_OK)
static int mg_set_feature(mg_feature_id feature, mg_feature_val config)
{
- target_t *target = mflash_bank->target;
+ struct target *target = mflash_bank->target;
uint32_t mg_task_reg = mflash_bank->base + MG_REG_OFFSET;
int ret;
uint16_t buff[MG_MFLASH_SECTOR_SIZE >> 1];
uint16_t i, j;
uint32_t address = mflash_bank->base + MG_BUFFER_OFFSET;
- target_t *target = mflash_bank->target;
+ struct target *target = mflash_bank->target;
int ret;
for (j = 0; j < 10; j++) {
COMMAND_HANDLER(mg_bank_cmd)
{
- target_t *target;
+ struct target *target;
int i;
if (argc < 4)
struct mflash_gpio_num rst_pin;
struct mflash_gpio_drv *gpio_drv;
- target_t *target;
+ struct target *target;
struct mg_drv_info *drv_info;
};
static uint32_t in_sram_address;
unsigned char sign_of_sequental_byte_read;
-static int test_iomux_settings (target_t * target, uint32_t value,
+static int test_iomux_settings (struct target * target, uint32_t value,
uint32_t mask, const char *text);
static int initialize_nf_controller (struct nand_device_s *nand);
-static int get_next_byte_from_sram_buffer (target_t * target, uint8_t * value);
-static int get_next_halfword_from_sram_buffer (target_t * target,
+static int get_next_byte_from_sram_buffer (struct target * target, uint8_t * value);
+static int get_next_halfword_from_sram_buffer (struct target * target,
uint16_t * value);
-static int poll_for_complete_op (target_t * target, const char *text);
+static int poll_for_complete_op (struct target * target, const char *text);
static int validate_target_state (struct nand_device_s *nand);
static int do_data_output (struct nand_device_s *nand);
static int imx31_init (struct nand_device_s *nand)
{
struct mx3_nf_controller *mx3_nf_info = nand->controller_priv;
- target_t *target = mx3_nf_info->target;
+ struct target *target = mx3_nf_info->target;
{
/*
static int imx31_read_data (struct nand_device_s *nand, void *data)
{
struct mx3_nf_controller *mx3_nf_info = nand->controller_priv;
- target_t *target = mx3_nf_info->target;
+ struct target *target = mx3_nf_info->target;
{
/*
* validate target state
static int imx31_command (struct nand_device_s *nand, uint8_t command)
{
struct mx3_nf_controller *mx3_nf_info = nand->controller_priv;
- target_t *target = mx3_nf_info->target;
+ struct target *target = mx3_nf_info->target;
{
/*
* validate target state
static int imx31_address (struct nand_device_s *nand, uint8_t address)
{
struct mx3_nf_controller *mx3_nf_info = nand->controller_priv;
- target_t *target = mx3_nf_info->target;
+ struct target *target = mx3_nf_info->target;
{
/*
* validate target state
{
uint16_t poll_complete_status;
struct mx3_nf_controller *mx3_nf_info = nand->controller_priv;
- target_t *target = mx3_nf_info->target;
+ struct target *target = mx3_nf_info->target;
{
/*
uint32_t oob_size)
{
struct mx3_nf_controller *mx3_nf_info = nand->controller_priv;
- target_t *target = mx3_nf_info->target;
+ struct target *target = mx3_nf_info->target;
if (data_size % 2)
{
uint32_t oob_size)
{
struct mx3_nf_controller *mx3_nf_info = nand->controller_priv;
- target_t *target = mx3_nf_info->target;
+ struct target *target = mx3_nf_info->target;
if (data_size % 2)
{
return ERROR_OK;
}
-static int test_iomux_settings (target_t * target, uint32_t address,
+static int test_iomux_settings (struct target * target, uint32_t address,
uint32_t mask, const char *text)
{
uint32_t register_content;
static int initialize_nf_controller (struct nand_device_s *nand)
{
struct mx3_nf_controller *mx3_nf_info = nand->controller_priv;
- target_t *target = mx3_nf_info->target;
+ struct target *target = mx3_nf_info->target;
/*
* resets NAND flash controller in zero time ? I dont know.
*/
return ERROR_OK;
}
-static int get_next_byte_from_sram_buffer (target_t * target, uint8_t * value)
+static int get_next_byte_from_sram_buffer (struct target * target, uint8_t * value)
{
static uint8_t even_byte = 0;
/*
return ERROR_OK;
}
-static int get_next_halfword_from_sram_buffer (target_t * target,
+static int get_next_halfword_from_sram_buffer (struct target * target,
uint16_t * value)
{
if (in_sram_address > MX3_NF_LAST_BUFFER_ADDR)
return ERROR_OK;
}
-static int poll_for_complete_op (target_t * target, const char *text)
+static int poll_for_complete_op (struct target * target, const char *text)
{
uint16_t poll_complete_status;
for (int poll_cycle_count = 0; poll_cycle_count < 100; poll_cycle_count++)
static int validate_target_state (struct nand_device_s *nand)
{
struct mx3_nf_controller *mx3_nf_info = nand->controller_priv;
- target_t *target = mx3_nf_info->target;
+ struct target *target = mx3_nf_info->target;
if (target->state != TARGET_HALTED)
{
static int do_data_output (struct nand_device_s *nand)
{
struct mx3_nf_controller *mx3_nf_info = nand->controller_priv;
- target_t *target = mx3_nf_info->target;
+ struct target *target = mx3_nf_info->target;
switch (mx3_nf_info->fin)
{
case MX3_NF_FIN_DATAOUT:
struct mx3_nf_controller
{
- struct target_s *target;
+ struct target *target;
enum mx_dataout_type optype;
enum mx_nf_finalize_action fin;
struct mx3_nf_flags flags;
struct orion_nand_controller
{
- struct target_s *target;
+ struct target *target;
struct arm_nand_data io;
static int orion_nand_command(struct nand_device_s *nand, uint8_t command)
{
struct orion_nand_controller *hw = nand->controller_priv;
- target_t *target = hw->target;
+ struct target *target = hw->target;
CHECK_HALTED;
target_write_u8(target, hw->cmd, command);
static int orion_nand_address(struct nand_device_s *nand, uint8_t address)
{
struct orion_nand_controller *hw = nand->controller_priv;
- target_t *target = hw->target;
+ struct target *target = hw->target;
CHECK_HALTED;
target_write_u8(target, hw->addr, address);
static int orion_nand_read(struct nand_device_s *nand, void *data)
{
struct orion_nand_controller *hw = nand->controller_priv;
- target_t *target = hw->target;
+ struct target *target = hw->target;
CHECK_HALTED;
target_read_u8(target, hw->data, data);
static int orion_nand_write(struct nand_device_s *nand, uint16_t data)
{
struct orion_nand_controller *hw = nand->controller_priv;
- target_t *target = hw->target;
+ struct target *target = hw->target;
CHECK_HALTED;
target_write_u8(target, hw->data, data);
static uint32_t pic32mx_get_flash_status(flash_bank_t *bank)
{
- target_t *target = bank->target;
+ struct target *target = bank->target;
uint32_t status;
target_read_u32(target, PIC32MX_NVMCON, &status);
static int pic32mx_nvm_exec(struct flash_bank_s *bank, uint32_t op, uint32_t timeout)
{
- target_t *target = bank->target;
+ struct target *target = bank->target;
uint32_t status;
target_write_u32(target, PIC32MX_NVMCON, NVMCON_NVMWREN | op);
static int pic32mx_protect_check(struct flash_bank_s *bank)
{
- target_t *target = bank->target;
+ struct target *target = bank->target;
uint32_t devcfg0;
int s;
static int pic32mx_erase(struct flash_bank_s *bank, int first, int last)
{
- target_t *target = bank->target;
+ struct target *target = bank->target;
int i;
uint32_t status;
static int pic32mx_protect(struct flash_bank_s *bank, int set, int first, int last)
{
struct pic32mx_flash_bank *pic32mx_info = NULL;
- target_t *target = bank->target;
+ struct target *target = bank->target;
#if 0
uint16_t prot_reg[4] = {0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF};
int i, reg, bit;
static int pic32mx_write_block(struct flash_bank_s *bank, uint8_t *buffer, uint32_t offset, uint32_t count)
{
- target_t *target = bank->target;
+ struct target *target = bank->target;
uint32_t buffer_size = 512;
struct working_area *source;
uint32_t address = bank->base + offset;
static int pic32mx_write_word(struct flash_bank_s *bank, uint32_t address, uint32_t word)
{
- target_t *target = bank->target;
+ struct target *target = bank->target;
if (bank->base >= PIC32MX_KSEG1_PGM_FLASH)
target_write_u32(target, PIC32MX_NVMADDR, KS1Virt2Phys(address));
*/
static int pic32mx_write_row(struct flash_bank_s *bank, uint32_t address, uint32_t srcaddr)
{
- target_t *target = bank->target;
+ struct target *target = bank->target;
LOG_DEBUG("addr: 0x%08" PRIx32 " srcaddr: 0x%08" PRIx32 "", address, srcaddr);
static int pic32mx_probe(struct flash_bank_s *bank)
{
- target_t *target = bank->target;
+ struct target *target = bank->target;
struct pic32mx_flash_bank *pic32mx_info = bank->driver_priv;
struct mips32_common *mips32 = target->arch_info;
struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
static int pic32mx_info(struct flash_bank_s *bank, char *buf, int buf_size)
{
- target_t *target = bank->target;
+ struct target *target = bank->target;
struct mips32_common *mips32 = target->arch_info;
struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
uint32_t device_id;
#if 0
COMMAND_HANDLER(pic32mx_handle_lock_command)
{
- target_t *target = NULL;
+ struct target *target = NULL;
struct pic32mx_flash_bank *pic32mx_info = NULL;
if (argc < 1)
COMMAND_HANDLER(pic32mx_handle_unlock_command)
{
- target_t *target = NULL;
+ struct target *target = NULL;
struct pic32mx_flash_bank *pic32mx_info = NULL;
if (argc < 1)
#if 0
static int pic32mx_chip_erase(struct flash_bank_s *bank)
{
- target_t *target = bank->target;
+ struct target *target = bank->target;
#if 0
uint32_t status;
#endif
static int s3c2410_init(struct nand_device_s *nand)
{
struct s3c24xx_nand_controller *s3c24xx_info = nand->controller_priv;
- target_t *target = s3c24xx_info->target;
+ struct target *target = s3c24xx_info->target;
target_write_u32(target, S3C2410_NFCONF,
S3C2410_NFCONF_EN | S3C2410_NFCONF_TACLS(3) |
static int s3c2410_write_data(struct nand_device_s *nand, uint16_t data)
{
struct s3c24xx_nand_controller *s3c24xx_info = nand->controller_priv;
- target_t *target = s3c24xx_info->target;
+ struct target *target = s3c24xx_info->target;
if (target->state != TARGET_HALTED) {
LOG_ERROR("target must be halted to use S3C24XX NAND flash controller");
static int s3c2410_read_data(struct nand_device_s *nand, void *data)
{
struct s3c24xx_nand_controller *s3c24xx_info = nand->controller_priv;
- target_t *target = s3c24xx_info->target;
+ struct target *target = s3c24xx_info->target;
if (target->state != TARGET_HALTED) {
LOG_ERROR("target must be halted to use S3C24XX NAND flash controller");
static int s3c2410_nand_ready(struct nand_device_s *nand, int timeout)
{
struct s3c24xx_nand_controller *s3c24xx_info = nand->controller_priv;
- target_t *target = s3c24xx_info->target;
+ struct target *target = s3c24xx_info->target;
uint8_t status;
if (target->state != TARGET_HALTED) {
static int s3c2412_init(struct nand_device_s *nand)
{
struct s3c24xx_nand_controller *s3c24xx_info = nand->controller_priv;
- target_t *target = s3c24xx_info->target;
+ struct target *target = s3c24xx_info->target;
target_write_u32(target, S3C2410_NFCONF,
S3C2440_NFCONF_TACLS(3) |
static int s3c2440_init(struct nand_device_s *nand)
{
struct s3c24xx_nand_controller *s3c24xx_info = nand->controller_priv;
- target_t *target = s3c24xx_info->target;
+ struct target *target = s3c24xx_info->target;
target_write_u32(target, S3C2410_NFCONF,
S3C2440_NFCONF_TACLS(3) |
int s3c2440_nand_ready(struct nand_device_s *nand, int timeout)
{
struct s3c24xx_nand_controller *s3c24xx_info = nand->controller_priv;
- target_t *target = s3c24xx_info->target;
+ struct target *target = s3c24xx_info->target;
uint8_t status;
if (target->state != TARGET_HALTED) {
int s3c2440_read_block_data(struct nand_device_s *nand, uint8_t *data, int data_size)
{
struct s3c24xx_nand_controller *s3c24xx_info = nand->controller_priv;
- target_t *target = s3c24xx_info->target;
+ struct target *target = s3c24xx_info->target;
uint32_t nfdata = s3c24xx_info->data;
uint32_t tmp;
int s3c2440_write_block_data(struct nand_device_s *nand, uint8_t *data, int data_size)
{
struct s3c24xx_nand_controller *s3c24xx_info = nand->controller_priv;
- target_t *target = s3c24xx_info->target;
+ struct target *target = s3c24xx_info->target;
uint32_t nfdata = s3c24xx_info->data;
uint32_t tmp;
static int s3c2443_init(struct nand_device_s *nand)
{
struct s3c24xx_nand_controller *s3c24xx_info = nand->controller_priv;
- target_t *target = s3c24xx_info->target;
+ struct target *target = s3c24xx_info->target;
target_write_u32(target, S3C2410_NFCONF,
S3C2440_NFCONF_TACLS(3) |
int s3c24xx_reset(struct nand_device_s *nand)
{
struct s3c24xx_nand_controller *s3c24xx_info = nand->controller_priv;
- target_t *target = s3c24xx_info->target;
+ struct target *target = s3c24xx_info->target;
if (target->state != TARGET_HALTED) {
LOG_ERROR("target must be halted to use S3C24XX NAND flash controller");
int s3c24xx_command(struct nand_device_s *nand, uint8_t command)
{
struct s3c24xx_nand_controller *s3c24xx_info = nand->controller_priv;
- target_t *target = s3c24xx_info->target;
+ struct target *target = s3c24xx_info->target;
if (target->state != TARGET_HALTED) {
LOG_ERROR("target must be halted to use S3C24XX NAND flash controller");
int s3c24xx_address(struct nand_device_s *nand, uint8_t address)
{
struct s3c24xx_nand_controller *s3c24xx_info = nand->controller_priv;
- target_t *target = s3c24xx_info->target;
+ struct target *target = s3c24xx_info->target;
if (target->state != TARGET_HALTED) {
LOG_ERROR("target must be halted to use S3C24XX NAND flash controller");
int s3c24xx_write_data(struct nand_device_s *nand, uint16_t data)
{
struct s3c24xx_nand_controller *s3c24xx_info = nand->controller_priv;
- target_t *target = s3c24xx_info->target;
+ struct target *target = s3c24xx_info->target;
if (target->state != TARGET_HALTED) {
LOG_ERROR("target must be halted to use S3C24XX NAND flash controller");
int s3c24xx_read_data(struct nand_device_s *nand, void *data)
{
struct s3c24xx_nand_controller *s3c24xx_info = nand->controller_priv;
- target_t *target = s3c24xx_info->target;
+ struct target *target = s3c24xx_info->target;
if (target->state != TARGET_HALTED) {
LOG_ERROR("target must be halted to use S3C24XX NAND flash controller");
struct s3c24xx_nand_controller
{
- struct target_s *target;
+ struct target *target;
/* register addresses */
uint32_t cmd;
static uint32_t stellaris_get_flash_status(flash_bank_t *bank)
{
- target_t *target = bank->target;
+ struct target *target = bank->target;
uint32_t fmc;
target_read_u32(target, FLASH_CONTROL_BASE | FLASH_FMC, &fmc);
static void stellaris_read_clock_info(flash_bank_t *bank)
{
struct stellaris_flash_bank *stellaris_info = bank->driver_priv;
- target_t *target = bank->target;
+ struct target *target = bank->target;
uint32_t rcc, rcc2, pllcfg, sysdiv, usesysdiv, bypass, oscsrc;
unsigned xtal;
unsigned long mainfreq;
static void stellaris_set_flash_mode(flash_bank_t *bank,int mode)
{
struct stellaris_flash_bank *stellaris_info = bank->driver_priv;
- target_t *target = bank->target;
+ struct target *target = bank->target;
uint32_t usecrl = (stellaris_info->mck_freq/1000000ul-1);
LOG_DEBUG("usecrl = %i",(int)(usecrl));
static int stellaris_flash_command(struct flash_bank_s *bank,uint8_t cmd,uint16_t pagen)
{
uint32_t fmc;
- target_t *target = bank->target;
+ struct target *target = bank->target;
fmc = FMC_WRKEY | cmd;
target_write_u32(target, FLASH_CONTROL_BASE | FLASH_FMC, fmc);
static int stellaris_read_part_info(struct flash_bank_s *bank)
{
struct stellaris_flash_bank *stellaris_info = bank->driver_priv;
- target_t *target = bank->target;
+ struct target *target = bank->target;
uint32_t did0, did1, ver, fam, status;
int i;
int banknr;
uint32_t flash_fmc, flash_cris;
struct stellaris_flash_bank *stellaris_info = bank->driver_priv;
- target_t *target = bank->target;
+ struct target *target = bank->target;
if (bank->target->state != TARGET_HALTED)
{
int lockregion;
struct stellaris_flash_bank *stellaris_info = bank->driver_priv;
- target_t *target = bank->target;
+ struct target *target = bank->target;
if (bank->target->state != TARGET_HALTED)
{
static int stellaris_write_block(struct flash_bank_s *bank, uint8_t *buffer, uint32_t offset, uint32_t wcount)
{
- target_t *target = bank->target;
+ struct target *target = bank->target;
uint32_t buffer_size = 8192;
struct working_area *source;
struct working_area *write_algorithm;
static int stellaris_write(struct flash_bank_s *bank, uint8_t *buffer, uint32_t offset, uint32_t count)
{
struct stellaris_flash_bank *stellaris_info = bank->driver_priv;
- target_t *target = bank->target;
+ struct target *target = bank->target;
uint32_t address = offset;
uint32_t flash_cris, flash_fmc;
uint32_t words_remaining = (count / 4);
static int stellaris_mass_erase(struct flash_bank_s *bank)
{
- target_t *target = NULL;
+ struct target *target = NULL;
struct stellaris_flash_bank *stellaris_info = NULL;
uint32_t flash_fmc;
static uint32_t stm32x_get_flash_status(flash_bank_t *bank)
{
- target_t *target = bank->target;
+ struct target *target = bank->target;
uint32_t status;
target_read_u32(target, STM32_FLASH_SR, &status);
static uint32_t stm32x_wait_status_busy(flash_bank_t *bank, int timeout)
{
- target_t *target = bank->target;
+ struct target *target = bank->target;
uint32_t status;
/* wait for busy to clear */
{
uint32_t optiondata;
struct stm32x_flash_bank *stm32x_info = NULL;
- target_t *target = bank->target;
+ struct target *target = bank->target;
stm32x_info = bank->driver_priv;
static int stm32x_erase_options(struct flash_bank_s *bank)
{
struct stm32x_flash_bank *stm32x_info = NULL;
- target_t *target = bank->target;
+ struct target *target = bank->target;
uint32_t status;
stm32x_info = bank->driver_priv;
static int stm32x_write_options(struct flash_bank_s *bank)
{
struct stm32x_flash_bank *stm32x_info = NULL;
- target_t *target = bank->target;
+ struct target *target = bank->target;
uint32_t status;
stm32x_info = bank->driver_priv;
static int stm32x_protect_check(struct flash_bank_s *bank)
{
- target_t *target = bank->target;
+ struct target *target = bank->target;
struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
uint32_t protection;
static int stm32x_erase(struct flash_bank_s *bank, int first, int last)
{
- target_t *target = bank->target;
+ struct target *target = bank->target;
int i;
uint32_t status;
static int stm32x_protect(struct flash_bank_s *bank, int set, int first, int last)
{
struct stm32x_flash_bank *stm32x_info = NULL;
- target_t *target = bank->target;
+ struct target *target = bank->target;
uint16_t prot_reg[4] = {0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF};
int i, reg, bit;
int status;
static int stm32x_write_block(struct flash_bank_s *bank, uint8_t *buffer, uint32_t offset, uint32_t count)
{
struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
- target_t *target = bank->target;
+ struct target *target = bank->target;
uint32_t buffer_size = 16384;
struct working_area *source;
uint32_t address = bank->base + offset;
static int stm32x_write(struct flash_bank_s *bank, uint8_t *buffer, uint32_t offset, uint32_t count)
{
- target_t *target = bank->target;
+ struct target *target = bank->target;
uint32_t words_remaining = (count / 2);
uint32_t bytes_remaining = (count & 0x00000001);
uint32_t address = bank->base + offset;
static int stm32x_probe(struct flash_bank_s *bank)
{
- target_t *target = bank->target;
+ struct target *target = bank->target;
struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
int i;
uint16_t num_pages;
static int stm32x_info(struct flash_bank_s *bank, char *buf, int buf_size)
{
- target_t *target = bank->target;
+ struct target *target = bank->target;
uint32_t device_id;
int printed;
COMMAND_HANDLER(stm32x_handle_lock_command)
{
- target_t *target = NULL;
+ struct target *target = NULL;
struct stm32x_flash_bank *stm32x_info = NULL;
if (argc < 1)
COMMAND_HANDLER(stm32x_handle_unlock_command)
{
- target_t *target = NULL;
+ struct target *target = NULL;
struct stm32x_flash_bank *stm32x_info = NULL;
if (argc < 1)
COMMAND_HANDLER(stm32x_handle_options_read_command)
{
uint32_t optionbyte;
- target_t *target = NULL;
+ struct target *target = NULL;
struct stm32x_flash_bank *stm32x_info = NULL;
if (argc < 1)
COMMAND_HANDLER(stm32x_handle_options_write_command)
{
- target_t *target = NULL;
+ struct target *target = NULL;
struct stm32x_flash_bank *stm32x_info = NULL;
uint16_t optionbyte = 0xF8;
static int stm32x_mass_erase(struct flash_bank_s *bank)
{
- target_t *target = bank->target;
+ struct target *target = bank->target;
uint32_t status;
if (target->state != TARGET_HALTED)
static uint32_t str7x_status(struct flash_bank_s *bank)
{
- target_t *target = bank->target;
+ struct target *target = bank->target;
uint32_t retval;
target_read_u32(target, str7x_get_flash_adr(bank, FLASH_CR0), &retval);
static uint32_t str7x_result(struct flash_bank_s *bank)
{
- target_t *target = bank->target;
+ struct target *target = bank->target;
uint32_t retval;
target_read_u32(target, str7x_get_flash_adr(bank, FLASH_ER), &retval);
static int str7x_protect_check(struct flash_bank_s *bank)
{
struct str7x_flash_bank *str7x_info = bank->driver_priv;
- target_t *target = bank->target;
+ struct target *target = bank->target;
int i;
uint32_t retval;
static int str7x_erase(struct flash_bank_s *bank, int first, int last)
{
struct str7x_flash_bank *str7x_info = bank->driver_priv;
- target_t *target = bank->target;
+ struct target *target = bank->target;
int i;
uint32_t cmd;
static int str7x_protect(struct flash_bank_s *bank, int set, int first, int last)
{
struct str7x_flash_bank *str7x_info = bank->driver_priv;
- target_t *target = bank->target;
+ struct target *target = bank->target;
int i;
uint32_t cmd;
uint32_t retval;
static int str7x_write_block(struct flash_bank_s *bank, uint8_t *buffer, uint32_t offset, uint32_t count)
{
struct str7x_flash_bank *str7x_info = bank->driver_priv;
- target_t *target = bank->target;
+ struct target *target = bank->target;
uint32_t buffer_size = 8192;
struct working_area *source;
uint32_t address = bank->base + offset;
static int str7x_write(struct flash_bank_s *bank, uint8_t *buffer, uint32_t offset, uint32_t count)
{
- target_t *target = bank->target;
+ struct target *target = bank->target;
struct str7x_flash_bank *str7x_info = bank->driver_priv;
uint32_t dwords_remaining = (count / 8);
uint32_t bytes_remaining = (count & 0x00000007);
COMMAND_HANDLER(str7x_handle_disable_jtag_command)
{
- target_t *target = NULL;
+ struct target *target = NULL;
struct str7x_flash_bank *str7x_info = NULL;
uint32_t flash_cmd;
{
int retval;
struct str9x_flash_bank *str9x_info = bank->driver_priv;
- target_t *target = bank->target;
+ struct target *target = bank->target;
int i;
uint32_t adr;
static int str9x_erase(struct flash_bank_s *bank, int first, int last)
{
- target_t *target = bank->target;
+ struct target *target = bank->target;
int i;
uint32_t adr;
uint8_t status;
static int str9x_protect(struct flash_bank_s *bank,
int set, int first, int last)
{
- target_t *target = bank->target;
+ struct target *target = bank->target;
int i;
uint32_t adr;
uint8_t status;
uint8_t *buffer, uint32_t offset, uint32_t count)
{
struct str9x_flash_bank *str9x_info = bank->driver_priv;
- target_t *target = bank->target;
+ struct target *target = bank->target;
uint32_t buffer_size = 8192;
struct working_area *source;
uint32_t address = bank->base + offset;
static int str9x_write(struct flash_bank_s *bank,
uint8_t *buffer, uint32_t offset, uint32_t count)
{
- target_t *target = bank->target;
+ struct target *target = bank->target;
uint32_t words_remaining = (count / 2);
uint32_t bytes_remaining = (count & 0x00000001);
uint32_t address = bank->base + offset;
COMMAND_HANDLER(str9x_handle_flash_config_command)
{
struct str9x_flash_bank *str9x_info;
- target_t *target = NULL;
+ struct target *target = NULL;
if (argc < 5)
{
static int tms470_read_part_info(struct flash_bank_s *bank)
{
struct tms470_flash_bank *tms470_info = bank->driver_priv;
- target_t *target = bank->target;
+ struct target *target = bank->target;
uint32_t device_ident_reg;
uint32_t silicon_version;
uint32_t technology_family;
/* ---------------------------------------------------------------------- */
-static int tms470_check_flash_unlocked(target_t * target)
+static int tms470_check_flash_unlocked(struct target * target)
{
uint32_t fmbbusy;
/* ---------------------------------------------------------------------- */
-static int tms470_try_flash_keys(target_t * target, const uint32_t * key_set)
+static int tms470_try_flash_keys(struct target * target, const uint32_t * key_set)
{
uint32_t glbctrl, fmmstat;
int retval = ERROR_FLASH_OPERATION_FAILED;
static int tms470_unlock_flash(struct flash_bank_s *bank)
{
- target_t *target = bank->target;
+ struct target *target = bank->target;
const uint32_t *p_key_sets[5];
unsigned i, key_set_count;
static int tms470_flash_initialize_internal_state_machine(struct flash_bank_s *bank)
{
uint32_t fmmac2, fmmac1, fmmaxep, k, delay, glbctrl, sysclk;
- target_t *target = bank->target;
+ struct target *target = bank->target;
struct tms470_flash_bank *tms470_info = bank->driver_priv;
int result = ERROR_OK;
int tms470_flash_status(struct flash_bank_s *bank)
{
- target_t *target = bank->target;
+ struct target *target = bank->target;
int result = ERROR_OK;
uint32_t fmmstat;
static int tms470_erase_sector(struct flash_bank_s *bank, int sector)
{
uint32_t glbctrl, orig_fmregopt, fmbsea, fmbseb, fmmstat;
- target_t *target = bank->target;
+ struct target *target = bank->target;
uint32_t flashAddr = bank->base + bank->sectors[sector].offset;
int result = ERROR_OK;
static int tms470_protect(struct flash_bank_s *bank, int set, int first, int last)
{
struct tms470_flash_bank *tms470_info = bank->driver_priv;
- target_t *target = bank->target;
+ struct target *target = bank->target;
uint32_t fmmac2, fmbsea, fmbseb;
int sector;
static int tms470_write(struct flash_bank_s *bank, uint8_t * buffer, uint32_t offset, uint32_t count)
{
- target_t *target = bank->target;
+ struct target *target = bank->target;
uint32_t glbctrl, fmbac2, orig_fmregopt, fmbsea, fmbseb, fmmaxpp, fmmstat;
int result = ERROR_OK;
uint32_t i;
static int tms470_erase_check(struct flash_bank_s *bank)
{
- target_t *target = bank->target;
+ struct target *target = bank->target;
struct tms470_flash_bank *tms470_info = bank->driver_priv;
int sector, result = ERROR_OK;
uint32_t fmmac2, fmbac2, glbctrl, orig_fmregopt;
static int tms470_protect_check(struct flash_bank_s *bank)
{
- target_t *target = bank->target;
+ struct target *target = bank->target;
struct tms470_flash_bank *tms470_info = bank->driver_priv;
int sector, result = ERROR_OK;
uint32_t fmmac2, fmbsea, fmbseb;
-static __inline__ void interface_jtag_add_dr_out_core(struct jtag_tap *target_tap,
+static __inline__ void interface_jtag_add_dr_out_core(struct jtag_tap *struct targetap,
int num_fields,
const int *num_bits,
const uint32_t *value,
/* synchronously do the operation here */
}
-static __inline__ void interface_jtag_add_dr_out(struct jtag_tap *target_tap,
+static __inline__ void interface_jtag_add_dr_out(struct jtag_tap *struct targetap,
int num_fields,
const int *num_bits,
const uint32_t *value,
-static __inline__ void interface_jtag_add_dr_out_core(struct jtag_tap *target_tap,
+static __inline__ void interface_jtag_add_dr_out_core(struct jtag_tap *struct targetap,
int num_fields,
const int *num_bits,
const uint32_t *value,
{
pause_state = end_state;
}
- if (tap == target_tap)
+ if (tap == struct targetap)
{
int j;
for (j = 0; j < (num_fields-1); j++)
}
}
-static __inline__ void interface_jtag_add_dr_out(struct jtag_tap *target_tap,
+static __inline__ void interface_jtag_add_dr_out(struct jtag_tap *struct targetap,
int num_fields,
const int *num_bits,
const uint32_t *value,
shiftValueInner(TAP_DRSHIFT, end_state, num_bits[1], value[1]);
} else
{
- interface_jtag_add_dr_out_core(target_tap, num_fields, num_bits, value, end_state);
+ interface_jtag_add_dr_out_core(struct targetap, num_fields, num_bits, value, end_state);
}
}
jtag_interface_quit();
}
-static int log_target_callback_event_handler(struct target_s *target, enum target_event event, void *priv)
+static int log_target_callback_event_handler(struct target *target, enum target_event event, void *priv)
{
switch (event)
{
* see the code in gdb_read_memory_packet() for further explanations */
int gdb_report_data_abort = 0;
-int gdb_last_signal(target_t *target)
+int gdb_last_signal(struct target *target)
{
switch (target->debug_reason)
{
}
-static void gdb_frontend_halted(struct target_s *target, struct connection *connection)
+static void gdb_frontend_halted(struct target *target, struct connection *connection)
{
struct gdb_connection *gdb_connection = connection->priv;
}
}
-int gdb_target_callback_event_handler(struct target_s *target, enum target_event event, void *priv)
+int gdb_target_callback_event_handler(struct target *target, enum target_event event, void *priv)
{
int retval;
struct connection *connection = priv;
gdb_put_packet(connection, err, 3);
}
-int gdb_last_signal_packet(struct connection *connection, target_t *target, char* packet, int packet_size)
+int gdb_last_signal_packet(struct connection *connection, struct target *target, char* packet, int packet_size)
{
char sig_reply[4];
int signal;
return ERROR_OK;
}
-static int gdb_reg_pos(target_t *target, int pos, int len)
+static int gdb_reg_pos(struct target *target, int pos, int len)
{
if (target->endianness == TARGET_LITTLE_ENDIAN)
return pos;
* The format of reg->value is little endian
*
*/
-void gdb_str_to_target(target_t *target, char *tstr, struct reg *reg)
+void gdb_str_to_target(struct target *target, char *tstr, struct reg *reg)
{
int i;
}
/* copy over in register buffer */
-void gdb_target_to_reg(target_t *target, char *tstr, int str_len, uint8_t *bin)
+void gdb_target_to_reg(struct target *target, char *tstr, int str_len, uint8_t *bin)
{
if (str_len % 2)
{
}
}
-int gdb_get_registers_packet(struct connection *connection, target_t *target, char* packet, int packet_size)
+int gdb_get_registers_packet(struct connection *connection, struct target *target, char* packet, int packet_size)
{
struct reg **reg_list;
int reg_list_size;
return ERROR_OK;
}
-int gdb_set_registers_packet(struct connection *connection, target_t *target, char *packet, int packet_size)
+int gdb_set_registers_packet(struct connection *connection, struct target *target, char *packet, int packet_size)
{
int i;
struct reg **reg_list;
return ERROR_OK;
}
-int gdb_get_register_packet(struct connection *connection, target_t *target, char *packet, int packet_size)
+int gdb_get_register_packet(struct connection *connection, struct target *target, char *packet, int packet_size)
{
char *reg_packet;
int reg_num = strtoul(packet + 1, NULL, 16);
return ERROR_OK;
}
-int gdb_set_register_packet(struct connection *connection, target_t *target, char *packet, int packet_size)
+int gdb_set_register_packet(struct connection *connection, struct target *target, char *packet, int packet_size)
{
char *separator;
uint8_t *bin_buf;
*
* 8191 bytes by the looks of it. Why 8191 bytes instead of 8192?????
*/
-int gdb_read_memory_packet(struct connection *connection, target_t *target, char *packet, int packet_size)
+int gdb_read_memory_packet(struct connection *connection, struct target *target, char *packet, int packet_size)
{
char *separator;
uint32_t addr = 0;
return retval;
}
-int gdb_write_memory_packet(struct connection *connection, target_t *target, char *packet, int packet_size)
+int gdb_write_memory_packet(struct connection *connection, struct target *target, char *packet, int packet_size)
{
char *separator;
uint32_t addr = 0;
return retval;
}
-int gdb_write_memory_binary_packet(struct connection *connection, target_t *target, char *packet, int packet_size)
+int gdb_write_memory_binary_packet(struct connection *connection, struct target *target, char *packet, int packet_size)
{
char *separator;
uint32_t addr = 0;
return ERROR_OK;
}
-int gdb_step_continue_packet(struct connection *connection, target_t *target, char *packet, int packet_size)
+int gdb_step_continue_packet(struct connection *connection, struct target *target, char *packet, int packet_size)
{
int current = 0;
uint32_t address = 0x0;
return retval;
}
-int gdb_breakpoint_watchpoint_packet(struct connection *connection, target_t *target, char *packet, int packet_size)
+int gdb_breakpoint_watchpoint_packet(struct connection *connection, struct target *target, char *packet, int packet_size)
{
int type;
enum breakpoint_type bp_type = BKPT_SOFT /* dummy init to avoid warning */;
}
}
-int gdb_query_packet(struct connection *connection, target_t *target, char *packet, int packet_size)
+int gdb_query_packet(struct connection *connection, struct target *target, char *packet, int packet_size)
{
command_context_t *cmd_ctx = connection->cmd_ctx;
struct gdb_connection *gdb_connection = connection->priv;
return ERROR_OK;
}
-int gdb_v_packet(struct connection *connection, target_t *target, char *packet, int packet_size)
+int gdb_v_packet(struct connection *connection, struct target *target, char *packet, int packet_size)
{
struct gdb_connection *gdb_connection = connection->priv;
struct gdb_service *gdb_service = connection->service->priv;
return ERROR_OK;
}
-int gdb_detach(struct connection *connection, target_t *target)
+int gdb_detach(struct connection *connection, struct target *target)
{
struct gdb_service *gdb_service = connection->service->priv;
int gdb_input_inner(struct connection *connection)
{
struct gdb_service *gdb_service = connection->service->priv;
- target_t *target = gdb_service->target;
+ struct target *target = gdb_service->target;
char *packet = gdb_packet_buffer;
int packet_size;
int retval;
int gdb_init(void)
{
struct gdb_service *gdb_service;
- target_t *target = all_targets;
+ struct target *target = all_targets;
if (!target)
{
struct gdb_service
{
- struct target_s *target;
+ struct target *target;
};
int gdb_init(void);
static int arm11_on_enter_debug_state(struct arm11_common *arm11);
-static int arm11_step(struct target_s *target, int current,
+static int arm11_step(struct target *target, int current,
uint32_t address, int handle_breakpoints);
/* helpers */
-static int arm11_build_reg_cache(target_t *target);
+static int arm11_build_reg_cache(struct target *target);
static int arm11_set_reg(struct reg *reg, uint8_t *buf);
static int arm11_get_reg(struct reg *reg);
/* poll current target status */
-static int arm11_poll(struct target_s *target)
+static int arm11_poll(struct target *target)
{
FNC_INFO;
int retval;
return ERROR_OK;
}
/* architecture specific status reply */
-static int arm11_arch_state(struct target_s *target)
+static int arm11_arch_state(struct target *target)
{
struct arm11_common * arm11 = target->arch_info;
}
/* target request support */
-static int arm11_target_request_data(struct target_s *target,
+static int arm11_target_request_data(struct target *target,
uint32_t size, uint8_t *buffer)
{
FNC_INFO_NOTIMPLEMENTED;
}
/* target execution control */
-static int arm11_halt(struct target_s *target)
+static int arm11_halt(struct target *target)
{
FNC_INFO;
return ERROR_OK;
}
-static int arm11_resume(struct target_s *target, int current,
+static int arm11_resume(struct target *target, int current,
uint32_t address, int handle_breakpoints, int debug_execution)
{
FNC_INFO;
return ARMV4_5_MODE_USR;
}
-static int arm11_simulate_step(target_t *target, uint32_t *dry_run_pc)
+static int arm11_simulate_step(struct target *target, uint32_t *dry_run_pc)
{
struct arm_sim_interface sim;
}
-static int arm11_step(struct target_s *target, int current,
+static int arm11_step(struct target *target, int current,
uint32_t address, int handle_breakpoints)
{
FNC_INFO;
return ERROR_OK;
}
-static int arm11_assert_reset(target_t *target)
+static int arm11_assert_reset(struct target *target)
{
FNC_INFO;
int retval;
return ERROR_OK;
}
-static int arm11_deassert_reset(target_t *target)
+static int arm11_deassert_reset(struct target *target)
{
return ERROR_OK;
}
-static int arm11_soft_reset_halt(struct target_s *target)
+static int arm11_soft_reset_halt(struct target *target)
{
FNC_INFO_NOTIMPLEMENTED;
}
/* target register access for gdb */
-static int arm11_get_gdb_reg_list(struct target_s *target,
+static int arm11_get_gdb_reg_list(struct target *target,
struct reg **reg_list[], int *reg_list_size)
{
FNC_INFO;
* to read/write a range of data to a "port". a "port" is an action on
* read memory address for some peripheral.
*/
-static int arm11_read_memory_inner(struct target_s *target,
+static int arm11_read_memory_inner(struct target *target,
uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer,
bool arm11_config_memrw_no_increment)
{
return arm11_run_instr_data_finish(arm11);
}
-static int arm11_read_memory(struct target_s *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer)
+static int arm11_read_memory(struct target *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer)
{
return arm11_read_memory_inner(target, address, size, count, buffer, false);
}
* to read/write a range of data to a "port". a "port" is an action on
* read memory address for some peripheral.
*/
-static int arm11_write_memory_inner(struct target_s *target,
+static int arm11_write_memory_inner(struct target *target,
uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer,
bool arm11_config_memrw_no_increment)
{
return arm11_run_instr_data_finish(arm11);
}
-static int arm11_write_memory(struct target_s *target,
+static int arm11_write_memory(struct target *target,
uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer)
{
return arm11_write_memory_inner(target, address, size, count, buffer, false);
}
/* write target memory in multiples of 4 byte, optimized for writing large quantities of data */
-static int arm11_bulk_write_memory(struct target_s *target,
+static int arm11_bulk_write_memory(struct target *target,
uint32_t address, uint32_t count, uint8_t *buffer)
{
FNC_INFO;
* fallback code will read data from the target and calculate the CRC on the
* host.
*/
-static int arm11_checksum_memory(struct target_s *target,
+static int arm11_checksum_memory(struct target *target,
uint32_t address, uint32_t count, uint32_t* checksum)
{
return ERROR_FAIL;
/* target break-/watchpoint control
* rw: 0 = write, 1 = read, 2 = access
*/
-static int arm11_add_breakpoint(struct target_s *target,
+static int arm11_add_breakpoint(struct target *target,
struct breakpoint *breakpoint)
{
FNC_INFO;
return ERROR_OK;
}
-static int arm11_remove_breakpoint(struct target_s *target,
+static int arm11_remove_breakpoint(struct target *target,
struct breakpoint *breakpoint)
{
FNC_INFO;
return ERROR_OK;
}
-static int arm11_add_watchpoint(struct target_s *target,
+static int arm11_add_watchpoint(struct target *target,
struct watchpoint *watchpoint)
{
FNC_INFO_NOTIMPLEMENTED;
return ERROR_OK;
}
-static int arm11_remove_watchpoint(struct target_s *target,
+static int arm11_remove_watchpoint(struct target *target,
struct watchpoint *watchpoint)
{
FNC_INFO_NOTIMPLEMENTED;
// HACKHACKHACK - FIXME mode/state
/* target algorithm support */
-static int arm11_run_algorithm(struct target_s *target,
+static int arm11_run_algorithm(struct target *target,
int num_mem_params, struct mem_param *mem_params,
int num_reg_params, struct reg_param *reg_params,
uint32_t entry_point, uint32_t exit_point,
return retval;
}
-static int arm11_target_create(struct target_s *target, Jim_Interp *interp)
+static int arm11_target_create(struct target *target, Jim_Interp *interp)
{
FNC_INFO;
}
static int arm11_init_target(struct command_context_s *cmd_ctx,
- struct target_s *target)
+ struct target *target)
{
/* Initialize anything we can set up without talking to the target */
return arm11_build_reg_cache(target);
}
/* talk to the target and set things up */
-static int arm11_examine(struct target_s *target)
+static int arm11_examine(struct target *target)
{
int retval;
{
FNC_INFO;
- target_t * target = ((struct arm11_reg_state *)reg->arch_info)->target;
+ struct target * target = ((struct arm11_reg_state *)reg->arch_info)->target;
if (target->state != TARGET_HALTED)
{
{
FNC_INFO;
- target_t * target = ((struct arm11_reg_state *)reg->arch_info)->target;
+ struct target * target = ((struct arm11_reg_state *)reg->arch_info)->target;
struct arm11_common *arm11 = target->arch_info;
// const struct arm11_reg_defs * arm11_reg_info = arm11_reg_defs + ((struct arm11_reg_state *)reg->arch_info)->def_index;
return ERROR_OK;
}
-static int arm11_build_reg_cache(target_t *target)
+static int arm11_build_reg_cache(struct target *target)
{
struct arm11_common *arm11 = target->arch_info;
static struct arm11_common * arm11_find_target(const char * arg)
{
struct jtag_tap * tap;
- target_t * t;
+ struct target * t;
tap = jtag_tap_by_string(arg);
return 0;
}
-static int arm11_mrc_inner(target_t *target, int cpnum,
+static int arm11_mrc_inner(struct target *target, int cpnum,
uint32_t op1, uint32_t op2, uint32_t CRn, uint32_t CRm,
uint32_t *value, bool read)
{
return arm11_run_instr_data_finish(arm11);
}
-static int arm11_mrc(target_t *target, int cpnum,
+static int arm11_mrc(struct target *target, int cpnum,
uint32_t op1, uint32_t op2, uint32_t CRn, uint32_t CRm, uint32_t *value)
{
return arm11_mrc_inner(target, cpnum, op1, op2, CRn, CRm, value, true);
}
-static int arm11_mcr(target_t *target, int cpnum,
+static int arm11_mcr(struct target *target, int cpnum,
uint32_t op1, uint32_t op2, uint32_t CRn, uint32_t CRm, uint32_t value)
{
return arm11_mrc_inner(target, cpnum, op1, op2, CRn, CRm, &value, false);
struct arm11_common
{
- target_t * target; /**< Reference back to the owner */
+ struct target * target; /**< Reference back to the owner */
/** \name Processor type detection */
/*@{*/
struct arm11_reg_state
{
uint32_t def_index;
- target_t * target;
+ struct target * target;
};
int arm11_register_commands(struct command_context_s *cmd_ctx);
#define _DEBUG_INSTRUCTION_EXECUTION_
#endif
-static int arm720t_scan_cp15(target_t *target,
+static int arm720t_scan_cp15(struct target *target,
uint32_t out, uint32_t *in, int instruction, int clock)
{
int retval;
return ERROR_OK;
}
-static int arm720t_read_cp15(target_t *target, uint32_t opcode, uint32_t *value)
+static int arm720t_read_cp15(struct target *target, uint32_t opcode, uint32_t *value)
{
/* fetch CP15 opcode */
arm720t_scan_cp15(target, opcode, NULL, 1, 1);
return ERROR_OK;
}
-static int arm720t_write_cp15(target_t *target, uint32_t opcode, uint32_t value)
+static int arm720t_write_cp15(struct target *target, uint32_t opcode, uint32_t value)
{
/* fetch CP15 opcode */
arm720t_scan_cp15(target, opcode, NULL, 1, 1);
return ERROR_OK;
}
-static uint32_t arm720t_get_ttb(target_t *target)
+static uint32_t arm720t_get_ttb(struct target *target)
{
uint32_t ttb = 0x0;
return ttb;
}
-static void arm720t_disable_mmu_caches(target_t *target,
+static void arm720t_disable_mmu_caches(struct target *target,
int mmu, int d_u_cache, int i_cache)
{
uint32_t cp15_control;
arm720t_write_cp15(target, 0xee010f10, cp15_control);
}
-static void arm720t_enable_mmu_caches(target_t *target,
+static void arm720t_enable_mmu_caches(struct target *target,
int mmu, int d_u_cache, int i_cache)
{
uint32_t cp15_control;
arm720t_write_cp15(target, 0xee010f10, cp15_control);
}
-static void arm720t_post_debug_entry(target_t *target)
+static void arm720t_post_debug_entry(struct target *target)
{
struct arm720t_common *arm720t = target_to_arm720(target);
jtag_execute_queue();
}
-static void arm720t_pre_restore_context(target_t *target)
+static void arm720t_pre_restore_context(struct target *target)
{
struct arm720t_common *arm720t = target_to_arm720(target);
return ERROR_OK;
}
-static int arm720t_arch_state(struct target_s *target)
+static int arm720t_arch_state(struct target *target)
{
struct arm720t_common *arm720t = target_to_arm720(target);
struct armv4_5_common_s *armv4_5;
return ERROR_OK;
}
-static int arm720_mmu(struct target_s *target, int *enabled)
+static int arm720_mmu(struct target *target, int *enabled)
{
if (target->state != TARGET_HALTED) {
LOG_ERROR("%s: target not halted", __func__);
return ERROR_OK;
}
-static int arm720_virt2phys(struct target_s *target,
+static int arm720_virt2phys(struct target *target,
uint32_t virt, uint32_t *phys)
{
/** @todo Implement this! */
return ERROR_FAIL;
}
-static int arm720t_read_memory(struct target_s *target,
+static int arm720t_read_memory(struct target *target,
uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer)
{
int retval;
return retval;
}
-static int arm720t_read_phys_memory(struct target_s *target,
+static int arm720t_read_phys_memory(struct target *target,
uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer)
{
struct arm720t_common *arm720t = target_to_arm720(target);
return armv4_5_mmu_read_physical(target, &arm720t->armv4_5_mmu, address, size, count, buffer);
}
-static int arm720t_write_phys_memory(struct target_s *target,
+static int arm720t_write_phys_memory(struct target *target,
uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer)
{
struct arm720t_common *arm720t = target_to_arm720(target);
return armv4_5_mmu_write_physical(target, &arm720t->armv4_5_mmu, address, size, count, buffer);
}
-static int arm720t_soft_reset_halt(struct target_s *target)
+static int arm720t_soft_reset_halt(struct target *target)
{
int retval = ERROR_OK;
struct arm720t_common *arm720t = target_to_arm720(target);
return ERROR_OK;
}
-static int arm720t_init_target(struct command_context_s *cmd_ctx, struct target_s *target)
+static int arm720t_init_target(struct command_context_s *cmd_ctx, struct target *target)
{
return arm7tdmi_init_target(cmd_ctx, target);
}
-static int arm720t_init_arch_info(target_t *target,
+static int arm720t_init_arch_info(struct target *target,
struct arm720t_common *arm720t, struct jtag_tap *tap)
{
struct arm7tdmi_common *arm7tdmi = &arm720t->arm7tdmi_common;
return ERROR_OK;
}
-static int arm720t_target_create(struct target_s *target, Jim_Interp *interp)
+static int arm720t_target_create(struct target *target, Jim_Interp *interp)
{
struct arm720t_common *arm720t = calloc(1, sizeof(*arm720t));
COMMAND_HANDLER(arm720t_handle_cp15_command)
{
int retval;
- target_t *target = get_current_target(cmd_ctx);
+ struct target *target = get_current_target(cmd_ctx);
struct arm720t_common *arm720t = target_to_arm720(target);
struct arm_jtag *jtag_info;
return ERROR_OK;
}
-static int arm720t_mrc(target_t *target, int cpnum, uint32_t op1, uint32_t op2, uint32_t CRn, uint32_t CRm, uint32_t *value)
+static int arm720t_mrc(struct target *target, int cpnum, uint32_t op1, uint32_t op2, uint32_t CRn, uint32_t CRm, uint32_t *value)
{
if (cpnum!=15)
{
}
-static int arm720t_mcr(target_t *target, int cpnum, uint32_t op1, uint32_t op2, uint32_t CRn, uint32_t CRm, uint32_t value)
+static int arm720t_mcr(struct target *target, int cpnum, uint32_t op1, uint32_t op2, uint32_t CRn, uint32_t CRm, uint32_t value)
{
if (cpnum!=15)
{
};
static inline struct arm720t_common *
-target_to_arm720(struct target_s *target)
+target_to_arm720(struct target *target)
{
return container_of(target->arch_info, struct arm720t_common,
arm7tdmi_common.arm7_9_common.armv4_5_common);
#include "arm_simulator.h"
-int arm7_9_debug_entry(target_t *target);
+int arm7_9_debug_entry(struct target *target);
/**
* Clear watchpoints for an ARM7/9 target.
* @param target Pointer to an ARM7/9 target to setup
* @return Result of clearing the watchpoints on the target
*/
-int arm7_9_setup(target_t *target)
+int arm7_9_setup(struct target *target)
{
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
* targets
* @return ERROR_OK if successful
*/
-int arm7_9_get_arch_pointers(target_t *target, struct arm **armv4_5_p, struct arm7_9_common **arm7_9_p)
+int arm7_9_get_arch_pointers(struct target *target, struct arm **armv4_5_p, struct arm7_9_common **arm7_9_p)
{
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
struct armv4_5_common_s *armv4_5 = &arm7_9->armv4_5_common;
* queue. For software breakpoints, this will be the status of the
* required memory reads and writes
*/
-int arm7_9_set_breakpoint(struct target_s *target, struct breakpoint *breakpoint)
+int arm7_9_set_breakpoint(struct target *target, struct breakpoint *breakpoint)
{
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
int retval = ERROR_OK;
* queue. For software breakpoints, this will be the status of the
* required memory reads and writes
*/
-int arm7_9_unset_breakpoint(struct target_s *target, struct breakpoint *breakpoint)
+int arm7_9_unset_breakpoint(struct target *target, struct breakpoint *breakpoint)
{
int retval = ERROR_OK;
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
* @return An error status if there is a problem adding the breakpoint or the
* result of setting the breakpoint
*/
-int arm7_9_add_breakpoint(struct target_s *target, struct breakpoint *breakpoint)
+int arm7_9_add_breakpoint(struct target *target, struct breakpoint *breakpoint)
{
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
* @return Error status if there was a problem unsetting the breakpoint or the
* watchpoints could not be cleared
*/
-int arm7_9_remove_breakpoint(struct target_s *target, struct breakpoint *breakpoint)
+int arm7_9_remove_breakpoint(struct target *target, struct breakpoint *breakpoint)
{
int retval = ERROR_OK;
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
* @return Error status if watchpoint set fails or the result of executing the
* JTAG queue
*/
-int arm7_9_set_watchpoint(struct target_s *target, struct watchpoint *watchpoint)
+int arm7_9_set_watchpoint(struct target *target, struct watchpoint *watchpoint)
{
int retval = ERROR_OK;
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
* @return Error status while trying to unset the watchpoint or the result of
* executing the JTAG queue
*/
-int arm7_9_unset_watchpoint(struct target_s *target, struct watchpoint *watchpoint)
+int arm7_9_unset_watchpoint(struct target *target, struct watchpoint *watchpoint)
{
int retval = ERROR_OK;
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
* @param watchpoint Pointer to the watchpoint to be added
* @return Error status while trying to add the watchpoint
*/
-int arm7_9_add_watchpoint(struct target_s *target, struct watchpoint *watchpoint)
+int arm7_9_add_watchpoint(struct target *target, struct watchpoint *watchpoint)
{
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
* @param watchpoint Pointer to the watchpoint to be removed
* @return Result of trying to unset the watchpoint
*/
-int arm7_9_remove_watchpoint(struct target_s *target, struct watchpoint *watchpoint)
+int arm7_9_remove_watchpoint(struct target *target, struct watchpoint *watchpoint)
{
int retval = ERROR_OK;
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
* @return Error status if there is a timeout or a problem while executing the
* JTAG queue
*/
-int arm7_9_execute_sys_speed(struct target_s *target)
+int arm7_9_execute_sys_speed(struct target *target)
{
int retval;
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
* @param target Pointer to the target to issue commands to
* @return Always ERROR_OK
*/
-int arm7_9_execute_fast_sys_speed(struct target_s *target)
+int arm7_9_execute_fast_sys_speed(struct target *target)
{
static int set = 0;
static uint8_t check_value[4], check_mask[4];
* @param buffer Pointer to the buffer that will hold the data
* @return The result of receiving data from the Embedded ICE unit
*/
-int arm7_9_target_request_data(target_t *target, uint32_t size, uint8_t *buffer)
+int arm7_9_target_request_data(struct target *target, uint32_t size, uint8_t *buffer)
{
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
struct arm_jtag *jtag_info = &arm7_9->jtag_info;
* target is running and the DCC control register has the W bit high, this will
* execute the request on the target.
*
- * @param priv Void pointer expected to be a target_t pointer
+ * @param priv Void pointer expected to be a struct target pointer
* @return ERROR_OK unless there are issues with the JTAG queue or when reading
* from the Embedded ICE unit
*/
int arm7_9_handle_target_request(void *priv)
{
int retval = ERROR_OK;
- target_t *target = priv;
+ struct target *target = priv;
if (!target_was_examined(target))
return ERROR_OK;
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
* @param target Pointer to the ARM7/9 target to poll
* @return ERROR_OK or an error status if a command fails
*/
-int arm7_9_poll(target_t *target)
+int arm7_9_poll(struct target *target)
{
int retval;
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
* @param target Pointer to an ARM7/9 target to assert reset on
* @return ERROR_FAIL if the JTAG device does not have SRST, otherwise ERROR_OK
*/
-int arm7_9_assert_reset(target_t *target)
+int arm7_9_assert_reset(struct target *target)
{
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
* @param target Pointer to the target to have the reset deasserted
* @return ERROR_OK or an error from polling or halting the target
*/
-int arm7_9_deassert_reset(target_t *target)
+int arm7_9_deassert_reset(struct target *target)
{
int retval = ERROR_OK;
LOG_DEBUG("target->state: %s",
* @param target Pointer to the ARM7/9 target to have halt cleared
* @return Always ERROR_OK
*/
-int arm7_9_clear_halt(target_t *target)
+int arm7_9_clear_halt(struct target *target)
{
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
struct reg *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
* @param target Pointer to the ARM7/9 target to be reset and halted by software
* @return Error status if any of the commands fail, otherwise ERROR_OK
*/
-int arm7_9_soft_reset_halt(struct target_s *target)
+int arm7_9_soft_reset_halt(struct target *target)
{
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
struct armv4_5_common_s *armv4_5 = &arm7_9->armv4_5_common;
* @param target Pointer to the ARM7/9 target to be halted
* @return Always ERROR_OK
*/
-int arm7_9_halt(target_t *target)
+int arm7_9_halt(struct target *target)
{
if (target->state == TARGET_RESET)
{
* @param target Pointer to target that is entering debug mode
* @return Error code if anything fails, otherwise ERROR_OK
*/
-int arm7_9_debug_entry(target_t *target)
+int arm7_9_debug_entry(struct target *target)
{
int i;
uint32_t context[16];
* @return Error if the target is not halted, has an invalid core mode, or if
* the JTAG queue fails to execute
*/
-int arm7_9_full_context(target_t *target)
+int arm7_9_full_context(struct target *target)
{
int i;
int retval;
* @return Error status if the target is not halted or the core mode in the
* armv4_5 struct is invalid.
*/
-int arm7_9_restore_context(target_t *target)
+int arm7_9_restore_context(struct target *target)
{
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
struct armv4_5_common_s *armv4_5 = &arm7_9->armv4_5_common;
* @param target Pointer to the ARM7/9 target to be restarted
* @return Result of executing the JTAG queue
*/
-int arm7_9_restart_core(struct target_s *target)
+int arm7_9_restart_core(struct target *target)
{
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
struct arm_jtag *jtag_info = &arm7_9->jtag_info;
*
* @param target Pointer to the ARM7/9 target to enable watchpoints on
*/
-void arm7_9_enable_watchpoints(struct target_s *target)
+void arm7_9_enable_watchpoints(struct target *target)
{
struct watchpoint *watchpoint = target->watchpoints;
*
* @param target Pointer to the ARM7/9 target to enable breakpoints on
*/
-void arm7_9_enable_breakpoints(struct target_s *target)
+void arm7_9_enable_breakpoints(struct target *target)
{
struct breakpoint *breakpoint = target->breakpoints;
}
}
-int arm7_9_resume(struct target_s *target, int current, uint32_t address, int handle_breakpoints, int debug_execution)
+int arm7_9_resume(struct target *target, int current, uint32_t address, int handle_breakpoints, int debug_execution)
{
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
struct armv4_5_common_s *armv4_5 = &arm7_9->armv4_5_common;
return ERROR_OK;
}
-void arm7_9_enable_eice_step(target_t *target, uint32_t next_pc)
+void arm7_9_enable_eice_step(struct target *target, uint32_t next_pc)
{
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
struct armv4_5_common_s *armv4_5 = &arm7_9->armv4_5_common;
}
}
-void arm7_9_disable_eice_step(target_t *target)
+void arm7_9_disable_eice_step(struct target *target)
{
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE]);
}
-int arm7_9_step(struct target_s *target, int current, uint32_t address, int handle_breakpoints)
+int arm7_9_step(struct target *target, int current, uint32_t address, int handle_breakpoints)
{
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
struct armv4_5_common_s *armv4_5 = &arm7_9->armv4_5_common;
return err;
}
-int arm7_9_read_core_reg(struct target_s *target, int num, enum armv4_5_mode mode)
+int arm7_9_read_core_reg(struct target *target, int num, enum armv4_5_mode mode)
{
uint32_t* reg_p[16];
uint32_t value;
return ERROR_OK;
}
-int arm7_9_write_core_reg(struct target_s *target, int num, enum armv4_5_mode mode, uint32_t value)
+int arm7_9_write_core_reg(struct target *target, int num, enum armv4_5_mode mode, uint32_t value)
{
uint32_t reg[16];
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
return jtag_execute_queue();
}
-int arm7_9_read_memory(struct target_s *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer)
+int arm7_9_read_memory(struct target *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer)
{
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
struct armv4_5_common_s *armv4_5 = &arm7_9->armv4_5_common;
return ERROR_OK;
}
-int arm7_9_write_memory(struct target_s *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer)
+int arm7_9_write_memory(struct target *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer)
{
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
struct armv4_5_common_s *armv4_5 = &arm7_9->armv4_5_common;
static int dcc_count;
static uint8_t *dcc_buffer;
-static int arm7_9_dcc_completion(struct target_s *target, uint32_t exit_point, int timeout_ms, void *arch_info)
+static int arm7_9_dcc_completion(struct target *target, uint32_t exit_point, int timeout_ms, void *arch_info)
{
int retval = ERROR_OK;
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
0xeafffff9 /* b w */
};
-int armv4_5_run_algorithm_inner(struct target_s *target, int num_mem_params, struct mem_param *mem_params, int num_reg_params, struct reg_param *reg_params, uint32_t entry_point, uint32_t exit_point, int timeout_ms, void *arch_info, int (*run_it)(struct target_s *target, uint32_t exit_point, int timeout_ms, void *arch_info));
+int armv4_5_run_algorithm_inner(struct target *target, int num_mem_params, struct mem_param *mem_params, int num_reg_params, struct reg_param *reg_params, uint32_t entry_point, uint32_t exit_point, int timeout_ms, void *arch_info, int (*run_it)(struct target *target, uint32_t exit_point, int timeout_ms, void *arch_info));
-int arm7_9_bulk_write_memory(target_t *target, uint32_t address, uint32_t count, uint8_t *buffer)
+int arm7_9_bulk_write_memory(struct target *target, uint32_t address, uint32_t count, uint8_t *buffer)
{
int retval;
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
return retval;
}
-int arm7_9_checksum_memory(struct target_s *target, uint32_t address, uint32_t count, uint32_t* checksum)
+int arm7_9_checksum_memory(struct target *target, uint32_t address, uint32_t count, uint32_t* checksum)
{
struct working_area *crc_algorithm;
struct armv4_5_algorithm armv4_5_info;
return ERROR_OK;
}
-int arm7_9_blank_check_memory(struct target_s *target, uint32_t address, uint32_t count, uint32_t* blank)
+int arm7_9_blank_check_memory(struct target *target, uint32_t address, uint32_t count, uint32_t* blank)
{
struct working_area *erase_check_algorithm;
struct reg_param reg_params[3];
uint32_t value;
int spsr;
int retval;
- target_t *target = get_current_target(cmd_ctx);
+ struct target *target = get_current_target(cmd_ctx);
struct arm *armv4_5;
struct arm7_9_common *arm7_9;
int rotate;
int spsr;
int retval;
- target_t *target = get_current_target(cmd_ctx);
+ struct target *target = get_current_target(cmd_ctx);
struct arm *armv4_5;
struct arm7_9_common *arm7_9;
uint32_t value;
uint32_t mode;
int num;
- target_t *target = get_current_target(cmd_ctx);
+ struct target *target = get_current_target(cmd_ctx);
struct arm *armv4_5;
struct arm7_9_common *arm7_9;
COMMAND_HANDLER(handle_arm7_9_dbgrq_command)
{
- target_t *target = get_current_target(cmd_ctx);
+ struct target *target = get_current_target(cmd_ctx);
struct arm *armv4_5;
struct arm7_9_common *arm7_9;
COMMAND_HANDLER(handle_arm7_9_fast_memory_access_command)
{
- target_t *target = get_current_target(cmd_ctx);
+ struct target *target = get_current_target(cmd_ctx);
struct arm *armv4_5;
struct arm7_9_common *arm7_9;
COMMAND_HANDLER(handle_arm7_9_dcc_downloads_command)
{
- target_t *target = get_current_target(cmd_ctx);
+ struct target *target = get_current_target(cmd_ctx);
struct arm *armv4_5;
struct arm7_9_common *arm7_9;
return ERROR_OK;
}
-int arm7_9_init_arch_info(target_t *target, struct arm7_9_common *arm7_9)
+int arm7_9_init_arch_info(struct target *target, struct arm7_9_common *arm7_9)
{
int retval = ERROR_OK;
struct arm *armv4_5 = &arm7_9->armv4_5_common;
struct working_area *dcc_working_area;
- int (*examine_debug_reason)(target_t *target); /**< Function for determining why debug state was entered */
+ int (*examine_debug_reason)(struct target *target); /**< Function for determining why debug state was entered */
- void (*change_to_arm)(target_t *target, uint32_t *r0, uint32_t *pc); /**< Function for changing from Thumb to ARM mode */
+ void (*change_to_arm)(struct target *target, uint32_t *r0, uint32_t *pc); /**< Function for changing from Thumb to ARM mode */
- void (*read_core_regs)(target_t *target, uint32_t mask, uint32_t *core_regs[16]); /**< Function for reading the core registers */
- void (*read_core_regs_target_buffer)(target_t *target, uint32_t mask, void *buffer, int size);
- void (*read_xpsr)(target_t *target, uint32_t *xpsr, int spsr); /**< Function for reading CPSR or SPSR */
+ void (*read_core_regs)(struct target *target, uint32_t mask, uint32_t *core_regs[16]); /**< Function for reading the core registers */
+ void (*read_core_regs_target_buffer)(struct target *target, uint32_t mask, void *buffer, int size);
+ void (*read_xpsr)(struct target *target, uint32_t *xpsr, int spsr); /**< Function for reading CPSR or SPSR */
- void (*write_xpsr)(target_t *target, uint32_t xpsr, int spsr); /**< Function for writing to CPSR or SPSR */
- void (*write_xpsr_im8)(target_t *target, uint8_t xpsr_im, int rot, int spsr); /**< Function for writing an immediate value to CPSR or SPSR */
- void (*write_core_regs)(target_t *target, uint32_t mask, uint32_t core_regs[16]);
+ void (*write_xpsr)(struct target *target, uint32_t xpsr, int spsr); /**< Function for writing to CPSR or SPSR */
+ void (*write_xpsr_im8)(struct target *target, uint8_t xpsr_im, int rot, int spsr); /**< Function for writing an immediate value to CPSR or SPSR */
+ void (*write_core_regs)(struct target *target, uint32_t mask, uint32_t core_regs[16]);
- void (*load_word_regs)(target_t *target, uint32_t mask);
- void (*load_hword_reg)(target_t *target, int num);
- void (*load_byte_reg)(target_t *target, int num);
+ void (*load_word_regs)(struct target *target, uint32_t mask);
+ void (*load_hword_reg)(struct target *target, int num);
+ void (*load_byte_reg)(struct target *target, int num);
- void (*store_word_regs)(target_t *target, uint32_t mask);
- void (*store_hword_reg)(target_t *target, int num);
- void (*store_byte_reg)(target_t *target, int num);
+ void (*store_word_regs)(struct target *target, uint32_t mask);
+ void (*store_hword_reg)(struct target *target, int num);
+ void (*store_byte_reg)(struct target *target, int num);
- void (*write_pc)(target_t *target, uint32_t pc); /**< Function for writing to the program counter */
- void (*branch_resume)(target_t *target);
- void (*branch_resume_thumb)(target_t *target);
+ void (*write_pc)(struct target *target, uint32_t pc); /**< Function for writing to the program counter */
+ void (*branch_resume)(struct target *target);
+ void (*branch_resume_thumb)(struct target *target);
- void (*enable_single_step)(target_t *target, uint32_t next_pc);
- void (*disable_single_step)(target_t *target);
+ void (*enable_single_step)(struct target *target, uint32_t next_pc);
+ void (*disable_single_step)(struct target *target);
- void (*set_special_dbgrq)(target_t *target); /**< Function for setting DBGRQ if the normal way won't work */
+ void (*set_special_dbgrq)(struct target *target); /**< Function for setting DBGRQ if the normal way won't work */
- void (*post_debug_entry)(target_t *target); /**< Callback function called after entering debug mode */
+ void (*post_debug_entry)(struct target *target); /**< Callback function called after entering debug mode */
- void (*pre_restore_context)(target_t *target); /**< Callback function called before restoring the processor context */
- void (*post_restore_context)(target_t *target); /**< Callback function called after restoring the processor context */
+ void (*pre_restore_context)(struct target *target); /**< Callback function called before restoring the processor context */
+ void (*post_restore_context)(struct target *target); /**< Callback function called after restoring the processor context */
};
static inline struct arm7_9_common *
-target_to_arm7_9(struct target_s *target)
+target_to_arm7_9(struct target *target)
{
return container_of(target->arch_info, struct arm7_9_common,
armv4_5_common);
int arm7_9_register_commands(struct command_context_s *cmd_ctx);
-int arm7_9_poll(target_t *target);
+int arm7_9_poll(struct target *target);
-int arm7_9_target_request_data(target_t *target, uint32_t size, uint8_t *buffer);
+int arm7_9_target_request_data(struct target *target, uint32_t size, uint8_t *buffer);
-int arm7_9_setup(target_t *target);
-int arm7_9_assert_reset(target_t *target);
-int arm7_9_deassert_reset(target_t *target);
-int arm7_9_reset_request_halt(target_t *target);
-int arm7_9_early_halt(target_t *target);
-int arm7_9_soft_reset_halt(struct target_s *target);
-int arm7_9_prepare_reset_halt(struct target_s *target);
+int arm7_9_setup(struct target *target);
+int arm7_9_assert_reset(struct target *target);
+int arm7_9_deassert_reset(struct target *target);
+int arm7_9_reset_request_halt(struct target *target);
+int arm7_9_early_halt(struct target *target);
+int arm7_9_soft_reset_halt(struct target *target);
+int arm7_9_prepare_reset_halt(struct target *target);
-int arm7_9_halt(target_t *target);
-int arm7_9_full_context(target_t *target);
-int arm7_9_restore_context(target_t *target);
-int arm7_9_resume(struct target_s *target, int current, uint32_t address, int handle_breakpoints, int debug_execution);
-int arm7_9_step(struct target_s *target, int current, uint32_t address, int handle_breakpoints);
-int arm7_9_read_core_reg(struct target_s *target, int num, enum armv4_5_mode mode);
-int arm7_9_read_memory(struct target_s *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer);
-int arm7_9_write_memory(struct target_s *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer);
-int arm7_9_bulk_write_memory(target_t *target, uint32_t address, uint32_t count, uint8_t *buffer);
-int arm7_9_checksum_memory(struct target_s *target, uint32_t address, uint32_t count, uint32_t* checksum);
-int arm7_9_blank_check_memory(struct target_s *target, uint32_t address, uint32_t count, uint32_t* blank);
+int arm7_9_halt(struct target *target);
+int arm7_9_full_context(struct target *target);
+int arm7_9_restore_context(struct target *target);
+int arm7_9_resume(struct target *target, int current, uint32_t address, int handle_breakpoints, int debug_execution);
+int arm7_9_step(struct target *target, int current, uint32_t address, int handle_breakpoints);
+int arm7_9_read_core_reg(struct target *target, int num, enum armv4_5_mode mode);
+int arm7_9_read_memory(struct target *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer);
+int arm7_9_write_memory(struct target *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer);
+int arm7_9_bulk_write_memory(struct target *target, uint32_t address, uint32_t count, uint8_t *buffer);
+int arm7_9_checksum_memory(struct target *target, uint32_t address, uint32_t count, uint32_t* checksum);
+int arm7_9_blank_check_memory(struct target *target, uint32_t address, uint32_t count, uint32_t* blank);
-int arm7_9_run_algorithm(struct target_s *target, int num_mem_params, struct mem_param *mem_params, int num_reg_prams, struct reg_param *reg_param, uint32_t entry_point, void *arch_info);
+int arm7_9_run_algorithm(struct target *target, int num_mem_params, struct mem_param *mem_params, int num_reg_prams, struct reg_param *reg_param, uint32_t entry_point, void *arch_info);
-int arm7_9_add_breakpoint(struct target_s *target, struct breakpoint *breakpoint);
-int arm7_9_remove_breakpoint(struct target_s *target, struct breakpoint *breakpoint);
-int arm7_9_add_watchpoint(struct target_s *target, struct watchpoint *watchpoint);
-int arm7_9_remove_watchpoint(struct target_s *target, struct watchpoint *watchpoint);
+int arm7_9_add_breakpoint(struct target *target, struct breakpoint *breakpoint);
+int arm7_9_remove_breakpoint(struct target *target, struct breakpoint *breakpoint);
+int arm7_9_add_watchpoint(struct target *target, struct watchpoint *watchpoint);
+int arm7_9_remove_watchpoint(struct target *target, struct watchpoint *watchpoint);
-void arm7_9_enable_eice_step(target_t *target, uint32_t next_pc);
-void arm7_9_disable_eice_step(target_t *target);
+void arm7_9_enable_eice_step(struct target *target, uint32_t next_pc);
+void arm7_9_disable_eice_step(struct target *target);
-int arm7_9_execute_sys_speed(struct target_s *target);
+int arm7_9_execute_sys_speed(struct target *target);
-int arm7_9_init_arch_info(target_t *target, struct arm7_9_common *arm7_9);
-int arm7_9_get_arch_pointers(target_t *target, struct arm **armv4_5_p, struct arm7_9_common **arm7_9_p);
+int arm7_9_init_arch_info(struct target *target, struct arm7_9_common *arm7_9);
+int arm7_9_get_arch_pointers(struct target *target, struct arm **armv4_5_p, struct arm7_9_common **arm7_9_p);
#endif /* ARM7_9_COMMON_H */
#define _DEBUG_INSTRUCTION_EXECUTION_
#endif
-static int arm7tdmi_examine_debug_reason(target_t *target)
+static int arm7tdmi_examine_debug_reason(struct target *target)
{
int retval = ERROR_OK;
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
return ERROR_OK;
}
-static void arm7tdmi_change_to_arm(target_t *target,
+static void arm7tdmi_change_to_arm(struct target *target,
uint32_t *r0, uint32_t *pc)
{
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
* The solution is to arrange for a large out/in scan in this loop and
* and convert data afterwards.
*/
-static void arm7tdmi_read_core_regs(target_t *target,
+static void arm7tdmi_read_core_regs(struct target *target,
uint32_t mask, uint32_t* core_regs[16])
{
int i;
}
}
-static void arm7tdmi_read_core_regs_target_buffer(target_t *target,
+static void arm7tdmi_read_core_regs_target_buffer(struct target *target,
uint32_t mask, void* buffer, int size)
{
int i;
}
}
-static void arm7tdmi_read_xpsr(target_t *target, uint32_t *xpsr, int spsr)
+static void arm7tdmi_read_xpsr(struct target *target, uint32_t *xpsr, int spsr)
{
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
struct arm_jtag *jtag_info = &arm7_9->jtag_info;
arm7tdmi_clock_data_in(jtag_info, xpsr);
}
-static void arm7tdmi_write_xpsr(target_t *target, uint32_t xpsr, int spsr)
+static void arm7tdmi_write_xpsr(struct target *target, uint32_t xpsr, int spsr)
{
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
struct arm_jtag *jtag_info = &arm7_9->jtag_info;
arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0);
}
-static void arm7tdmi_write_xpsr_im8(target_t *target,
+static void arm7tdmi_write_xpsr_im8(struct target *target,
uint8_t xpsr_im, int rot, int spsr)
{
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0);
}
-static void arm7tdmi_write_core_regs(target_t *target,
+static void arm7tdmi_write_core_regs(struct target *target,
uint32_t mask, uint32_t core_regs[16])
{
int i;
arm7tdmi_clock_out_inner(jtag_info, ARMV4_5_NOP, 0);
}
-static void arm7tdmi_load_word_regs(target_t *target, uint32_t mask)
+static void arm7tdmi_load_word_regs(struct target *target, uint32_t mask)
{
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
struct arm_jtag *jtag_info = &arm7_9->jtag_info;
arm7tdmi_clock_out(jtag_info, ARMV4_5_LDMIA(0, mask & 0xffff, 0, 1), NULL, 0);
}
-static void arm7tdmi_load_hword_reg(target_t *target, int num)
+static void arm7tdmi_load_hword_reg(struct target *target, int num)
{
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
struct arm_jtag *jtag_info = &arm7_9->jtag_info;
arm7tdmi_clock_out(jtag_info, ARMV4_5_LDRH_IP(num, 0), NULL, 0);
}
-static void arm7tdmi_load_byte_reg(target_t *target, int num)
+static void arm7tdmi_load_byte_reg(struct target *target, int num)
{
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
struct arm_jtag *jtag_info = &arm7_9->jtag_info;
arm7tdmi_clock_out(jtag_info, ARMV4_5_LDRB_IP(num, 0), NULL, 0);
}
-static void arm7tdmi_store_word_regs(target_t *target, uint32_t mask)
+static void arm7tdmi_store_word_regs(struct target *target, uint32_t mask)
{
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
struct arm_jtag *jtag_info = &arm7_9->jtag_info;
arm7tdmi_clock_out(jtag_info, ARMV4_5_STMIA(0, mask, 0, 1), NULL, 0);
}
-static void arm7tdmi_store_hword_reg(target_t *target, int num)
+static void arm7tdmi_store_hword_reg(struct target *target, int num)
{
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
struct arm_jtag *jtag_info = &arm7_9->jtag_info;
arm7tdmi_clock_out(jtag_info, ARMV4_5_STRH_IP(num, 0), NULL, 0);
}
-static void arm7tdmi_store_byte_reg(target_t *target, int num)
+static void arm7tdmi_store_byte_reg(struct target *target, int num)
{
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
struct arm_jtag *jtag_info = &arm7_9->jtag_info;
arm7tdmi_clock_out(jtag_info, ARMV4_5_STRB_IP(num, 0), NULL, 0);
}
-static void arm7tdmi_write_pc(target_t *target, uint32_t pc)
+static void arm7tdmi_write_pc(struct target *target, uint32_t pc)
{
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
struct arm_jtag *jtag_info = &arm7_9->jtag_info;
arm7tdmi_clock_out_inner(jtag_info, ARMV4_5_NOP, 0);
}
-static void arm7tdmi_branch_resume(target_t *target)
+static void arm7tdmi_branch_resume(struct target *target)
{
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
struct arm_jtag *jtag_info = &arm7_9->jtag_info;
arm7tdmi_clock_out_inner(jtag_info, ARMV4_5_B(0xfffffa, 0), 0);
}
-static void arm7tdmi_branch_resume_thumb(target_t *target)
+static void arm7tdmi_branch_resume_thumb(struct target *target)
{
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
struct armv4_5_common_s *armv4_5 = &arm7_9->armv4_5_common;
arm7tdmi_clock_out(jtag_info, ARMV4_5_T_B(0x7f8), NULL, 0);
}
-static void arm7tdmi_build_reg_cache(target_t *target)
+static void arm7tdmi_build_reg_cache(struct target *target)
{
struct reg_cache **cache_p = register_get_last_cache_p(&target->reg_cache);
struct armv4_5_common_s *armv4_5 = target_to_armv4_5(target);
armv4_5->core_cache = (*cache_p);
}
-int arm7tdmi_examine(struct target_s *target)
+int arm7tdmi_examine(struct target *target)
{
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
int retval;
return ERROR_OK;
}
-int arm7tdmi_init_target(struct command_context_s *cmd_ctx, struct target_s *target)
+int arm7tdmi_init_target(struct command_context_s *cmd_ctx, struct target *target)
{
arm7tdmi_build_reg_cache(target);
return ERROR_OK;
}
-int arm7tdmi_init_arch_info(target_t *target, struct arm7tdmi_common *arm7tdmi, struct jtag_tap *tap)
+int arm7tdmi_init_arch_info(struct target *target, struct arm7tdmi_common *arm7tdmi, struct jtag_tap *tap)
{
struct arm7_9_common *arm7_9 = &arm7tdmi->arm7_9_common;
return ERROR_OK;
}
-static int arm7tdmi_target_create(struct target_s *target, Jim_Interp *interp)
+static int arm7tdmi_target_create(struct target *target, Jim_Interp *interp)
{
struct arm7tdmi_common *arm7tdmi;
struct arm7_9_common arm7_9_common;
};
-int arm7tdmi_init_arch_info(target_t *target, struct arm7tdmi_common *arm7tdmi, struct jtag_tap *tap);
-int arm7tdmi_init_target(struct command_context_s *cmd_ctx, struct target_s *target);
-int arm7tdmi_examine(struct target_s *target);
+int arm7tdmi_init_arch_info(struct target *target, struct arm7tdmi_common *arm7tdmi, struct jtag_tap *tap);
+int arm7tdmi_init_target(struct command_context_s *cmd_ctx, struct target *target);
+int arm7tdmi_examine(struct target *target);
#endif /* ARM7TDMI_H */
#define ARM920T_CP15_PHYS_ADDR(x, y, z) ((x << 5) | (y << 1) << (z))
-static int arm920t_read_cp15_physical(target_t *target,
+static int arm920t_read_cp15_physical(struct target *target,
int reg_addr, uint32_t *value)
{
struct arm920t_common *arm920t = target_to_arm920(target);
return ERROR_OK;
}
-static int arm920t_write_cp15_physical(target_t *target,
+static int arm920t_write_cp15_physical(struct target *target,
int reg_addr, uint32_t value)
{
struct arm920t_common *arm920t = target_to_arm920(target);
return ERROR_OK;
}
-static int arm920t_execute_cp15(target_t *target, uint32_t cp15_opcode,
+static int arm920t_execute_cp15(struct target *target, uint32_t cp15_opcode,
uint32_t arm_opcode)
{
int retval;
return ERROR_OK;
}
-static int arm920t_read_cp15_interpreted(target_t *target,
+static int arm920t_read_cp15_interpreted(struct target *target,
uint32_t cp15_opcode, uint32_t address, uint32_t *value)
{
struct armv4_5_common_s *armv4_5 = target_to_armv4_5(target);
}
static
-int arm920t_write_cp15_interpreted(target_t *target,
+int arm920t_write_cp15_interpreted(struct target *target,
uint32_t cp15_opcode, uint32_t value, uint32_t address)
{
uint32_t cp15c15 = 0x0;
}
// EXPORTED to FA256
-uint32_t arm920t_get_ttb(target_t *target)
+uint32_t arm920t_get_ttb(struct target *target)
{
int retval;
uint32_t ttb = 0x0;
}
// EXPORTED to FA256
-void arm920t_disable_mmu_caches(target_t *target, int mmu, int d_u_cache, int i_cache)
+void arm920t_disable_mmu_caches(struct target *target, int mmu, int d_u_cache, int i_cache)
{
uint32_t cp15_control;
}
// EXPORTED to FA256
-void arm920t_enable_mmu_caches(target_t *target, int mmu, int d_u_cache, int i_cache)
+void arm920t_enable_mmu_caches(struct target *target, int mmu, int d_u_cache, int i_cache)
{
uint32_t cp15_control;
}
// EXPORTED to FA256
-void arm920t_post_debug_entry(target_t *target)
+void arm920t_post_debug_entry(struct target *target)
{
uint32_t cp15c15;
struct arm920t_common *arm920t = target_to_arm920(target);
}
// EXPORTED to FA256
-void arm920t_pre_restore_context(target_t *target)
+void arm920t_pre_restore_context(struct target *target)
{
uint32_t cp15c15;
struct arm920t_common *arm920t = target_to_arm920(target);
}
/** Logs summary of ARM920 state for a halted target. */
-int arm920t_arch_state(struct target_s *target)
+int arm920t_arch_state(struct target *target)
{
static const char *state[] =
{
return ERROR_OK;
}
-static int arm920_mmu(struct target_s *target, int *enabled)
+static int arm920_mmu(struct target *target, int *enabled)
{
if (target->state != TARGET_HALTED) {
LOG_ERROR("%s: target not halted", __func__);
return ERROR_OK;
}
-static int arm920_virt2phys(struct target_s *target,
+static int arm920_virt2phys(struct target *target,
uint32_t virt, uint32_t *phys)
{
/** @todo Implement this! */
}
/** Reads a buffer, in the specified word size, with current MMU settings. */
-int arm920t_read_memory(struct target_s *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer)
+int arm920t_read_memory(struct target *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer)
{
int retval;
}
-static int arm920t_read_phys_memory(struct target_s *target,
+static int arm920t_read_phys_memory(struct target *target,
uint32_t address, uint32_t size,
uint32_t count, uint8_t *buffer)
{
address, size, count, buffer);
}
-static int arm920t_write_phys_memory(struct target_s *target,
+static int arm920t_write_phys_memory(struct target *target,
uint32_t address, uint32_t size,
uint32_t count, uint8_t *buffer)
{
/** Writes a buffer, in the specified word size, with current MMU settings. */
-int arm920t_write_memory(struct target_s *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer)
+int arm920t_write_memory(struct target *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer)
{
int retval;
}
// EXPORTED to FA256
-int arm920t_soft_reset_halt(struct target_s *target)
+int arm920t_soft_reset_halt(struct target *target)
{
int retval = ERROR_OK;
struct arm920t_common *arm920t = target_to_arm920(target);
return ERROR_OK;
}
-int arm920t_init_arch_info(target_t *target, struct arm920t_common *arm920t, struct jtag_tap *tap)
+int arm920t_init_arch_info(struct target *target, struct arm920t_common *arm920t, struct jtag_tap *tap)
{
struct arm9tdmi_common *arm9tdmi = &arm920t->arm9tdmi_common;
struct arm7_9_common *arm7_9 = &arm9tdmi->arm7_9_common;
return ERROR_OK;
}
-static int arm920t_target_create(struct target_s *target, Jim_Interp *interp)
+static int arm920t_target_create(struct target *target, Jim_Interp *interp)
{
struct arm920t_common *arm920t = calloc(1,sizeof(struct arm920t_common));
COMMAND_HANDLER(arm920t_handle_read_cache_command)
{
int retval = ERROR_OK;
- target_t *target = get_current_target(cmd_ctx);
+ struct target *target = get_current_target(cmd_ctx);
struct arm920t_common *arm920t = target_to_arm920(target);
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
struct armv4_5_common_s *armv4_5 = &arm7_9->armv4_5_common;
COMMAND_HANDLER(arm920t_handle_read_mmu_command)
{
int retval = ERROR_OK;
- target_t *target = get_current_target(cmd_ctx);
+ struct target *target = get_current_target(cmd_ctx);
struct arm920t_common *arm920t = target_to_arm920(target);
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
struct armv4_5_common_s *armv4_5 = &arm7_9->armv4_5_common;
COMMAND_HANDLER(arm920t_handle_cp15_command)
{
int retval;
- target_t *target = get_current_target(cmd_ctx);
+ struct target *target = get_current_target(cmd_ctx);
struct arm920t_common *arm920t = target_to_arm920(target);
retval = arm920t_verify_pointer(cmd_ctx, arm920t);
COMMAND_HANDLER(arm920t_handle_cp15i_command)
{
int retval;
- target_t *target = get_current_target(cmd_ctx);
+ struct target *target = get_current_target(cmd_ctx);
struct arm920t_common *arm920t = target_to_arm920(target);
retval = arm920t_verify_pointer(cmd_ctx, arm920t);
COMMAND_HANDLER(arm920t_handle_cache_info_command)
{
int retval;
- target_t *target = get_current_target(cmd_ctx);
+ struct target *target = get_current_target(cmd_ctx);
struct arm920t_common *arm920t = target_to_arm920(target);
retval = arm920t_verify_pointer(cmd_ctx, arm920t);
}
-static int arm920t_mrc(target_t *target, int cpnum, uint32_t op1, uint32_t op2, uint32_t CRn, uint32_t CRm, uint32_t *value)
+static int arm920t_mrc(struct target *target, int cpnum, uint32_t op1, uint32_t op2, uint32_t CRn, uint32_t CRm, uint32_t *value)
{
if (cpnum!=15)
{
return arm920t_read_cp15_interpreted(target, mrc_opcode(cpnum, op1, op2, CRn, CRm), 0, value);
}
-static int arm920t_mcr(target_t *target, int cpnum, uint32_t op1, uint32_t op2, uint32_t CRn, uint32_t CRm, uint32_t value)
+static int arm920t_mcr(struct target *target, int cpnum, uint32_t op1, uint32_t op2, uint32_t CRn, uint32_t CRm, uint32_t value)
{
if (cpnum!=15)
{
};
static inline struct arm920t_common *
-target_to_arm920(struct target_s *target)
+target_to_arm920(struct target *target)
{
return container_of(target->arch_info, struct arm920t_common,
arm9tdmi_common.arm7_9_common.armv4_5_common);
uint32_t ram2;
};
-int arm920t_arch_state(struct target_s *target);
-int arm920t_soft_reset_halt(struct target_s *target);
-int arm920t_read_memory(struct target_s *target,
+int arm920t_arch_state(struct target *target);
+int arm920t_soft_reset_halt(struct target *target);
+int arm920t_read_memory(struct target *target,
uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer);
-int arm920t_write_memory(struct target_s *target,
+int arm920t_write_memory(struct target *target,
uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer);
-void arm920t_post_debug_entry(target_t *target);
-void arm920t_pre_restore_context(target_t *target);
- uint32_t arm920t_get_ttb(target_t *target);
-void arm920t_disable_mmu_caches(target_t *target,
+void arm920t_post_debug_entry(struct target *target);
+void arm920t_pre_restore_context(struct target *target);
+ uint32_t arm920t_get_ttb(struct target *target);
+void arm920t_disable_mmu_caches(struct target *target,
int mmu, int d_u_cache, int i_cache);
-void arm920t_enable_mmu_caches(target_t *target,
+void arm920t_enable_mmu_caches(struct target *target,
int mmu, int d_u_cache, int i_cache);
int arm920t_register_commands(struct command_context_s *cmd_ctx);
#define ARM926EJS_CP15_ADDR(opcode_1, opcode_2, CRn, CRm) ((opcode_1 << 11) | (opcode_2 << 8) | (CRn << 4) | (CRm << 0))
-static int arm926ejs_cp15_read(target_t *target, uint32_t op1, uint32_t op2,
+static int arm926ejs_cp15_read(struct target *target, uint32_t op1, uint32_t op2,
uint32_t CRn, uint32_t CRm, uint32_t *value)
{
int retval = ERROR_OK;
return ERROR_OK;
}
-static int arm926ejs_mrc(target_t *target, int cpnum, uint32_t op1,
+static int arm926ejs_mrc(struct target *target, int cpnum, uint32_t op1,
uint32_t op2, uint32_t CRn, uint32_t CRm, uint32_t *value)
{
if (cpnum != 15) {
return arm926ejs_cp15_read(target, op1, op2, CRn, CRm, value);
}
-static int arm926ejs_cp15_write(target_t *target, uint32_t op1, uint32_t op2,
+static int arm926ejs_cp15_write(struct target *target, uint32_t op1, uint32_t op2,
uint32_t CRn, uint32_t CRm, uint32_t value)
{
int retval = ERROR_OK;
return ERROR_OK;
}
-static int arm926ejs_mcr(target_t *target, int cpnum, uint32_t op1,
+static int arm926ejs_mcr(struct target *target, int cpnum, uint32_t op1,
uint32_t op2, uint32_t CRn, uint32_t CRm, uint32_t value)
{
if (cpnum != 15) {
return arm926ejs_cp15_write(target, op1, op2, CRn, CRm, value);
}
-static int arm926ejs_examine_debug_reason(target_t *target)
+static int arm926ejs_examine_debug_reason(struct target *target)
{
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
struct reg *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
return ERROR_OK;
}
-static uint32_t arm926ejs_get_ttb(target_t *target)
+static uint32_t arm926ejs_get_ttb(struct target *target)
{
struct arm926ejs_common *arm926ejs = target_to_arm926(target);
int retval;
return ttb;
}
-static void arm926ejs_disable_mmu_caches(target_t *target, int mmu,
+static void arm926ejs_disable_mmu_caches(struct target *target, int mmu,
int d_u_cache, int i_cache)
{
struct arm926ejs_common *arm926ejs = target_to_arm926(target);
arm926ejs->write_cp15(target, 0, 0, 1, 0, cp15_control);
}
-static void arm926ejs_enable_mmu_caches(target_t *target, int mmu,
+static void arm926ejs_enable_mmu_caches(struct target *target, int mmu,
int d_u_cache, int i_cache)
{
struct arm926ejs_common *arm926ejs = target_to_arm926(target);
arm926ejs->write_cp15(target, 0, 0, 1, 0, cp15_control);
}
-static void arm926ejs_post_debug_entry(target_t *target)
+static void arm926ejs_post_debug_entry(struct target *target)
{
struct arm926ejs_common *arm926ejs = target_to_arm926(target);
arm926ejs->write_cp15(target, 7, 0, 15, 0, cache_dbg_ctrl);
}
-static void arm926ejs_pre_restore_context(target_t *target)
+static void arm926ejs_pre_restore_context(struct target *target)
{
struct arm926ejs_common *arm926ejs = target_to_arm926(target);
}
/** Logs summary of ARM926 state for a halted target. */
-int arm926ejs_arch_state(struct target_s *target)
+int arm926ejs_arch_state(struct target *target)
{
static const char *state[] =
{
return ERROR_OK;
}
-int arm926ejs_soft_reset_halt(struct target_s *target)
+int arm926ejs_soft_reset_halt(struct target *target)
{
int retval = ERROR_OK;
struct arm926ejs_common *arm926ejs = target_to_arm926(target);
}
/** Writes a buffer, in the specified word size, with current MMU settings. */
-int arm926ejs_write_memory(struct target_s *target, uint32_t address,
+int arm926ejs_write_memory(struct target *target, uint32_t address,
uint32_t size, uint32_t count, uint8_t *buffer)
{
int retval;
return retval;
}
-static int arm926ejs_write_phys_memory(struct target_s *target,
+static int arm926ejs_write_phys_memory(struct target *target,
uint32_t address, uint32_t size,
uint32_t count, uint8_t *buffer)
{
address, size, count, buffer);
}
-static int arm926ejs_read_phys_memory(struct target_s *target,
+static int arm926ejs_read_phys_memory(struct target *target,
uint32_t address, uint32_t size,
uint32_t count, uint8_t *buffer)
{
address, size, count, buffer);
}
-int arm926ejs_init_arch_info(target_t *target, struct arm926ejs_common *arm926ejs,
+int arm926ejs_init_arch_info(struct target *target, struct arm926ejs_common *arm926ejs,
struct jtag_tap *tap)
{
struct arm9tdmi_common *arm9tdmi = &arm926ejs->arm9tdmi_common;
return ERROR_OK;
}
-static int arm926ejs_target_create(struct target_s *target, Jim_Interp *interp)
+static int arm926ejs_target_create(struct target *target, Jim_Interp *interp)
{
struct arm926ejs_common *arm926ejs = calloc(1,sizeof(struct arm926ejs_common));
COMMAND_HANDLER(arm926ejs_handle_cp15_command)
{
int retval;
- target_t *target = get_current_target(cmd_ctx);
+ struct target *target = get_current_target(cmd_ctx);
struct arm926ejs_common *arm926ejs = target_to_arm926(target);
int opcode_1;
int opcode_2;
COMMAND_HANDLER(arm926ejs_handle_cache_info_command)
{
int retval;
- target_t *target = get_current_target(cmd_ctx);
+ struct target *target = get_current_target(cmd_ctx);
struct arm926ejs_common *arm926ejs = target_to_arm926(target);
retval = arm926ejs_verify_pointer(cmd_ctx, arm926ejs);
return armv4_5_handle_cache_info_command(cmd_ctx, &arm926ejs->armv4_5_mmu.armv4_5_cache);
}
-static int arm926ejs_virt2phys(struct target_s *target, uint32_t virtual, uint32_t *physical)
+static int arm926ejs_virt2phys(struct target *target, uint32_t virtual, uint32_t *physical)
{
int type;
uint32_t cb;
return ERROR_OK;
}
-static int arm926ejs_mmu(struct target_s *target, int *enabled)
+static int arm926ejs_mmu(struct target *target, int *enabled)
{
struct arm926ejs_common *arm926ejs = target_to_arm926(target);
struct arm9tdmi_common arm9tdmi_common;
uint32_t common_magic;
struct armv4_5_mmu_common armv4_5_mmu;
- int (*read_cp15)(target_t *target, uint32_t op1, uint32_t op2, uint32_t CRn, uint32_t CRm, uint32_t *value);
- int (*write_cp15)(target_t *target, uint32_t op1, uint32_t op2, uint32_t CRn, uint32_t CRm, uint32_t value);
+ int (*read_cp15)(struct target *target, uint32_t op1, uint32_t op2, uint32_t CRn, uint32_t CRm, uint32_t *value);
+ int (*write_cp15)(struct target *target, uint32_t op1, uint32_t op2, uint32_t CRn, uint32_t CRm, uint32_t value);
uint32_t cp15_control_reg;
uint32_t d_fsr;
uint32_t i_fsr;
};
static inline struct arm926ejs_common *
-target_to_arm926(struct target_s *target)
+target_to_arm926(struct target *target)
{
return container_of(target->arch_info, struct arm926ejs_common,
arm9tdmi_common.arm7_9_common.armv4_5_common);
}
-int arm926ejs_init_arch_info(target_t *target,
+int arm926ejs_init_arch_info(struct target *target,
struct arm926ejs_common *arm926ejs, struct jtag_tap *tap);
int arm926ejs_register_commands(struct command_context_s *cmd_ctx);
-int arm926ejs_arch_state(struct target_s *target);
-int arm926ejs_write_memory(struct target_s *target,
+int arm926ejs_arch_state(struct target *target);
+int arm926ejs_write_memory(struct target *target,
uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer);
-int arm926ejs_soft_reset_halt(struct target_s *target);
+int arm926ejs_soft_reset_halt(struct target *target);
#endif /* ARM926EJS_H */
#define _DEBUG_INSTRUCTION_EXECUTION_
#endif
-int arm966e_init_arch_info(target_t *target, struct arm966e_common *arm966e, struct jtag_tap *tap)
+int arm966e_init_arch_info(struct target *target, struct arm966e_common *arm966e, struct jtag_tap *tap)
{
struct arm9tdmi_common *arm9tdmi = &arm966e->arm9tdmi_common;
struct arm7_9_common *arm7_9 = &arm9tdmi->arm7_9_common;
return ERROR_OK;
}
-static int arm966e_target_create(struct target_s *target, Jim_Interp *interp)
+static int arm966e_target_create(struct target *target, Jim_Interp *interp)
{
struct arm966e_common *arm966e = calloc(1,sizeof(struct arm966e_common));
return ERROR_OK;
}
-static int arm966e_read_cp15(target_t *target, int reg_addr, uint32_t *value)
+static int arm966e_read_cp15(struct target *target, int reg_addr, uint32_t *value)
{
int retval = ERROR_OK;
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
}
// EXPORTED to str9x (flash)
-int arm966e_write_cp15(target_t *target, int reg_addr, uint32_t value)
+int arm966e_write_cp15(struct target *target, int reg_addr, uint32_t value)
{
int retval = ERROR_OK;
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
COMMAND_HANDLER(arm966e_handle_cp15_command)
{
int retval;
- target_t *target = get_current_target(cmd_ctx);
+ struct target *target = get_current_target(cmd_ctx);
struct arm966e_common *arm966e = target_to_arm966(target);
retval = arm966e_verify_pointer(cmd_ctx, arm966e);
};
static inline struct arm966e_common *
-target_to_arm966(struct target_s *target)
+target_to_arm966(struct target *target)
{
return container_of(target->arch_info, struct arm966e_common,
arm9tdmi_common.arm7_9_common.armv4_5_common);
}
-int arm966e_init_arch_info(target_t *target,
+int arm966e_init_arch_info(struct target *target,
struct arm966e_common *arm966e, struct jtag_tap *tap);
int arm966e_register_commands(struct command_context_s *cmd_ctx);
-int arm966e_write_cp15(target_t *target, int reg_addr, uint32_t value);
+int arm966e_write_cp15(struct target *target, int reg_addr, uint32_t value);
#endif /* ARM966E_H */
{0, 0},
};
-int arm9tdmi_examine_debug_reason(target_t *target)
+int arm9tdmi_examine_debug_reason(struct target *target)
{
int retval = ERROR_OK;
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
return ERROR_OK;
}
-static void arm9tdmi_change_to_arm(target_t *target,
+static void arm9tdmi_change_to_arm(struct target *target,
uint32_t *r0, uint32_t *pc)
{
int retval = ERROR_OK;
*pc -= 0xc;
}
-void arm9tdmi_read_core_regs(target_t *target,
+void arm9tdmi_read_core_regs(struct target *target,
uint32_t mask, uint32_t* core_regs[16])
{
int i;
}
}
-static void arm9tdmi_read_core_regs_target_buffer(target_t *target,
+static void arm9tdmi_read_core_regs_target_buffer(struct target *target,
uint32_t mask, void* buffer, int size)
{
int i;
}
}
-static void arm9tdmi_read_xpsr(target_t *target, uint32_t *xpsr, int spsr)
+static void arm9tdmi_read_xpsr(struct target *target, uint32_t *xpsr, int spsr)
{
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
struct arm_jtag *jtag_info = &arm7_9->jtag_info;
arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, xpsr, 0);
}
-static void arm9tdmi_write_xpsr(target_t *target, uint32_t xpsr, int spsr)
+static void arm9tdmi_write_xpsr(struct target *target, uint32_t xpsr, int spsr)
{
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
struct arm_jtag *jtag_info = &arm7_9->jtag_info;
arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
}
-static void arm9tdmi_write_xpsr_im8(target_t *target,
+static void arm9tdmi_write_xpsr_im8(struct target *target,
uint8_t xpsr_im, int rot, int spsr)
{
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
}
}
-void arm9tdmi_write_core_regs(target_t *target,
+void arm9tdmi_write_core_regs(struct target *target,
uint32_t mask, uint32_t core_regs[16])
{
int i;
arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
}
-void arm9tdmi_load_word_regs(target_t *target, uint32_t mask)
+void arm9tdmi_load_word_regs(struct target *target, uint32_t mask)
{
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
struct arm_jtag *jtag_info = &arm7_9->jtag_info;
arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 1);
}
-void arm9tdmi_load_hword_reg(target_t *target, int num)
+void arm9tdmi_load_hword_reg(struct target *target, int num)
{
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
struct arm_jtag *jtag_info = &arm7_9->jtag_info;
arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 1);
}
-void arm9tdmi_load_byte_reg(target_t *target, int num)
+void arm9tdmi_load_byte_reg(struct target *target, int num)
{
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
struct arm_jtag *jtag_info = &arm7_9->jtag_info;
arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 1);
}
-void arm9tdmi_store_word_regs(target_t *target, uint32_t mask)
+void arm9tdmi_store_word_regs(struct target *target, uint32_t mask)
{
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
struct arm_jtag *jtag_info = &arm7_9->jtag_info;
arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 1);
}
-void arm9tdmi_store_hword_reg(target_t *target, int num)
+void arm9tdmi_store_hword_reg(struct target *target, int num)
{
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
struct arm_jtag *jtag_info = &arm7_9->jtag_info;
arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 1);
}
-void arm9tdmi_store_byte_reg(target_t *target, int num)
+void arm9tdmi_store_byte_reg(struct target *target, int num)
{
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
struct arm_jtag *jtag_info = &arm7_9->jtag_info;
arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 1);
}
-static void arm9tdmi_write_pc(target_t *target, uint32_t pc)
+static void arm9tdmi_write_pc(struct target *target, uint32_t pc)
{
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
struct arm_jtag *jtag_info = &arm7_9->jtag_info;
arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
}
-void arm9tdmi_branch_resume(target_t *target)
+void arm9tdmi_branch_resume(struct target *target)
{
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
struct arm_jtag *jtag_info = &arm7_9->jtag_info;
arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 1);
}
-static void arm9tdmi_branch_resume_thumb(target_t *target)
+static void arm9tdmi_branch_resume_thumb(struct target *target)
{
LOG_DEBUG("-");
arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
}
-void arm9tdmi_enable_single_step(target_t *target, uint32_t next_pc)
+void arm9tdmi_enable_single_step(struct target *target, uint32_t next_pc)
{
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
}
}
-void arm9tdmi_disable_single_step(target_t *target)
+void arm9tdmi_disable_single_step(struct target *target)
{
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
}
}
-static void arm9tdmi_build_reg_cache(target_t *target)
+static void arm9tdmi_build_reg_cache(struct target *target)
{
struct reg_cache **cache_p = register_get_last_cache_p(&target->reg_cache);
struct armv4_5_common_s *armv4_5 = target_to_armv4_5(target);
armv4_5->core_cache = (*cache_p);
}
-int arm9tdmi_examine(struct target_s *target)
+int arm9tdmi_examine(struct target *target)
{
int retval;
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
}
int arm9tdmi_init_target(struct command_context_s *cmd_ctx,
- struct target_s *target)
+ struct target *target)
{
arm9tdmi_build_reg_cache(target);
return ERROR_OK;
}
-int arm9tdmi_init_arch_info(target_t *target, struct arm9tdmi_common *arm9tdmi, struct jtag_tap *tap)
+int arm9tdmi_init_arch_info(struct target *target, struct arm9tdmi_common *arm9tdmi, struct jtag_tap *tap)
{
struct arm *armv4_5;
struct arm7_9_common *arm7_9;
return ERROR_OK;
}
-static int arm9tdmi_target_create(struct target_s *target, Jim_Interp *interp)
+static int arm9tdmi_target_create(struct target *target, Jim_Interp *interp)
{
struct arm9tdmi_common *arm9tdmi = calloc(1,sizeof(struct arm9tdmi_common));
COMMAND_HANDLER(handle_arm9tdmi_catch_vectors_command)
{
- target_t *target = get_current_target(cmd_ctx);
+ struct target *target = get_current_target(cmd_ctx);
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
struct reg *vector_catch;
uint32_t vector_catch_value;
};
int arm9tdmi_init_target(struct command_context_s *cmd_ctx,
- struct target_s *target);
-int arm9tdmi_examine(struct target_s *target);
-int arm9tdmi_init_arch_info(target_t *target,
+ struct target *target);
+int arm9tdmi_examine(struct target *target);
+int arm9tdmi_init_arch_info(struct target *target,
struct arm9tdmi_common *arm9tdmi, struct jtag_tap *tap);
int arm9tdmi_register_commands(struct command_context_s *cmd_ctx);
int arm9tdmi_clock_data_in(struct arm_jtag *jtag_info, uint32_t *in);
int arm9tdmi_clock_data_in_endianness(struct arm_jtag *jtag_info,
void *in, int size, int be);
-void arm9tdmi_read_core_regs(target_t *target,
+void arm9tdmi_read_core_regs(struct target *target,
uint32_t mask, uint32_t* core_regs[16]);
-void arm9tdmi_write_core_regs(target_t *target,
+void arm9tdmi_write_core_regs(struct target *target,
uint32_t mask, uint32_t core_regs[16]);
-int arm9tdmi_examine_debug_reason(target_t *target);
+int arm9tdmi_examine_debug_reason(struct target *target);
-void arm9tdmi_load_word_regs(target_t *target, uint32_t mask);
-void arm9tdmi_load_hword_reg(target_t *target, int num);
-void arm9tdmi_load_byte_reg(target_t *target, int num);
-void arm9tdmi_store_word_regs(target_t *target, uint32_t mask);
-void arm9tdmi_store_hword_reg(target_t *target, int num);
-void arm9tdmi_store_byte_reg(target_t *target, int num);
+void arm9tdmi_load_word_regs(struct target *target, uint32_t mask);
+void arm9tdmi_load_hword_reg(struct target *target, int num);
+void arm9tdmi_load_byte_reg(struct target *target, int num);
+void arm9tdmi_store_word_regs(struct target *target, uint32_t mask);
+void arm9tdmi_store_hword_reg(struct target *target, int num);
+void arm9tdmi_store_byte_reg(struct target *target, int num);
-void arm9tdmi_branch_resume(target_t *target);
-void arm9tdmi_enable_single_step(target_t *target, uint32_t next_pc);
-void arm9tdmi_disable_single_step(target_t *target);
+void arm9tdmi_branch_resume(struct target *target);
+void arm9tdmi_enable_single_step(struct target *target, uint32_t next_pc);
+void arm9tdmi_disable_single_step(struct target *target);
#endif /* ARM9TDMI_H */
* always set. That means eventual arm_simulate_step() support for Thumb2
* will need work in this area.
*/
-int thumb2_opcode(target_t *target, uint32_t address, struct arm_instruction *instruction)
+int thumb2_opcode(struct target *target, uint32_t address, struct arm_instruction *instruction)
{
int retval;
uint16_t op;
struct arm_instruction *instruction);
int thumb_evaluate_opcode(uint16_t opcode, uint32_t address,
struct arm_instruction *instruction);
-int thumb2_opcode(target_t *target, uint32_t address,
+int thumb2_opcode(struct target *target, uint32_t address,
struct arm_instruction *instruction);
int arm_access_size(struct arm_instruction *instruction);
* if the dry_run_pc argument is provided, no state is changed,
* but the new pc is stored in the variable pointed at by the argument
*/
-int arm_simulate_step_core(target_t *target,
+int arm_simulate_step_core(struct target *target,
uint32_t *dry_run_pc, struct arm_sim_interface *sim)
{
uint32_t current_pc = sim->get_reg(sim, 15);
-int arm_simulate_step(target_t *target, uint32_t *dry_run_pc)
+int arm_simulate_step(struct target *target, uint32_t *dry_run_pc)
{
struct armv4_5_common_s *armv4_5 = target_to_armv4_5(target);
struct arm_sim_interface sim;
#include "types.h"
-struct target_s;
+struct target;
struct arm_sim_interface
{
};
/* armv4_5 version */
-int arm_simulate_step(struct target_s *target, uint32_t *dry_run_pc);
+int arm_simulate_step(struct target *target, uint32_t *dry_run_pc);
/* a generic arm simulator. Caller must implement the sim interface */
-int arm_simulate_step_core(target_t *target,
+int arm_simulate_step_core(struct target *target,
uint32_t *dry_run_pc, struct arm_sim_interface *sim);
#endif /* ARM_SIMULATOR_H */
{
int retval;
struct armv4_5_core_reg *armv4_5 = reg->arch_info;
- target_t *target = armv4_5->target;
+ struct target *target = armv4_5->target;
if (target->state != TARGET_HALTED)
{
int armv4_5_set_core_reg(struct reg *reg, uint8_t *buf)
{
struct armv4_5_core_reg *armv4_5 = reg->arch_info;
- target_t *target = armv4_5->target;
+ struct target *target = armv4_5->target;
struct armv4_5_common_s *armv4_5_target = target_to_armv4_5(target);
uint32_t value = buf_get_u32(buf, 0, 32);
return ERROR_OK;
}
-int armv4_5_invalidate_core_regs(target_t *target)
+int armv4_5_invalidate_core_regs(struct target *target)
{
struct armv4_5_common_s *armv4_5 = target_to_armv4_5(target);
int i;
return ERROR_OK;
}
-struct reg_cache* armv4_5_build_reg_cache(target_t *target, struct arm *armv4_5_common)
+struct reg_cache* armv4_5_build_reg_cache(struct target *target, struct arm *armv4_5_common)
{
int num_regs = 37;
struct reg_cache *cache = malloc(sizeof(struct reg_cache));
return cache;
}
-int armv4_5_arch_state(struct target_s *target)
+int armv4_5_arch_state(struct target *target)
{
struct armv4_5_common_s *armv4_5 = target_to_armv4_5(target);
char output[128];
int output_len;
int mode, num;
- target_t *target = get_current_target(cmd_ctx);
+ struct target *target = get_current_target(cmd_ctx);
struct armv4_5_common_s *armv4_5 = target_to_armv4_5(target);
if (armv4_5->common_magic != ARMV4_5_COMMON_MAGIC)
COMMAND_HANDLER(handle_armv4_5_core_state_command)
{
- target_t *target = get_current_target(cmd_ctx);
+ struct target *target = get_current_target(cmd_ctx);
struct armv4_5_common_s *armv4_5 = target_to_armv4_5(target);
if (armv4_5->common_magic != ARMV4_5_COMMON_MAGIC)
COMMAND_HANDLER(handle_armv4_5_disassemble_command)
{
int retval = ERROR_OK;
- target_t *target = get_current_target(cmd_ctx);
+ struct target *target = get_current_target(cmd_ctx);
struct armv4_5_common_s *armv4_5 = target_to_armv4_5(target);
uint32_t address;
int count = 1;
return ERROR_OK;
}
-int armv4_5_get_gdb_reg_list(target_t *target, struct reg **reg_list[], int *reg_list_size)
+int armv4_5_get_gdb_reg_list(struct target *target, struct reg **reg_list[], int *reg_list_size)
{
struct armv4_5_common_s *armv4_5 = target_to_armv4_5(target);
int i;
}
/* wait for execution to complete and check exit point */
-static int armv4_5_run_algorithm_completion(struct target_s *target, uint32_t exit_point, int timeout_ms, void *arch_info)
+static int armv4_5_run_algorithm_completion(struct target *target, uint32_t exit_point, int timeout_ms, void *arch_info)
{
int retval;
struct armv4_5_common_s *armv4_5 = target_to_armv4_5(target);
return ERROR_OK;
}
-int armv4_5_run_algorithm_inner(struct target_s *target, int num_mem_params, struct mem_param *mem_params, int num_reg_params, struct reg_param *reg_params, uint32_t entry_point, uint32_t exit_point, int timeout_ms, void *arch_info, int (*run_it)(struct target_s *target, uint32_t exit_point, int timeout_ms, void *arch_info))
+int armv4_5_run_algorithm_inner(struct target *target, int num_mem_params, struct mem_param *mem_params, int num_reg_params, struct reg_param *reg_params, uint32_t entry_point, uint32_t exit_point, int timeout_ms, void *arch_info, int (*run_it)(struct target *target, uint32_t exit_point, int timeout_ms, void *arch_info))
{
struct armv4_5_common_s *armv4_5 = target_to_armv4_5(target);
struct armv4_5_algorithm *armv4_5_algorithm_info = arch_info;
return retval;
}
-int armv4_5_run_algorithm(struct target_s *target, int num_mem_params, struct mem_param *mem_params, int num_reg_params, struct reg_param *reg_params, uint32_t entry_point, uint32_t exit_point, int timeout_ms, void *arch_info)
+int armv4_5_run_algorithm(struct target *target, int num_mem_params, struct mem_param *mem_params, int num_reg_params, struct reg_param *reg_params, uint32_t entry_point, uint32_t exit_point, int timeout_ms, void *arch_info)
{
return armv4_5_run_algorithm_inner(target, num_mem_params, mem_params, num_reg_params, reg_params, entry_point, exit_point, timeout_ms, arch_info, armv4_5_run_algorithm_completion);
}
-int armv4_5_init_arch_info(target_t *target, struct arm *armv4_5)
+int armv4_5_init_arch_info(struct target *target, struct arm *armv4_5)
{
target->arch_info = armv4_5;
/** Handle for the Embedded Trace Module, if one is present. */
struct etm_context *etm;
- int (*full_context)(struct target_s *target);
- int (*read_core_reg)(struct target_s *target,
+ int (*full_context)(struct target *target);
+ int (*read_core_reg)(struct target *target,
int num, enum armv4_5_mode mode);
- int (*write_core_reg)(struct target_s *target,
+ int (*write_core_reg)(struct target *target,
int num, enum armv4_5_mode mode, uint32_t value);
void *arch_info;
};
#define target_to_armv4_5 target_to_arm
/** Convert target handle to generic ARM target state handle. */
-static inline struct arm *target_to_arm(struct target_s *target)
+static inline struct arm *target_to_arm(struct target *target)
{
return target->arch_info;
}
{
int num;
enum armv4_5_mode mode;
- target_t *target;
+ struct target *target;
struct arm *armv4_5_common;
};
-struct reg_cache* armv4_5_build_reg_cache(target_t *target,
+struct reg_cache* armv4_5_build_reg_cache(struct target *target,
struct arm *armv4_5_common);
/* map psr mode bits to linear number */
}
};
-int armv4_5_arch_state(struct target_s *target);
-int armv4_5_get_gdb_reg_list(target_t *target,
+int armv4_5_arch_state(struct target *target);
+int armv4_5_get_gdb_reg_list(struct target *target,
struct reg **reg_list[], int *reg_list_size);
int armv4_5_register_commands(struct command_context_s *cmd_ctx);
-int armv4_5_init_arch_info(target_t *target, struct arm *armv4_5);
+int armv4_5_init_arch_info(struct target *target, struct arm *armv4_5);
-int armv4_5_run_algorithm(struct target_s *target,
+int armv4_5_run_algorithm(struct target *target,
int num_mem_params, struct mem_param *mem_params,
int num_reg_params, struct reg_param *reg_params,
uint32_t entry_point, uint32_t exit_point,
int timeout_ms, void *arch_info);
-int armv4_5_invalidate_core_regs(target_t *target);
+int armv4_5_invalidate_core_regs(struct target *target);
/* ARM mode instructions
*/
#include "armv4_5_mmu.h"
-uint32_t armv4mmu_translate_va(target_t *target, struct armv4_5_mmu_common *armv4_5_mmu, uint32_t va, int *type, uint32_t *cb, int *domain, uint32_t *ap);
+uint32_t armv4mmu_translate_va(struct target *target, struct armv4_5_mmu_common *armv4_5_mmu, uint32_t va, int *type, uint32_t *cb, int *domain, uint32_t *ap);
char* armv4_5_mmu_page_type_names[] =
{
"section", "large page", "small page", "tiny page"
};
-uint32_t armv4_5_mmu_translate_va(target_t *target, struct armv4_5_mmu_common *armv4_5_mmu, uint32_t va, int *type, uint32_t *cb, int *domain, uint32_t *ap)
+uint32_t armv4_5_mmu_translate_va(struct target *target, struct armv4_5_mmu_common *armv4_5_mmu, uint32_t va, int *type, uint32_t *cb, int *domain, uint32_t *ap)
{
uint32_t first_lvl_descriptor = 0x0;
uint32_t second_lvl_descriptor = 0x0;
return ERROR_TARGET_TRANSLATION_FAULT;
}
-int armv4_5_mmu_read_physical(target_t *target, struct armv4_5_mmu_common *armv4_5_mmu, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer)
+int armv4_5_mmu_read_physical(struct target *target, struct armv4_5_mmu_common *armv4_5_mmu, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer)
{
int retval;
return retval;
}
-int armv4_5_mmu_write_physical(target_t *target, struct armv4_5_mmu_common *armv4_5_mmu, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer)
+int armv4_5_mmu_write_physical(struct target *target, struct armv4_5_mmu_common *armv4_5_mmu, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer)
{
int retval;
struct armv4_5_mmu_common
{
- uint32_t (*get_ttb)(target_t *target);
- int (*read_memory)(target_t *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer);
- int (*write_memory)(target_t *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer);
- void (*disable_mmu_caches)(target_t *target, int mmu, int d_u_cache, int i_cache);
- void (*enable_mmu_caches)(target_t *target, int mmu, int d_u_cache, int i_cache);
+ uint32_t (*get_ttb)(struct target *target);
+ int (*read_memory)(struct target *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer);
+ int (*write_memory)(struct target *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer);
+ void (*disable_mmu_caches)(struct target *target, int mmu, int d_u_cache, int i_cache);
+ void (*enable_mmu_caches)(struct target *target, int mmu, int d_u_cache, int i_cache);
struct armv4_5_cache_common armv4_5_cache;
int has_tiny_pages;
int mmu_enabled;
extern char* armv4_5_page_type_names[];
-uint32_t armv4_5_mmu_translate_va(target_t *target,
+uint32_t armv4_5_mmu_translate_va(struct target *target,
struct armv4_5_mmu_common *armv4_5_mmu, uint32_t va, int *type,
uint32_t *cb, int *domain, uint32_t *ap);
-int armv4_5_mmu_read_physical(target_t *target,
+int armv4_5_mmu_read_physical(struct target *target,
struct armv4_5_mmu_common *armv4_5_mmu,
uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer);
-int armv4_5_mmu_write_physical(target_t *target,
+int armv4_5_mmu_write_physical(struct target *target,
struct armv4_5_mmu_common *armv4_5_mmu,
uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer);
0, 1, 96, NULL, 0, NULL, 0
};
-void armv7a_show_fault_registers(target_t *target)
+void armv7a_show_fault_registers(struct target *target)
{
uint32_t dfsr, ifsr, dfar, ifar;
struct armv7a_common *armv7a = target_to_armv7a(target);
}
-int armv7a_arch_state(struct target_s *target)
+int armv7a_arch_state(struct target *target)
{
static const char *state[] =
{
COMMAND_HANDLER(handle_dap_baseaddr_command)
{
- target_t *target = get_current_target(cmd_ctx);
+ struct target *target = get_current_target(cmd_ctx);
struct armv7a_common *armv7a = target_to_armv7a(target);
struct swjdp_common *swjdp = &armv7a->swjdp_info;
COMMAND_HANDLER(handle_dap_memaccess_command)
{
- target_t *target = get_current_target(cmd_ctx);
+ struct target *target = get_current_target(cmd_ctx);
struct armv7a_common *armv7a = target_to_armv7a(target);
struct swjdp_common *swjdp = &armv7a->swjdp_info;
COMMAND_HANDLER(handle_dap_apsel_command)
{
- target_t *target = get_current_target(cmd_ctx);
+ struct target *target = get_current_target(cmd_ctx);
struct armv7a_common *armv7a = target_to_armv7a(target);
struct swjdp_common *swjdp = &armv7a->swjdp_info;
COMMAND_HANDLER(handle_dap_apid_command)
{
- target_t *target = get_current_target(cmd_ctx);
+ struct target *target = get_current_target(cmd_ctx);
struct armv7a_common *armv7a = target_to_armv7a(target);
struct swjdp_common *swjdp = &armv7a->swjdp_info;
COMMAND_HANDLER(handle_dap_info_command)
{
- target_t *target = get_current_target(cmd_ctx);
+ struct target *target = get_current_target(cmd_ctx);
struct armv7a_common *armv7a = target_to_armv7a(target);
struct swjdp_common *swjdp = &armv7a->swjdp_info;
uint32_t apsel;
COMMAND_HANDLER(handle_armv7a_disassemble_command)
{
- target_t *target = get_current_target(cmd_ctx);
+ struct target *target = get_current_target(cmd_ctx);
struct armv4_5_common_s *armv4_5 = target_to_armv4_5(target);
int thumb = 0;
int count = 1;
struct armv4_5_mmu_common armv4_5_mmu;
struct arm armv4_5_common;
-// int (*full_context)(struct target_s *target);
-// int (*read_core_reg)(struct target_s *target, int num, enum armv7a_mode mode);
-// int (*write_core_reg)(struct target_s *target, int num, enum armv7a_mode mode, u32 value);
- int (*read_cp15)(struct target_s *target,
+// int (*full_context)(struct target *target);
+// int (*read_core_reg)(struct target *target, int num, enum armv7a_mode mode);
+// int (*write_core_reg)(struct target *target, int num, enum armv7a_mode mode, u32 value);
+ int (*read_cp15)(struct target *target,
uint32_t op1, uint32_t op2,
uint32_t CRn, uint32_t CRm, uint32_t *value);
- int (*write_cp15)(struct target_s *target,
+ int (*write_cp15)(struct target *target,
uint32_t op1, uint32_t op2,
uint32_t CRn, uint32_t CRm, uint32_t value);
- int (*examine_debug_reason)(target_t *target);
- void (*post_debug_entry)(target_t *target);
+ int (*examine_debug_reason)(struct target *target);
+ void (*post_debug_entry)(struct target *target);
- void (*pre_restore_context)(target_t *target);
- void (*post_restore_context)(target_t *target);
+ void (*pre_restore_context)(struct target *target);
+ void (*post_restore_context)(struct target *target);
};
static inline struct armv7a_common *
-target_to_armv7a(struct target_s *target)
+target_to_armv7a(struct target *target)
{
return container_of(target->arch_info, struct armv7a_common,
armv4_5_common);
{
int num;
enum armv7a_mode mode;
- target_t *target;
+ struct target *target;
struct armv7a_common *armv7a_common;
};
-int armv7a_arch_state(struct target_s *target);
-struct reg_cache *armv7a_build_reg_cache(target_t *target,
+int armv7a_arch_state(struct target *target);
+struct reg_cache *armv7a_build_reg_cache(struct target *target,
struct armv7a_common *armv7a_common);
int armv7a_register_commands(struct command_context_s *cmd_ctx);
-int armv7a_init_arch_info(target_t *target, struct armv7a_common *armv7a);
+int armv7a_init_arch_info(struct target *target, struct armv7a_common *armv7a);
/* map psr mode bits to linear number */
static inline int armv7a_mode_to_number(enum armv7a_mode mode)
* Restores target context using the cache of core registers set up
* by armv7m_build_reg_cache(), calling optional core-specific hooks.
*/
-int armv7m_restore_context(target_t *target)
+int armv7m_restore_context(struct target *target)
{
int i;
struct armv7m_common *armv7m = target_to_armv7m(target);
{
int retval;
struct armv7m_core_reg *armv7m_reg = reg->arch_info;
- target_t *target = armv7m_reg->target;
+ struct target *target = armv7m_reg->target;
struct armv7m_common *armv7m = target_to_armv7m(target);
if (target->state != TARGET_HALTED)
static int armv7m_set_core_reg(struct reg *reg, uint8_t *buf)
{
struct armv7m_core_reg *armv7m_reg = reg->arch_info;
- target_t *target = armv7m_reg->target;
+ struct target *target = armv7m_reg->target;
uint32_t value = buf_get_u32(buf, 0, 32);
if (target->state != TARGET_HALTED)
return ERROR_OK;
}
-static int armv7m_read_core_reg(struct target_s *target, int num)
+static int armv7m_read_core_reg(struct target *target, int num)
{
uint32_t reg_value;
int retval;
return retval;
}
-static int armv7m_write_core_reg(struct target_s *target, int num)
+static int armv7m_write_core_reg(struct target *target, int num)
{
int retval;
uint32_t reg_value;
}
/** Invalidates cache of core registers set up by armv7m_build_reg_cache(). */
-int armv7m_invalidate_core_regs(target_t *target)
+int armv7m_invalidate_core_regs(struct target *target)
{
struct armv7m_common *armv7m = target_to_armv7m(target);
int i;
* hardware, so this also fakes a set of long-obsolete FPA registers that
* are not used in EABI based software stacks.
*/
-int armv7m_get_gdb_reg_list(target_t *target, struct reg **reg_list[], int *reg_list_size)
+int armv7m_get_gdb_reg_list(struct target *target, struct reg **reg_list[], int *reg_list_size)
{
struct armv7m_common *armv7m = target_to_armv7m(target);
int i;
}
/* run to exit point. return error if exit point was not reached. */
-static int armv7m_run_and_wait(struct target_s *target, uint32_t entry_point, int timeout_ms, uint32_t exit_point, struct armv7m_common *armv7m)
+static int armv7m_run_and_wait(struct target *target, uint32_t entry_point, int timeout_ms, uint32_t exit_point, struct armv7m_common *armv7m)
{
uint32_t pc;
int retval;
}
/** Runs a Thumb algorithm in the target. */
-int armv7m_run_algorithm(struct target_s *target,
+int armv7m_run_algorithm(struct target *target,
int num_mem_params, struct mem_param *mem_params,
int num_reg_params, struct reg_param *reg_params,
uint32_t entry_point, uint32_t exit_point,
}
/** Logs summary of ARMv7-M state for a halted target. */
-int armv7m_arch_state(struct target_s *target)
+int armv7m_arch_state(struct target *target)
{
struct armv7m_common *armv7m = target_to_armv7m(target);
uint32_t ctrl, sp;
}
/** Builds cache of architecturally defined registers. */
-struct reg_cache *armv7m_build_reg_cache(target_t *target)
+struct reg_cache *armv7m_build_reg_cache(struct target *target)
{
struct armv7m_common *armv7m = target_to_armv7m(target);
int num_regs = ARMV7M_NUM_REGS;
}
/** Sets up target as a generic ARMv7-M core */
-int armv7m_init_arch_info(target_t *target, struct armv7m_common *armv7m)
+int armv7m_init_arch_info(struct target *target, struct armv7m_common *armv7m)
{
/* register arch-specific functions */
}
/** Generates a CRC32 checksum of a memory region. */
-int armv7m_checksum_memory(struct target_s *target,
+int armv7m_checksum_memory(struct target *target,
uint32_t address, uint32_t count, uint32_t* checksum)
{
struct working_area *crc_algorithm;
}
/** Checks whether a memory region is zeroed. */
-int armv7m_blank_check_memory(struct target_s *target,
+int armv7m_blank_check_memory(struct target *target,
uint32_t address, uint32_t count, uint32_t* blank)
{
struct working_area *erase_check_algorithm;
*/
COMMAND_HANDLER(handle_dap_baseaddr_command)
{
- target_t *target = get_current_target(cmd_ctx);
+ struct target *target = get_current_target(cmd_ctx);
struct armv7m_common *armv7m = target_to_armv7m(target);
struct swjdp_common *swjdp = &armv7m->swjdp_info;
uint32_t apsel, apselsave, baseaddr;
*/
COMMAND_HANDLER(handle_dap_apid_command)
{
- target_t *target = get_current_target(cmd_ctx);
+ struct target *target = get_current_target(cmd_ctx);
struct armv7m_common *armv7m = target_to_armv7m(target);
struct swjdp_common *swjdp = &armv7m->swjdp_info;
COMMAND_HANDLER(handle_dap_apsel_command)
{
- target_t *target = get_current_target(cmd_ctx);
+ struct target *target = get_current_target(cmd_ctx);
struct armv7m_common *armv7m = target_to_armv7m(target);
struct swjdp_common *swjdp = &armv7m->swjdp_info;
COMMAND_HANDLER(handle_dap_memaccess_command)
{
- target_t *target = get_current_target(cmd_ctx);
+ struct target *target = get_current_target(cmd_ctx);
struct armv7m_common *armv7m = target_to_armv7m(target);
struct swjdp_common *swjdp = &armv7m->swjdp_info;
COMMAND_HANDLER(handle_dap_info_command)
{
- target_t *target = get_current_target(cmd_ctx);
+ struct target *target = get_current_target(cmd_ctx);
struct armv7m_common *armv7m = target_to_armv7m(target);
struct swjdp_common *swjdp = &armv7m->swjdp_info;
uint32_t apsel;
struct swjdp_common swjdp_info;
/* Direct processor core register read and writes */
- int (*load_core_reg_u32)(struct target_s *target, enum armv7m_regtype type, uint32_t num, uint32_t *value);
- int (*store_core_reg_u32)(struct target_s *target, enum armv7m_regtype type, uint32_t num, uint32_t value);
+ int (*load_core_reg_u32)(struct target *target, enum armv7m_regtype type, uint32_t num, uint32_t *value);
+ int (*store_core_reg_u32)(struct target *target, enum armv7m_regtype type, uint32_t num, uint32_t value);
/* register cache to processor synchronization */
- int (*read_core_reg)(struct target_s *target, int num);
- int (*write_core_reg)(struct target_s *target, int num);
+ int (*read_core_reg)(struct target *target, int num);
+ int (*write_core_reg)(struct target *target, int num);
- int (*examine_debug_reason)(target_t *target);
- void (*post_debug_entry)(target_t *target);
+ int (*examine_debug_reason)(struct target *target);
+ void (*post_debug_entry)(struct target *target);
- void (*pre_restore_context)(target_t *target);
- void (*post_restore_context)(target_t *target);
+ void (*pre_restore_context)(struct target *target);
+ void (*post_restore_context)(struct target *target);
};
static inline struct armv7m_common *
-target_to_armv7m(struct target_s *target)
+target_to_armv7m(struct target *target)
{
return target->arch_info;
}
{
uint32_t num;
enum armv7m_regtype type;
- target_t *target;
+ struct target *target;
struct armv7m_common *armv7m_common;
};
-struct reg_cache *armv7m_build_reg_cache(target_t *target);
+struct reg_cache *armv7m_build_reg_cache(struct target *target);
enum armv7m_mode armv7m_number_to_mode(int number);
int armv7m_mode_to_number(enum armv7m_mode mode);
-int armv7m_arch_state(struct target_s *target);
-int armv7m_get_gdb_reg_list(target_t *target,
+int armv7m_arch_state(struct target *target);
+int armv7m_get_gdb_reg_list(struct target *target,
struct reg **reg_list[], int *reg_list_size);
int armv7m_register_commands(struct command_context_s *cmd_ctx);
-int armv7m_init_arch_info(target_t *target, struct armv7m_common *armv7m);
+int armv7m_init_arch_info(struct target *target, struct armv7m_common *armv7m);
-int armv7m_run_algorithm(struct target_s *target,
+int armv7m_run_algorithm(struct target *target,
int num_mem_params, struct mem_param *mem_params,
int num_reg_params, struct reg_param *reg_params,
uint32_t entry_point, uint32_t exit_point,
int timeout_ms, void *arch_info);
-int armv7m_invalidate_core_regs(target_t *target);
+int armv7m_invalidate_core_regs(struct target *target);
-int armv7m_restore_context(target_t *target);
+int armv7m_restore_context(struct target *target);
-int armv7m_checksum_memory(struct target_s *target,
+int armv7m_checksum_memory(struct target *target,
uint32_t address, uint32_t count, uint32_t* checksum);
-int armv7m_blank_check_memory(struct target_s *target,
+int armv7m_blank_check_memory(struct target *target,
uint32_t address, uint32_t count, uint32_t* blank);
/* Thumb mode instructions
int avr_register_commands(struct command_context_s *cmd_ctx);
/* forward declarations */
-int avr_target_create(struct target_s *target, Jim_Interp *interp);
-int avr_init_target(struct command_context_s *cmd_ctx, struct target_s *target);
+int avr_target_create(struct target *target, Jim_Interp *interp);
+int avr_init_target(struct command_context_s *cmd_ctx, struct target *target);
-int avr_arch_state(struct target_s *target);
-int avr_poll(target_t *target);
-int avr_halt(target_t *target);
-int avr_resume(struct target_s *target, int current, uint32_t address, int handle_breakpoints, int debug_execution);
-int avr_step(struct target_s *target, int current, uint32_t address, int handle_breakpoints);
+int avr_arch_state(struct target *target);
+int avr_poll(struct target *target);
+int avr_halt(struct target *target);
+int avr_resume(struct target *target, int current, uint32_t address, int handle_breakpoints, int debug_execution);
+int avr_step(struct target *target, int current, uint32_t address, int handle_breakpoints);
-int avr_assert_reset(target_t *target);
-int avr_deassert_reset(target_t *target);
-int avr_soft_reset_halt(struct target_s *target);
+int avr_assert_reset(struct target *target);
+int avr_deassert_reset(struct target *target);
+int avr_soft_reset_halt(struct target *target);
/* IR and DR functions */
int avr_jtag_sendinstr(struct jtag_tap *tap, uint8_t *ir_in, uint8_t ir_out);
return ERROR_OK;
}
-int avr_target_create(struct target_s *target, Jim_Interp *interp)
+int avr_target_create(struct target *target, Jim_Interp *interp)
{
struct avr_common *avr = calloc(1, sizeof(struct avr_common));
return ERROR_OK;
}
-int avr_init_target(struct command_context_s *cmd_ctx, struct target_s *target)
+int avr_init_target(struct command_context_s *cmd_ctx, struct target *target)
{
LOG_DEBUG("%s", __FUNCTION__);
return ERROR_OK;
}
-int avr_arch_state(struct target_s *target)
+int avr_arch_state(struct target *target)
{
LOG_DEBUG("%s", __FUNCTION__);
return ERROR_OK;
}
-int avr_poll(target_t *target)
+int avr_poll(struct target *target)
{
if ((target->state == TARGET_RUNNING) || (target->state == TARGET_DEBUG_RUNNING))
{
return ERROR_OK;
}
-int avr_halt(target_t *target)
+int avr_halt(struct target *target)
{
LOG_DEBUG("%s", __FUNCTION__);
return ERROR_OK;
}
-int avr_resume(struct target_s *target, int current, uint32_t address, int handle_breakpoints, int debug_execution)
+int avr_resume(struct target *target, int current, uint32_t address, int handle_breakpoints, int debug_execution)
{
LOG_DEBUG("%s", __FUNCTION__);
return ERROR_OK;
}
-int avr_step(struct target_s *target, int current, uint32_t address, int handle_breakpoints)
+int avr_step(struct target *target, int current, uint32_t address, int handle_breakpoints)
{
LOG_DEBUG("%s", __FUNCTION__);
return ERROR_OK;
}
-int avr_assert_reset(target_t *target)
+int avr_assert_reset(struct target *target)
{
target->state = TARGET_RESET;
return ERROR_OK;
}
-int avr_deassert_reset(target_t *target)
+int avr_deassert_reset(struct target *target)
{
target->state = TARGET_RUNNING;
return ERROR_OK;
}
-int avr_soft_reset_halt(struct target_s *target)
+int avr_soft_reset_halt(struct target *target)
{
LOG_DEBUG("%s", __FUNCTION__);
return ERROR_OK;
// monotonic counter/id-number for breakpoints and watch points
static int bpwp_unique_id;
-int breakpoint_add(target_t *target, uint32_t address, uint32_t length, enum breakpoint_type type)
+int breakpoint_add(struct target *target, uint32_t address, uint32_t length, enum breakpoint_type type)
{
struct breakpoint *breakpoint = target->breakpoints;
struct breakpoint **breakpoint_p = &target->breakpoints;
}
/* free up a breakpoint */
-static void breakpoint_free(target_t *target, struct breakpoint *breakpoint_remove)
+static void breakpoint_free(struct target *target, struct breakpoint *breakpoint_remove)
{
struct breakpoint *breakpoint = target->breakpoints;
struct breakpoint **breakpoint_p = &target->breakpoints;
free(breakpoint);
}
-void breakpoint_remove(target_t *target, uint32_t address)
+void breakpoint_remove(struct target *target, uint32_t address)
{
struct breakpoint *breakpoint = target->breakpoints;
struct breakpoint **breakpoint_p = &target->breakpoints;
}
}
-void breakpoint_clear_target(target_t *target)
+void breakpoint_clear_target(struct target *target)
{
struct breakpoint *breakpoint;
LOG_DEBUG("Delete all breakpoints for target: %s", target_get_name( target ));
}
}
-struct breakpoint* breakpoint_find(target_t *target, uint32_t address)
+struct breakpoint* breakpoint_find(struct target *target, uint32_t address)
{
struct breakpoint *breakpoint = target->breakpoints;
return NULL;
}
-int watchpoint_add(target_t *target, uint32_t address, uint32_t length,
+int watchpoint_add(struct target *target, uint32_t address, uint32_t length,
enum watchpoint_rw rw, uint32_t value, uint32_t mask)
{
struct watchpoint *watchpoint = target->watchpoints;
return ERROR_OK;
}
-static void watchpoint_free(target_t *target, struct watchpoint *watchpoint_remove)
+static void watchpoint_free(struct target *target, struct watchpoint *watchpoint_remove)
{
struct watchpoint *watchpoint = target->watchpoints;
struct watchpoint **watchpoint_p = &target->watchpoints;
free(watchpoint);
}
-void watchpoint_remove(target_t *target, uint32_t address)
+void watchpoint_remove(struct target *target, uint32_t address)
{
struct watchpoint *watchpoint = target->watchpoints;
struct watchpoint **watchpoint_p = &target->watchpoints;
}
}
-void watchpoint_clear_target(target_t *target)
+void watchpoint_clear_target(struct target *target)
{
struct watchpoint *watchpoint;
LOG_DEBUG("Delete all watchpoints for target: %s", target_get_name( target ));
#include "types.h"
-struct target_s;
+struct target;
enum breakpoint_type
{
int unique_id;
};
-void breakpoint_clear_target(struct target_s *target);
-int breakpoint_add(struct target_s *target,
+void breakpoint_clear_target(struct target *target);
+int breakpoint_add(struct target *target,
uint32_t address, uint32_t length, enum breakpoint_type type);
-void breakpoint_remove(struct target_s *target, uint32_t address);
+void breakpoint_remove(struct target *target, uint32_t address);
-struct breakpoint* breakpoint_find(struct target_s *target, uint32_t address);
+struct breakpoint* breakpoint_find(struct target *target, uint32_t address);
-void watchpoint_clear_target(struct target_s *target);
-int watchpoint_add(struct target_s *target,
+void watchpoint_clear_target(struct target *target);
+int watchpoint_add(struct target *target,
uint32_t address, uint32_t length,
enum watchpoint_rw rw, uint32_t value, uint32_t mask);
-void watchpoint_remove(struct target_s *target, uint32_t address);
+void watchpoint_remove(struct target *target, uint32_t address);
#endif /* BREAKPOINTS_H */
#include "target_request.h"
#include "target_type.h"
-static int cortex_a8_poll(target_t *target);
-static int cortex_a8_debug_entry(target_t *target);
-static int cortex_a8_restore_context(target_t *target);
-static int cortex_a8_set_breakpoint(struct target_s *target,
+static int cortex_a8_poll(struct target *target);
+static int cortex_a8_debug_entry(struct target *target);
+static int cortex_a8_restore_context(struct target *target);
+static int cortex_a8_set_breakpoint(struct target *target,
struct breakpoint *breakpoint, uint8_t matchmode);
-static int cortex_a8_unset_breakpoint(struct target_s *target,
+static int cortex_a8_unset_breakpoint(struct target *target,
struct breakpoint *breakpoint);
-static int cortex_a8_dap_read_coreregister_u32(target_t *target,
+static int cortex_a8_dap_read_coreregister_u32(struct target *target,
uint32_t *value, int regnum);
-static int cortex_a8_dap_write_coreregister_u32(target_t *target,
+static int cortex_a8_dap_write_coreregister_u32(struct target *target,
uint32_t value, int regnum);
/*
* FIXME do topology discovery using the ROM; don't
/*
* Cortex-A8 Basic debug access, very low level assumes state is saved
*/
-static int cortex_a8_init_debug_access(target_t *target)
+static int cortex_a8_init_debug_access(struct target *target)
{
struct armv7a_common *armv7a = target_to_armv7a(target);
struct swjdp_common *swjdp = &armv7a->swjdp_info;
return retval;
}
-int cortex_a8_exec_opcode(target_t *target, uint32_t opcode)
+int cortex_a8_exec_opcode(struct target *target, uint32_t opcode)
{
uint32_t dscr;
int retval;
Read core register with very few exec_opcode, fast but needs work_area.
This can cause problems with MMU active.
**************************************************************************/
-static int cortex_a8_read_regs_through_mem(target_t *target, uint32_t address,
+static int cortex_a8_read_regs_through_mem(struct target *target, uint32_t address,
uint32_t * regfile)
{
int retval = ERROR_OK;
return retval;
}
-static int cortex_a8_read_cp(target_t *target, uint32_t *value, uint8_t CP,
+static int cortex_a8_read_cp(struct target *target, uint32_t *value, uint8_t CP,
uint8_t op1, uint8_t CRn, uint8_t CRm, uint8_t op2)
{
int retval;
return retval;
}
-static int cortex_a8_write_cp(target_t *target, uint32_t value,
+static int cortex_a8_write_cp(struct target *target, uint32_t value,
uint8_t CP, uint8_t op1, uint8_t CRn, uint8_t CRm, uint8_t op2)
{
int retval;
return retval;
}
-static int cortex_a8_read_cp15(target_t *target, uint32_t op1, uint32_t op2,
+static int cortex_a8_read_cp15(struct target *target, uint32_t op1, uint32_t op2,
uint32_t CRn, uint32_t CRm, uint32_t *value)
{
return cortex_a8_read_cp(target, value, 15, op1, CRn, CRm, op2);
}
-static int cortex_a8_write_cp15(target_t *target, uint32_t op1, uint32_t op2,
+static int cortex_a8_write_cp15(struct target *target, uint32_t op1, uint32_t op2,
uint32_t CRn, uint32_t CRm, uint32_t value)
{
return cortex_a8_write_cp(target, value, 15, op1, CRn, CRm, op2);
}
-static int cortex_a8_mrc(target_t *target, int cpnum, uint32_t op1, uint32_t op2, uint32_t CRn, uint32_t CRm, uint32_t *value)
+static int cortex_a8_mrc(struct target *target, int cpnum, uint32_t op1, uint32_t op2, uint32_t CRn, uint32_t CRm, uint32_t *value)
{
if (cpnum!=15)
{
return cortex_a8_read_cp15(target, op1, op2, CRn, CRm, value);
}
-static int cortex_a8_mcr(target_t *target, int cpnum, uint32_t op1, uint32_t op2, uint32_t CRn, uint32_t CRm, uint32_t value)
+static int cortex_a8_mcr(struct target *target, int cpnum, uint32_t op1, uint32_t op2, uint32_t CRn, uint32_t CRm, uint32_t value)
{
if (cpnum!=15)
{
-static int cortex_a8_dap_read_coreregister_u32(target_t *target,
+static int cortex_a8_dap_read_coreregister_u32(struct target *target,
uint32_t *value, int regnum)
{
int retval = ERROR_OK;
return retval;
}
-static int cortex_a8_dap_write_coreregister_u32(target_t *target, uint32_t value, int regnum)
+static int cortex_a8_dap_write_coreregister_u32(struct target *target, uint32_t value, int regnum)
{
int retval = ERROR_OK;
uint8_t Rd = regnum&0xFF;
}
/* Write to memory mapped registers directly with no cache or mmu handling */
-static int cortex_a8_dap_write_memap_register_u32(target_t *target, uint32_t address, uint32_t value)
+static int cortex_a8_dap_write_memap_register_u32(struct target *target, uint32_t address, uint32_t value)
{
int retval;
struct armv7a_common *armv7a = target_to_armv7a(target);
* Cortex-A8 Run control
*/
-static int cortex_a8_poll(target_t *target)
+static int cortex_a8_poll(struct target *target)
{
int retval = ERROR_OK;
uint32_t dscr;
return retval;
}
-static int cortex_a8_halt(target_t *target)
+static int cortex_a8_halt(struct target *target)
{
int retval = ERROR_OK;
uint32_t dscr;
return retval;
}
-static int cortex_a8_resume(struct target_s *target, int current,
+static int cortex_a8_resume(struct target *target, int current,
uint32_t address, int handle_breakpoints, int debug_execution)
{
struct armv7a_common *armv7a = target_to_armv7a(target);
return ERROR_OK;
}
-static int cortex_a8_debug_entry(target_t *target)
+static int cortex_a8_debug_entry(struct target *target)
{
int i;
uint32_t regfile[16], pc, cpsr, dscr;
}
-static void cortex_a8_post_debug_entry(target_t *target)
+static void cortex_a8_post_debug_entry(struct target *target)
{
struct cortex_a8_common *cortex_a8 = target_to_cortex_a8(target);
struct armv7a_common *armv7a = &cortex_a8->armv7a_common;
}
-static int cortex_a8_step(struct target_s *target, int current, uint32_t address,
+static int cortex_a8_step(struct target *target, int current, uint32_t address,
int handle_breakpoints)
{
struct armv7a_common *armv7a = target_to_armv7a(target);
return ERROR_OK;
}
-static int cortex_a8_restore_context(target_t *target)
+static int cortex_a8_restore_context(struct target *target)
{
int i;
uint32_t value;
/*
* Cortex-A8 Core register functions
*/
-static int cortex_a8_load_core_reg_u32(struct target_s *target, int num,
+static int cortex_a8_load_core_reg_u32(struct target *target, int num,
armv4_5_mode_t mode, uint32_t * value)
{
int retval;
return ERROR_OK;
}
-static int cortex_a8_store_core_reg_u32(struct target_s *target, int num,
+static int cortex_a8_store_core_reg_u32(struct target *target, int num,
armv4_5_mode_t mode, uint32_t value)
{
int retval;
#endif
-static int cortex_a8_read_core_reg(struct target_s *target, int num,
+static int cortex_a8_read_core_reg(struct target *target, int num,
enum armv4_5_mode mode)
{
uint32_t value;
return ERROR_OK;
}
-int cortex_a8_write_core_reg(struct target_s *target, int num,
+int cortex_a8_write_core_reg(struct target *target, int num,
enum armv4_5_mode mode, uint32_t value)
{
int retval;
*/
/* Setup hardware Breakpoint Register Pair */
-static int cortex_a8_set_breakpoint(struct target_s *target,
+static int cortex_a8_set_breakpoint(struct target *target,
struct breakpoint *breakpoint, uint8_t matchmode)
{
int retval;
return ERROR_OK;
}
-static int cortex_a8_unset_breakpoint(struct target_s *target, struct breakpoint *breakpoint)
+static int cortex_a8_unset_breakpoint(struct target *target, struct breakpoint *breakpoint)
{
int retval;
struct cortex_a8_common *cortex_a8 = target_to_cortex_a8(target);
return ERROR_OK;
}
-int cortex_a8_add_breakpoint(struct target_s *target, struct breakpoint *breakpoint)
+int cortex_a8_add_breakpoint(struct target *target, struct breakpoint *breakpoint)
{
struct cortex_a8_common *cortex_a8 = target_to_cortex_a8(target);
return ERROR_OK;
}
-static int cortex_a8_remove_breakpoint(struct target_s *target, struct breakpoint *breakpoint)
+static int cortex_a8_remove_breakpoint(struct target *target, struct breakpoint *breakpoint)
{
struct cortex_a8_common *cortex_a8 = target_to_cortex_a8(target);
* Cortex-A8 Reset fuctions
*/
-static int cortex_a8_assert_reset(target_t *target)
+static int cortex_a8_assert_reset(struct target *target)
{
LOG_DEBUG(" ");
return ERROR_OK;
}
-static int cortex_a8_deassert_reset(target_t *target)
+static int cortex_a8_deassert_reset(struct target *target)
{
LOG_DEBUG(" ");
* ap number for every access.
*/
-static int cortex_a8_read_memory(struct target_s *target, uint32_t address,
+static int cortex_a8_read_memory(struct target *target, uint32_t address,
uint32_t size, uint32_t count, uint8_t *buffer)
{
struct armv7a_common *armv7a = target_to_armv7a(target);
return retval;
}
-int cortex_a8_write_memory(struct target_s *target, uint32_t address,
+int cortex_a8_write_memory(struct target *target, uint32_t address,
uint32_t size, uint32_t count, uint8_t *buffer)
{
struct armv7a_common *armv7a = target_to_armv7a(target);
return retval;
}
-static int cortex_a8_bulk_write_memory(target_t *target, uint32_t address,
+static int cortex_a8_bulk_write_memory(struct target *target, uint32_t address,
uint32_t count, uint8_t *buffer)
{
return cortex_a8_write_memory(target, address, 4, count, buffer);
static int cortex_a8_handle_target_request(void *priv)
{
- target_t *target = priv;
+ struct target *target = priv;
if (!target->type->examined)
return ERROR_OK;
struct armv7a_common *armv7a = target_to_armv7a(target);
* Cortex-A8 target information and configuration
*/
-static int cortex_a8_examine(struct target_s *target)
+static int cortex_a8_examine(struct target *target)
{
struct cortex_a8_common *cortex_a8 = target_to_cortex_a8(target);
struct armv7a_common *armv7a = &cortex_a8->armv7a_common;
* Cortex-A8 target creation and initialization
*/
-static void cortex_a8_build_reg_cache(target_t *target)
+static void cortex_a8_build_reg_cache(struct target *target)
{
struct reg_cache **cache_p = register_get_last_cache_p(&target->reg_cache);
struct armv4_5_common_s *armv4_5 = target_to_armv4_5(target);
static int cortex_a8_init_target(struct command_context_s *cmd_ctx,
- struct target_s *target)
+ struct target *target)
{
cortex_a8_build_reg_cache(target);
return ERROR_OK;
}
-int cortex_a8_init_arch_info(target_t *target,
+int cortex_a8_init_arch_info(struct target *target,
struct cortex_a8_common *cortex_a8, struct jtag_tap *tap)
{
struct arm *armv4_5;
return ERROR_OK;
}
-static int cortex_a8_target_create(struct target_s *target, Jim_Interp *interp)
+static int cortex_a8_target_create(struct target *target, Jim_Interp *interp)
{
struct cortex_a8_common *cortex_a8 = calloc(1, sizeof(struct cortex_a8_common));
COMMAND_HANDLER(cortex_a8_handle_cache_info_command)
{
- target_t *target = get_current_target(cmd_ctx);
+ struct target *target = get_current_target(cmd_ctx);
struct armv7a_common *armv7a = target_to_armv7a(target);
return armv4_5_handle_cache_info_command(cmd_ctx,
COMMAND_HANDLER(cortex_a8_handle_dbginit_command)
{
- target_t *target = get_current_target(cmd_ctx);
+ struct target *target = get_current_target(cmd_ctx);
cortex_a8_init_debug_access(target);
};
static inline struct cortex_a8_common *
-target_to_cortex_a8(struct target_s *target)
+target_to_cortex_a8(struct target *target)
{
return container_of(target->arch_info, struct cortex_a8_common,
armv7a_common.armv4_5_common);
}
-int cortex_a8_init_arch_info(target_t *target,
+int cortex_a8_init_arch_info(struct target *target,
struct cortex_a8_common *cortex_a8, struct jtag_tap *tap);
#endif /* CORTEX_A8_H */
/* forward declarations */
-static int cortex_m3_set_breakpoint(struct target_s *target, struct breakpoint *breakpoint);
-static int cortex_m3_unset_breakpoint(struct target_s *target, struct breakpoint *breakpoint);
-static void cortex_m3_enable_watchpoints(struct target_s *target);
-static int cortex_m3_store_core_reg_u32(target_t *target,
+static int cortex_m3_set_breakpoint(struct target *target, struct breakpoint *breakpoint);
+static int cortex_m3_unset_breakpoint(struct target *target, struct breakpoint *breakpoint);
+static void cortex_m3_enable_watchpoints(struct target *target);
+static int cortex_m3_store_core_reg_u32(struct target *target,
enum armv7m_regtype type, uint32_t num, uint32_t value);
#ifdef ARMV7_GDB_HACKS
return retval;
}
-static int cortex_m3_write_debug_halt_mask(target_t *target,
+static int cortex_m3_write_debug_halt_mask(struct target *target,
uint32_t mask_on, uint32_t mask_off)
{
struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
return mem_ap_write_atomic_u32(swjdp, DCB_DHCSR, cortex_m3->dcb_dhcsr);
}
-static int cortex_m3_clear_halt(target_t *target)
+static int cortex_m3_clear_halt(struct target *target)
{
struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
struct swjdp_common *swjdp = &cortex_m3->armv7m.swjdp_info;
return ERROR_OK;
}
-static int cortex_m3_single_step_core(target_t *target)
+static int cortex_m3_single_step_core(struct target *target)
{
struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
struct swjdp_common *swjdp = &cortex_m3->armv7m.swjdp_info;
return ERROR_OK;
}
-static int cortex_m3_endreset_event(target_t *target)
+static int cortex_m3_endreset_event(struct target *target)
{
int i;
uint32_t dcb_demcr;
return ERROR_OK;
}
-static int cortex_m3_examine_debug_reason(target_t *target)
+static int cortex_m3_examine_debug_reason(struct target *target)
{
struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
return ERROR_OK;
}
-static int cortex_m3_examine_exception_reason(target_t *target)
+static int cortex_m3_examine_exception_reason(struct target *target)
{
uint32_t shcsr, except_sr, cfsr = -1, except_ar = -1;
struct armv7m_common *armv7m = target_to_armv7m(target);
return ERROR_OK;
}
-static int cortex_m3_debug_entry(target_t *target)
+static int cortex_m3_debug_entry(struct target *target)
{
int i;
uint32_t xPSR;
return ERROR_OK;
}
-static int cortex_m3_poll(target_t *target)
+static int cortex_m3_poll(struct target *target)
{
int retval;
enum target_state prev_target_state = target->state;
return ERROR_OK;
}
-static int cortex_m3_halt(target_t *target)
+static int cortex_m3_halt(struct target *target)
{
LOG_DEBUG("target->state: %s",
target_state_name(target));
return ERROR_OK;
}
-static int cortex_m3_soft_reset_halt(struct target_s *target)
+static int cortex_m3_soft_reset_halt(struct target *target)
{
struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
struct swjdp_common *swjdp = &cortex_m3->armv7m.swjdp_info;
return ERROR_OK;
}
-static void cortex_m3_enable_breakpoints(struct target_s *target)
+static void cortex_m3_enable_breakpoints(struct target *target)
{
struct breakpoint *breakpoint = target->breakpoints;
}
}
-static int cortex_m3_resume(struct target_s *target, int current,
+static int cortex_m3_resume(struct target *target, int current,
uint32_t address, int handle_breakpoints, int debug_execution)
{
struct armv7m_common *armv7m = target_to_armv7m(target);
}
/* int irqstepcount = 0; */
-static int cortex_m3_step(struct target_s *target, int current,
+static int cortex_m3_step(struct target *target, int current,
uint32_t address, int handle_breakpoints)
{
struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
return ERROR_OK;
}
-static int cortex_m3_assert_reset(target_t *target)
+static int cortex_m3_assert_reset(struct target *target)
{
struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
struct swjdp_common *swjdp = &cortex_m3->armv7m.swjdp_info;
return ERROR_OK;
}
-static int cortex_m3_deassert_reset(target_t *target)
+static int cortex_m3_deassert_reset(struct target *target)
{
LOG_DEBUG("target->state: %s",
target_state_name(target));
}
static int
-cortex_m3_set_breakpoint(struct target_s *target, struct breakpoint *breakpoint)
+cortex_m3_set_breakpoint(struct target *target, struct breakpoint *breakpoint)
{
int retval;
int fp_num = 0;
}
static int
-cortex_m3_unset_breakpoint(struct target_s *target, struct breakpoint *breakpoint)
+cortex_m3_unset_breakpoint(struct target *target, struct breakpoint *breakpoint)
{
int retval;
struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
}
static int
-cortex_m3_add_breakpoint(struct target_s *target, struct breakpoint *breakpoint)
+cortex_m3_add_breakpoint(struct target *target, struct breakpoint *breakpoint)
{
struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
}
static int
-cortex_m3_remove_breakpoint(struct target_s *target, struct breakpoint *breakpoint)
+cortex_m3_remove_breakpoint(struct target *target, struct breakpoint *breakpoint)
{
struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
}
static int
-cortex_m3_set_watchpoint(struct target_s *target, struct watchpoint *watchpoint)
+cortex_m3_set_watchpoint(struct target *target, struct watchpoint *watchpoint)
{
int dwt_num = 0;
uint32_t mask, temp;
}
static int
-cortex_m3_unset_watchpoint(struct target_s *target, struct watchpoint *watchpoint)
+cortex_m3_unset_watchpoint(struct target *target, struct watchpoint *watchpoint)
{
struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
str
Code Review / openocd.git / commitdiff