* Code limitations:
* The workarea must have size multiple of 4 bytes, since R/W
* operations are all at 32 bits.
- * The workarea must be big enough to contain 32 bytes of data,
- * thus the minimum size is (rp, wp, data) = 4 + 4 + 32 = 40 bytes.
+ * The workarea must be big enough to contain rp, wp and data, thus the minumum
+ * workarea size is: min_wa_size = sizeof(rp, wp, data) = 4 + 4 + sizeof(data).
+ * - for 0x450 devices: sizeof(data) = 32 bytes, thus min_wa_size = 40 bytes.
+ * - for 0x480 devices: sizeof(data) = 16 bytes, thus min_wa_size = 24 bytes.
* To benefit from concurrent host write-to-buffer and target
* write-to-flash, the workarea must be way bigger than the minimum.
- */
+ *
+ * To avoid confusions the write word size is got from .block_size member of
+ * struct stm32h7x_part_info defined in stm32h7x.c
+*/
/*
* Params :
* r0 = workarea start, status (out)
* r1 = workarea end
* r2 = target address
- * r3 = count (256 bit words)
- * r4 = flash reg base
+ * r3 = count (of write words)
+ * r4 = size of write word
+ * r5 = flash reg base
*
* Clobbered:
- * r5 - rp
- * r6 - wp, status, tmp
- * r7 - loop index, tmp
+ * r6 - rp
+ * r7 - wp, status, tmp
+ * r8 - loop index, tmp
*/
#define STM32_FLASH_CR_OFFSET 0x0C /* offset of CR register in FLASH struct */
#define STM32_FLASH_SR_OFFSET 0x10 /* offset of SR register in FLASH struct */
-#define STM32_CR_PROG 0x00000032 /* PSIZE64 | PG */
+#define STM32_CR_PROG 0x00000002 /* PG */
#define STM32_SR_QW_MASK 0x00000004 /* QW */
#define STM32_SR_ERROR_MASK 0x07ee0000 /* DBECCERR | SNECCERR | RDSERR | RDPERR | OPERR
| INCERR | STRBERR | PGSERR | WRPERR */
.thumb_func
.global _start
_start:
- ldr r5, [r0, #4] /* read rp */
+ ldr r6, [r0, #4] /* read rp */
wait_fifo:
- ldr r6, [r0, #0] /* read wp */
- cbz r6, exit /* abort if wp == 0, status = 0 */
- subs r6, r6, r5 /* number of bytes available for read in r6 */
+ ldr r7, [r0, #0] /* read wp */
+ cbz r7, exit /* abort if wp == 0, status = 0 */
+ subs r7, r7, r6 /* number of bytes available for read in r7 */
ittt mi /* if wrapped around */
- addmi r6, r1 /* add size of buffer */
- submi r6, r0
- submi r6, #8
- cmp r6, #32 /* wait until 32 bytes are available */
+ addmi r7, r1 /* add size of buffer */
+ submi r7, r0
+ submi r7, #8
+ cmp r7, r4 /* wait until data buffer is full */
bcc wait_fifo
- mov r6, #STM32_CR_PROG
- str r6, [r4, #STM32_FLASH_CR_OFFSET]
+ mov r7, #STM32_CR_PROG
+ str r7, [r5, #STM32_FLASH_CR_OFFSET]
- mov r7, #8 /* program by 8 words = 32 bytes */
+ mov r8, #4
+ udiv r8, r4, r8 /* number of words is size of write word devided by 4*/
write_flash:
dsb
- ldr r6, [r5], #0x04 /* read one word from src, increment ptr */
- str r6, [r2], #0x04 /* write one word to dst, increment ptr */
+ ldr r7, [r6], #0x04 /* read one word from src, increment ptr */
+ str r7, [r2], #0x04 /* write one word to dst, increment ptr */
dsb
- cmp r5, r1 /* if rp >= end of buffer ... */
+ cmp r6, r1 /* if rp >= end of buffer ... */
it cs
- addcs r5, r0, #8 /* ... then wrap at buffer start */
- subs r7, r7, #1 /* decrement loop index */
+ addcs r6, r0, #8 /* ... then wrap at buffer start */
+ subs r8, r8, #1 /* decrement loop index */
bne write_flash /* loop if not done */
busy:
- ldr r6, [r4, #STM32_FLASH_SR_OFFSET]
- tst r6, #STM32_SR_QW_MASK
+ ldr r7, [r5, #STM32_FLASH_SR_OFFSET]
+ tst r7, #STM32_SR_QW_MASK
bne busy /* operation in progress, wait ... */
- ldr r7, =STM32_SR_ERROR_MASK
- tst r6, r7
+ ldr r8, =STM32_SR_ERROR_MASK
+ tst r7, r8
bne error /* fail... */
- str r5, [r0, #4] /* store rp */
+ str r6, [r0, #4] /* store rp */
subs r3, r3, #1 /* decrement count */
bne wait_fifo /* loop if not done */
b exit
error:
- movs r7, #0
- str r7, [r0, #4] /* set rp = 0 on error */
+ movs r8, #0
+ str r8, [r0, #4] /* set rp = 0 on error */
exit:
- mov r0, r6 /* return status in r0 */
+ mov r0, r7 /* return status in r0 */
bkpt #0x00
.pool
/* Autogenerated with ../../../../src/helper/bin2char.sh */
-0x45,0x68,0x06,0x68,0x36,0xb3,0x76,0x1b,0x42,0xbf,0x76,0x18,0x36,0x1a,0x08,0x3e,
-0x20,0x2e,0xf6,0xd3,0x4f,0xf0,0x32,0x06,0xe6,0x60,0x4f,0xf0,0x08,0x07,0xbf,0xf3,
-0x4f,0x8f,0x55,0xf8,0x04,0x6b,0x42,0xf8,0x04,0x6b,0xbf,0xf3,0x4f,0x8f,0x8d,0x42,
-0x28,0xbf,0x00,0xf1,0x08,0x05,0x01,0x3f,0xf1,0xd1,0x26,0x69,0x16,0xf0,0x04,0x0f,
-0xfb,0xd1,0x05,0x4f,0x3e,0x42,0x03,0xd1,0x45,0x60,0x01,0x3b,0xd9,0xd1,0x01,0xe0,
-0x00,0x27,0x47,0x60,0x30,0x46,0x00,0xbe,0x00,0x00,0xee,0x07,
+0x46,0x68,0x07,0x68,0x6f,0xb3,0xbf,0x1b,0x42,0xbf,0x7f,0x18,0x3f,0x1a,0x08,0x3f,
+0xa7,0x42,0xf6,0xd3,0x4f,0xf0,0x02,0x07,0xef,0x60,0x4f,0xf0,0x04,0x08,0xb4,0xfb,
+0xf8,0xf8,0xbf,0xf3,0x4f,0x8f,0x56,0xf8,0x04,0x7b,0x42,0xf8,0x04,0x7b,0xbf,0xf3,
+0x4f,0x8f,0x8e,0x42,0x28,0xbf,0x00,0xf1,0x08,0x06,0xb8,0xf1,0x01,0x08,0xf0,0xd1,
+0x2f,0x69,0x17,0xf0,0x04,0x0f,0xfb,0xd1,0xdf,0xf8,0x1c,0x80,0x17,0xea,0x08,0x0f,
+0x03,0xd1,0x46,0x60,0x01,0x3b,0xd4,0xd1,0x03,0xe0,0x5f,0xf0,0x00,0x08,0xc0,0xf8,
+0x04,0x80,0x38,0x46,0x00,0xbe,0x00,0x00,0x00,0x00,0xee,0x07,
#define FLASH_FW (1 << 6)
#define FLASH_START (1 << 7)
-#define FLASH_SNB(a) ((a) << 8)
-
/* FLASH_SR register bits */
#define FLASH_BSY (1 << 0) /* Operation in progress */
#define FLASH_QW (1 << 2) /* Operation queue in progress */
#define FLASH_BANK1_ADDRESS 0x08100000
#define FLASH_REG_BASE_B0 0x52002000
#define FLASH_REG_BASE_B1 0x52002100
-#define FLASH_SIZE_ADDRESS 0x1FF1E880
-#define FLASH_BLOCK_SIZE 32
struct stm32h7x_rev {
uint16_t rev;
const char *str;
};
+/* stm32h7x_part_info permits the store each device information and specificities.
+ * the default unit is byte unless the suffix '_kb' is used. */
+
struct stm32h7x_part_info {
uint16_t id;
const char *device_str;
const struct stm32h7x_rev *revs;
size_t num_revs;
- unsigned int page_size;
+ unsigned int page_size_kb;
+ unsigned int block_size; /* flash write word size in bytes */
uint16_t max_flash_size_kb;
uint8_t has_dual_bank;
uint16_t first_bank_size_kb; /* Used when has_dual_bank is true */
uint32_t flash_regs_base; /* Flash controller registers location */
uint32_t fsize_addr; /* Location of FSIZE register */
+ uint32_t wps_group_size; /* write protection group sectors' count */
+ uint32_t wps_mask;
+ /* function to compute flash_cr register values */
+ uint32_t (*compute_flash_cr)(uint32_t cmd, int snb);
};
struct stm32h7x_flash_bank {
{ 0x1000, "A" }, { 0x1001, "Z" }, { 0x1003, "Y" }, { 0x2001, "X" }, { 0x2003, "V" },
};
+static const struct stm32h7x_rev stm32_480_revs[] = {
+ { 0x1000, "A"},
+};
+
+static uint32_t stm32x_compute_flash_cr_450(uint32_t cmd, int snb)
+{
+ return cmd | (snb << 8);
+}
+
+static uint32_t stm32x_compute_flash_cr_480(uint32_t cmd, int snb)
+{
+ /* save FW and START bits, to be right shifted by 2 bits later */
+ const uint32_t tmp = cmd & (FLASH_FW | FLASH_START);
+
+ /* mask parallelism (ignored), FW and START bits */
+ cmd &= ~(FLASH_PSIZE_64 | FLASH_FW | FLASH_START);
+
+ return cmd | (tmp >> 2) | (snb << 6);
+}
+
static const struct stm32h7x_part_info stm32h7x_parts[] = {
{
.id = 0x450,
.revs = stm32_450_revs,
.num_revs = ARRAY_SIZE(stm32_450_revs),
.device_str = "STM32H74x/75x",
- .page_size = 128, /* 128 KB */
+ .page_size_kb = 128,
+ .block_size = 32,
+ .max_flash_size_kb = 2048,
+ .first_bank_size_kb = 1024,
+ .has_dual_bank = 1,
+ .flash_regs_base = FLASH_REG_BASE_B0,
+ .fsize_addr = 0x1FF1E880,
+ .wps_group_size = 1,
+ .wps_mask = 0xFF,
+ .compute_flash_cr = stm32x_compute_flash_cr_450,
+ },
+ {
+ .id = 0x480,
+ .revs = stm32_480_revs,
+ .num_revs = ARRAY_SIZE(stm32_480_revs),
+ .device_str = "STM32H7Ax/7Bx",
+ .page_size_kb = 8,
+ .block_size = 16,
.max_flash_size_kb = 2048,
.first_bank_size_kb = 1024,
.has_dual_bank = 1,
.flash_regs_base = FLASH_REG_BASE_B0,
- .fsize_addr = FLASH_SIZE_ADDRESS,
+ .fsize_addr = 0x08FFF80C,
+ .wps_group_size = 4,
+ .wps_mask = 0xFFFFFFFF,
+ .compute_flash_cr = stm32x_compute_flash_cr_480,
},
};
stm32x_info->probed = false;
stm32x_info->user_bank_size = bank->size;
- bank->write_start_alignment = FLASH_BLOCK_SIZE;
- bank->write_end_alignment = FLASH_BLOCK_SIZE;
-
return ERROR_OK;
}
return retval;
}
- for (int i = 0; i < bank->num_sectors; i++) {
- bank->sectors[i].is_protected = protection & (1 << i) ? 0 : 1;
- }
+ for (int i = 0; i < bank->num_prot_blocks; i++)
+ bank->prot_blocks[i].is_protected = protection & (1 << i) ? 0 : 1;
+
return ERROR_OK;
}
static int stm32x_erase(struct flash_bank *bank, int first, int last)
{
+ struct stm32h7x_flash_bank *stm32x_info = bank->driver_priv;
int retval, retval2;
assert(first < bank->num_sectors);
for (int i = first; i <= last; i++) {
LOG_DEBUG("erase sector %d", i);
retval = stm32x_write_flash_reg(bank, FLASH_CR,
- FLASH_SER | FLASH_SNB(i) | FLASH_PSIZE_64);
+ stm32x_info->part_info->compute_flash_cr(FLASH_SER | FLASH_PSIZE_64, i));
if (retval != ERROR_OK) {
LOG_ERROR("Error erase sector %d", i);
goto flash_lock;
}
retval = stm32x_write_flash_reg(bank, FLASH_CR,
- FLASH_SER | FLASH_SNB(i) | FLASH_PSIZE_64 | FLASH_START);
+ stm32x_info->part_info->compute_flash_cr(FLASH_SER | FLASH_PSIZE_64 | FLASH_START, i));
if (retval != ERROR_OK) {
LOG_ERROR("Error erase sector %d", i);
goto flash_lock;
uint32_t offset, uint32_t count)
{
struct target *target = bank->target;
+ struct stm32h7x_flash_bank *stm32x_info = bank->driver_priv;
/*
- * If the size of the data part of the buffer is not a multiple of FLASH_BLOCK_SIZE, we get
+ * If the size of the data part of the buffer is not a multiple of .block_size, we get
* "corrupted fifo read" pointer in target_run_flash_async_algorithm()
*/
- uint32_t data_size = 512 * FLASH_BLOCK_SIZE; /* 16384 */
+ uint32_t data_size = 512 * stm32x_info->part_info->block_size;
uint32_t buffer_size = 8 + data_size;
struct working_area *write_algorithm;
struct working_area *source;
uint32_t address = bank->base + offset;
- struct reg_param reg_params[5];
+ struct reg_param reg_params[6];
struct armv7m_algorithm armv7m_info;
- struct stm32h7x_flash_bank *stm32x_info = bank->driver_priv;
int retval = ERROR_OK;
static const uint8_t stm32x_flash_write_code[] = {
init_reg_param(®_params[0], "r0", 32, PARAM_IN_OUT); /* buffer start, status (out) */
init_reg_param(®_params[1], "r1", 32, PARAM_OUT); /* buffer end */
init_reg_param(®_params[2], "r2", 32, PARAM_OUT); /* target address */
- init_reg_param(®_params[3], "r3", 32, PARAM_OUT); /* count (word-256 bits) */
- init_reg_param(®_params[4], "r4", 32, PARAM_OUT); /* flash reg base */
+ init_reg_param(®_params[3], "r3", 32, PARAM_OUT); /* count of words (word size = .block_size (bytes) */
+ init_reg_param(®_params[4], "r4", 32, PARAM_OUT); /* word size in bytes */
+ init_reg_param(®_params[5], "r5", 32, PARAM_OUT); /* flash reg base */
buf_set_u32(reg_params[0].value, 0, 32, source->address);
buf_set_u32(reg_params[1].value, 0, 32, source->address + source->size);
buf_set_u32(reg_params[2].value, 0, 32, address);
buf_set_u32(reg_params[3].value, 0, 32, count);
- buf_set_u32(reg_params[4].value, 0, 32, stm32x_info->flash_regs_base);
+ buf_set_u32(reg_params[4].value, 0, 32, stm32x_info->part_info->block_size);
+ buf_set_u32(reg_params[5].value, 0, 32, stm32x_info->flash_regs_base);
retval = target_run_flash_async_algorithm(target,
buffer,
count,
- FLASH_BLOCK_SIZE,
+ stm32x_info->part_info->block_size,
0, NULL,
- 5, reg_params,
+ ARRAY_SIZE(reg_params), reg_params,
source->address, source->size,
write_algorithm->address, 0,
&armv7m_info);
destroy_reg_param(®_params[2]);
destroy_reg_param(®_params[3]);
destroy_reg_param(®_params[4]);
+ destroy_reg_param(®_params[5]);
return retval;
}
uint32_t offset, uint32_t count)
{
struct target *target = bank->target;
+ struct stm32h7x_flash_bank *stm32x_info = bank->driver_priv;
uint32_t address = bank->base + offset;
int retval, retval2;
}
/* should be enforced via bank->write_start_alignment */
- assert(!(offset % FLASH_BLOCK_SIZE));
+ assert(!(offset % stm32x_info->part_info->block_size));
/* should be enforced via bank->write_end_alignment */
- assert(!(count % FLASH_BLOCK_SIZE));
+ assert(!(count % stm32x_info->part_info->block_size));
retval = stm32x_unlock_reg(bank);
if (retval != ERROR_OK)
goto flash_lock;
- uint32_t blocks_remaining = count / FLASH_BLOCK_SIZE;
+ uint32_t blocks_remaining = count / stm32x_info->part_info->block_size;
- /* multiple words (32-bytes) to be programmed in block */
+ /* multiple words (n * .block_size) to be programmed in block */
if (blocks_remaining) {
retval = stm32x_write_block(bank, buffer, offset, blocks_remaining);
if (retval != ERROR_OK) {
LOG_WARNING("couldn't use block writes, falling back to single memory accesses");
}
} else {
- buffer += blocks_remaining * FLASH_BLOCK_SIZE;
- address += blocks_remaining * FLASH_BLOCK_SIZE;
+ buffer += blocks_remaining * stm32x_info->part_info->block_size;
+ address += blocks_remaining * stm32x_info->part_info->block_size;
blocks_remaining = 0;
}
if ((retval != ERROR_OK) && (retval != ERROR_TARGET_RESOURCE_NOT_AVAILABLE))
4. Wait for flash operations completion
*/
while (blocks_remaining > 0) {
- retval = stm32x_write_flash_reg(bank, FLASH_CR, FLASH_PG | FLASH_PSIZE_64);
+ retval = stm32x_write_flash_reg(bank, FLASH_CR,
+ stm32x_info->part_info->compute_flash_cr(FLASH_PG | FLASH_PSIZE_64, 0));
if (retval != ERROR_OK)
goto flash_lock;
- retval = target_write_buffer(target, address, FLASH_BLOCK_SIZE, buffer);
+ retval = target_write_buffer(target, address, stm32x_info->part_info->block_size, buffer);
if (retval != ERROR_OK)
goto flash_lock;
if (retval != ERROR_OK)
goto flash_lock;
- buffer += FLASH_BLOCK_SIZE;
- address += FLASH_BLOCK_SIZE;
+ buffer += stm32x_info->part_info->block_size;
+ address += stm32x_info->part_info->block_size;
blocks_remaining--;
}
return (retval == ERROR_OK) ? retval2 : retval;
}
-static void setup_sector(struct flash_bank *bank, int start, int num, int size)
-{
- for (int i = start; i < (start + num) ; i++) {
- assert(i < bank->num_sectors);
- bank->sectors[i].offset = bank->size;
- bank->sectors[i].size = size;
- bank->size += bank->sectors[i].size;
- }
-}
-
static int stm32x_read_id_code(struct flash_bank *bank, uint32_t *id)
{
/* read stm32 device id register */
/* did we assign flash size? */
assert(flash_size_in_kb != 0xffff);
- /* calculate numbers of pages */
- int num_pages = flash_size_in_kb / stm32x_info->part_info->page_size;
+ bank->base = base_address;
+ bank->size = flash_size_in_kb * 1024;
+ bank->write_start_alignment = stm32x_info->part_info->block_size;
+ bank->write_end_alignment = stm32x_info->part_info->block_size;
- /* check that calculation result makes sense */
- assert(num_pages > 0);
+ /* setup sectors */
+ bank->num_sectors = flash_size_in_kb / stm32x_info->part_info->page_size_kb;
+ assert(bank->num_sectors > 0);
- if (bank->sectors) {
+ if (bank->sectors)
free(bank->sectors);
- bank->sectors = NULL;
- }
- bank->base = base_address;
- bank->num_sectors = num_pages;
- bank->sectors = malloc(sizeof(struct flash_sector) * num_pages);
+ bank->sectors = alloc_block_array(0, stm32x_info->part_info->page_size_kb * 1024,
+ bank->num_sectors);
+
if (bank->sectors == NULL) {
LOG_ERROR("failed to allocate bank sectors");
return ERROR_FAIL;
}
- bank->size = 0;
- /* fixed memory */
- setup_sector(bank, 0, num_pages, stm32x_info->part_info->page_size * 1024);
+ /* setup protection blocks */
+ const uint32_t wpsn = stm32x_info->part_info->wps_group_size;
+ assert(bank->num_sectors % wpsn == 0);
+
+ bank->num_prot_blocks = bank->num_sectors / wpsn;
+ assert(bank->num_prot_blocks > 0);
- for (int i = 0; i < num_pages; i++) {
- bank->sectors[i].is_erased = -1;
- bank->sectors[i].is_protected = 0;
+ if (bank->prot_blocks)
+ free(bank->prot_blocks);
+
+ bank->prot_blocks = alloc_block_array(0, stm32x_info->part_info->page_size_kb * wpsn * 1024,
+ bank->num_prot_blocks);
+
+ if (bank->prot_blocks == NULL) {
+ LOG_ERROR("failed to allocate bank prot_block");
+ return ERROR_FAIL;
}
- stm32x_info->probed = true;
+ stm32x_info->probed = 1;
return ERROR_OK;
}
{
int retval, retval2;
struct target *target = bank->target;
+ struct stm32h7x_flash_bank *stm32x_info = bank->driver_priv;
if (target->state != TARGET_HALTED) {
LOG_ERROR("Target not halted");
goto flash_lock;
/* mass erase flash memory bank */
- retval = stm32x_write_flash_reg(bank, FLASH_CR, FLASH_BER | FLASH_PSIZE_64);
+ retval = stm32x_write_flash_reg(bank, FLASH_CR,
+ stm32x_info->part_info->compute_flash_cr(FLASH_BER | FLASH_PSIZE_64, 0));
if (retval != ERROR_OK)
goto flash_lock;
- retval = stm32x_write_flash_reg(bank, FLASH_CR, FLASH_BER | FLASH_PSIZE_64 | FLASH_START);
+ retval = stm32x_write_flash_reg(bank, FLASH_CR,
+ stm32x_info->part_info->compute_flash_cr(FLASH_BER | FLASH_PSIZE_64 | FLASH_START, 0));
if (retval != ERROR_OK)
goto flash_lock;
Code Review / openocd.git / commitdiff