flash/nor/stm32h7x: fix option bytes handling to work with both banks 91/5291/4
authorTarek BOCHKATI <tarek.bouchkati@gmail.com>
Thu, 29 Aug 2019 13:58:39 +0000 (15:58 +0200)
committerTomas Vanek <vanekt@fbl.cz>
Wed, 27 Nov 2019 06:16:40 +0000 (06:16 +0000)
commit8d8c6df557ab1976c6df39cf712b6ef23ce8a27e
tree51408d345a44d608d4f7b48d2fdd46e0990fdc87
parent1b276c0ad56ed7d1ef72787b6bee885ac5d063a8
flash/nor/stm32h7x: fix option bytes handling to work with both banks

To achieve that we need to avoid using FLASH_REG_BASE_B0, and use
bank registers instead:
   For dual bank devices, each option register is mapped in 2 addresses
   at the same offset from flash_bank_reg_base.
   This is true for OPTCR, OPTKEYR, OPTSR_CUR/PRG, OPTCCR according to
   RM0433 Rev6 (refer to section 3.9: FLASH registers)

In stm32x_write_options, according to RM0433 Rev6, after OBL launch we
should wait for OPTSR_CUR.BSY bit instead of FLASH_SR.QW

Change-Id: Ie24a91f069d03c9233797390fc2e925c737dad90
Signed-off-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
Reviewed-on: http://openocd.zylin.com/5291
Tested-by: jenkins
Reviewed-by: Christopher Head <chead@zaber.com>
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
src/flash/nor/stm32h7x.c