flash/nor/psoc6: remove setting of xPSR.T bit from sromalgo_prepare()
PSoC6 erases flash to 0x00 not more common 0xff, so a device
with erased flash loads xPSR.T=0 from the zeroed reset vector.
Wrong thumb bit value caused a target algorithm failed with HardFault.
The low level write to xPSR solved the problem only if xPSR cached
copy was not marked dirty.
Later commit
49bd64347a21f5e12b33c256171b3035126d1260 fixed T setting
for all Cortex-M target algorithms.
Since 49bd64 this part of code is useless as xPSR target_start_algorithm()
sets always xPSR dirty so the effect of the low level write is eliminated
(and proper setting of thumb bit is ensured in target_start_algorithm())
Change-Id: I68aea5e921fbc6203f2fe91a45f10d22869327de
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: http://openocd.zylin.com/5875
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
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