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target/arc: Introduce L1I,L1D,L2 caches support 88/5688/5
authorEvgeniy Didin <didin@synopsys.com>
Fri, 15 May 2020 20:04:01 +0000 (23:04 +0300)
committerAntonio Borneo <borneo.antonio@gmail.com>
Sat, 27 Jun 2020 14:34:24 +0000 (15:34 +0100)
commit057aed11a2f80645322ff76c7dd0c7908582d0a4
tree1dbf0f12ea59e53d4c3dfe25c6700448ac6722e5tree | snapshot
parent2e6904eef5e81e71453168ed8c6f649e3a5c0f6ccommit | diff
target/arc: Introduce L1I,L1D,L2 caches support

With this commit we introduce L1 and L2 cache
flush and invalidate operations which are necessary for
getting/setting actual data during memory r/w operations.

We introduce L2 cache support, which is not presented
on currently support EMSK board. But L2 is presented
on HSDK board, which soon will be introduced.

Change-Id: I2fda505a47ecb8833cc9f5ffe24f6a4e22ab6eb0
Signed-off-by: Evgeniy Didin <didin@synopsys.com>
Reviewed-on: http://openocd.zylin.com/5688
Reviewed-by: Oleksij Rempel <linux@rempel-privat.de>
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
src/target/arc.c diff | blob | history
src/target/arc.h diff | blob | history
src/target/arc_cmd.c diff | blob | history
src/target/arc_mem.c diff | blob | history
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