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stlink: Set speed before entering JTAG/SWD mode 18/4818/4
authorFrans-Willem Hardijzer <fw@hardijzer.nl>
Sat, 22 Dec 2018 11:03:43 +0000 (12:03 +0100)
committerTomas Vanek <vanekt@fbl.cz>
Tue, 26 Mar 2019 08:20:06 +0000 (08:20 +0000)
commit89f07325f2e7ca9d28ba0c54a26e3aab8b34984a
tree4d9bdad8b154cb156cc861f6539c3769e5e0df3etree | snapshot
parentb2e56656dcf3acecde8af73aa13a33814085bef3commit | diff
stlink: Set speed before entering JTAG/SWD mode

Some boards require a slower clock speed because of passive components on the
JTAG/SWD lines. The previous implementation would first try to discover the
chips on the default speed, and only after discovery switch to the requested
adapter_khz speed.

This patch moves the speed change to just before entering the SWD/JTAG mode,
which should alleviate this problem.

Tested on an STLink V2 clone.

Change-Id: I9734452dcc8bb28d6629e64d9a7e32ef92868cf9
Signed-off-by: Frans-Willem Hardijzer <fw@hardijzer.nl>
Reviewed-on: http://openocd.zylin.com/4818
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
src/jtag/drivers/stlink_usb.c diff | blob | history
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