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(parent: 3edcb94) | patch
flash/nor/jtagspi: add JTAGSPI driver 44/2844/13
authorRobert Jordens <jordens@gmail.com>
Wed, 1 Jul 2015 09:18:46 +0000 (03:18 -0600)
committerSpencer Oliver <spen@spen-soft.co.uk>
Thu, 6 Aug 2015 12:14:08 +0000 (13:14 +0100)
commitd25355473da9a925a696183a9947aac292cd2f60
treefa695378980ccf9cf0b326a2df4c7dc53709b471tree | snapshot
parent3edcb941864d677e30d36ad77c22d86ec7ac8eb3commit | diff
flash/nor/jtagspi: add JTAGSPI driver

Many FPGA board speak JTAG and have a SPI flash for their bitstream
attached to them. The SPI flash is programmed by first uploading a
proxy bitstream to the FPGA that connects the JTAG interface to the
SPI interface if the IR contains a certain USER instruction. Then the
SPI flash can be erase, written, read directly through the JTAG DR.

The JTAG and SPI signaling is compatible. Such a proxy bitstream only
needs to connect TDO-MISO, TDI-MOSI, TCK-CLK, and the activate the
chip select when the IR contains the special instruction and the JTAG
state machine is in the DR-SHIFT state.

Change-Id: Ibc21d793a83b36fa37e2704966aa5c837c4dd0d2
Signed-off-by: Robert Jordens <jordens@gmail.com>
Reviewed-on: http://openocd.zylin.com/2844
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
contrib/loaders/flash/fpga/xilinx_bscan_spi.py [new file with mode: 0755] blob
doc/openocd.texi diff | blob | history
src/flash/nor/Makefile.am diff | blob | history
src/flash/nor/drivers.c diff | blob | history
src/flash/nor/jtagspi.c [new file with mode: 0644] blob
tcl/cpld/jtagspi.cfg [new file with mode: 0644] blob
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