mips32: Sync Caches to Make Instr Writes Effective
authorDrasko DRASKOVIC <drasko.draskovic@gmail.com>
Thu, 7 Jul 2011 15:59:13 +0000 (17:59 +0200)
committerØyvind Harboe <oyvind.harboe@zylin.com>
Tue, 9 Aug 2011 21:17:28 +0000 (23:17 +0200)
commitc18e02387b0628a9ecfc41a65af4802e8b95357e
treee5c0ebe5c2bf3ef8ce0ec7bf83b0a6d0b9f5c9a3
parent1be7163408cc6420d85bf990a2dae46c559a12b1
mips32: Sync Caches to Make Instr Writes Effective

Pprogram that loads another program into memory is actually writing the
D- side cache.
The instructions it has loaded can't be executed until they reach the
I-cache.

After the instructions have been written, the loader should arrange to
write back any containing D-cache line and invalidate any locations
already in the I-cache.

For the MIPS Architecture Release2 cores, we can use synci command
that does this job.
For Release1 we must use "cache" instruction.
src/target/mips32.h
src/target/mips32_pracc.c

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