Lots of RISC-V improvements. 22/4922/3
authorTim Newsome <tim@sifive.com>
Fri, 15 Feb 2019 20:08:51 +0000 (12:08 -0800)
committerMatthias Welwarsky <matthias@welwarsky.de>
Wed, 27 Mar 2019 08:53:09 +0000 (08:53 +0000)
commitbc72695f6738951571502706bd48680de5ccc84c
tree66a66342d6b3bd1f38dc33facb7ab1e433309236
parent89f07325f2e7ca9d28ba0c54a26e3aab8b34984a
Lots of RISC-V improvements.

This represents months of continuing RISC-V work, with too many changes
to list individually. Some improvements:
* Fixed memory leaks.
* Better handling of dbus timeouts.
* Add `riscv expose_custom` command.
* Somewhat deal with cache coherency.
* Deal with more timeouts during block memory accesses.
* Basic debug compliance test.
* Tell gdb which watchpoint hit.
* SMP support for use with -rtos hwthread
* Add `riscv set_ir`

Change-Id: Ica507ee2a57eaf51b578ab1d9b7de71512fdf47f
Signed-off-by: Tim Newsome <tim@sifive.com>
Reviewed-on: http://openocd.zylin.com/4922
Tested-by: jenkins
Reviewed-by: Philipp Guehring <pg@futureware.at>
Reviewed-by: Liviu Ionescu <ilg@livius.net>
Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
doc/openocd.texi
src/target/riscv/batch.c
src/target/riscv/opcodes.h
src/target/riscv/program.h
src/target/riscv/riscv-011.c
src/target/riscv/riscv-013.c
src/target/riscv/riscv.c
src/target/riscv/riscv.h