Add RISC-V support. 78/4578/5
authorTim Newsome <tim@sifive.com>
Wed, 18 Jul 2018 20:34:23 +0000 (13:34 -0700)
committerMatthias Welwarsky <matthias@welwarsky.de>
Tue, 24 Jul 2018 12:07:26 +0000 (13:07 +0100)
commita51ab8ddf63a0d60eaaf3b8f3eedcada1e773c20
tree60cd18e3649cbc2700abfe7724954e97de640229
parent9363705820d9552bd24a4e876041a90a881ede55
Add RISC-V support.

This supports both 0.11 and 0.13 versions of the debug spec.

Support for `-rtos riscv` will come in a separate commit since it was
easy to separate out, and is likely to be more controversial.

Flash support for the SiFive boards will also come in a later commit.

Change-Id: I1d38fe669c2041b4e21a5c54a091594aac3e2190
Signed-off-by: Tim Newsome <tim@sifive.com>
Reviewed-on: http://openocd.zylin.com/4578
Tested-by: jenkins
Reviewed-by: Liviu Ionescu <ilg@livius.net>
Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
22 files changed:
doc/openocd.texi
src/helper/log.h
src/target/Makefile.am
src/target/riscv/Makefile.am [new file with mode: 0644]
src/target/riscv/asm.h [new file with mode: 0644]
src/target/riscv/batch.c [new file with mode: 0644]
src/target/riscv/batch.h [new file with mode: 0644]
src/target/riscv/debug_defines.h [new file with mode: 0644]
src/target/riscv/encoding.h [new file with mode: 0644]
src/target/riscv/gdb_regs.h [new file with mode: 0644]
src/target/riscv/opcodes.h [new file with mode: 0644]
src/target/riscv/program.c [new file with mode: 0644]
src/target/riscv/program.h [new file with mode: 0644]
src/target/riscv/riscv-011.c [new file with mode: 0644]
src/target/riscv/riscv-013.c [new file with mode: 0644]
src/target/riscv/riscv.c [new file with mode: 0644]
src/target/riscv/riscv.h [new file with mode: 0644]
src/target/riscv/riscv_semihosting.c [new file with mode: 0644]
src/target/target.c
tcl/board/sifive-e31arty.cfg [new file with mode: 0644]
tcl/board/sifive-e51arty.cfg [new file with mode: 0644]
tcl/board/sifive-hifive1.cfg [new file with mode: 0644]