xilinx-xcu: add Xilinx Ultrascale tap data 88/4188/8
authorRobert Jordens <jordens@gmail.com>
Thu, 3 Aug 2017 10:25:07 +0000 (12:25 +0200)
committerMatthias Welwarsky <matthias@welwarsky.de>
Fri, 30 Mar 2018 09:07:49 +0000 (10:07 +0100)
commit7944ebb6945d01e2f603f80c5c70f349c8338950
treeccb267caac42b771bc35b07a67aead4587dd32ca
parent2231da8ec4e7d7ae9b652f3dd1a7104f5a110f3f
xilinx-xcu: add Xilinx Ultrascale tap data

The Ultrascale series is a bit more complicated to handle since with the
stacked and interconnected dies the IR gets longer. This adds support
for all currently known chips from the Ultrascale family.

Change-Id: Ibac325dd6fadc76f73cc682b1c62c1a5f39f0786
Signed-off-by: Robert Jordens <jordens@gmail.com>
Reviewed-on: http://openocd.zylin.com/4188
Tested-by: jenkins
Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
tcl/cpld/xilinx-xcu.cfg [new file with mode: 0644]