esirisc: support eSi-RISC targets 60/4660/17
authorSteven Stallion <stallion@squareup.com>
Wed, 29 Aug 2018 00:18:01 +0000 (17:18 -0700)
committerMatthias Welwarsky <matthias@welwarsky.de>
Tue, 16 Oct 2018 10:58:24 +0000 (11:58 +0100)
commit4ab75a3634901c4e3897d771e2c75a64c7353c28
tree475731fa20dae25c39a88804e894b69c69900e2f
parente72b2601e71f49af10f72c4bb6220ee2061ef173
esirisc: support eSi-RISC targets

eSi-RISC is a highly configurable microprocessor architecture for
embedded systems provided by EnSilica. This patch adds support for
32-bit targets and also includes an internal flash driver and
uC/OS-III RTOS support. This is a non-traditional target and required
a number of additional changes to support non-linear register numbers
and the 'p' packet in RTOS support for proper integration into
EnSilica's GDB port.

Change-Id: I59d5c40b3bb2ace1b1a01b2538bfab211adf113f
Signed-off-by: Steven Stallion <stallion@squareup.com>
Reviewed-on: http://openocd.zylin.com/4660
Tested-by: jenkins
Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
17 files changed:
README
doc/openocd.texi
src/flash/nor/Makefile.am
src/flash/nor/drivers.c
src/flash/nor/esirisc_flash.c [new file with mode: 0644]
src/rtos/rtos_ucos_iii_stackings.c
src/rtos/rtos_ucos_iii_stackings.h
src/rtos/uCOS-III.c
src/target/Makefile.am
src/target/esirisc.c [new file with mode: 0644]
src/target/esirisc.h [new file with mode: 0644]
src/target/esirisc_jtag.c [new file with mode: 0644]
src/target/esirisc_jtag.h [new file with mode: 0644]
src/target/esirisc_regs.h [new file with mode: 0644]
src/target/target.c
src/target/target.h
tcl/target/esi32xx.cfg [new file with mode: 0644]