+
+ | ID |
+ Target |
+ Interface |
+ Description |
+ Initial state |
+ Input |
+ Expected output |
+ Actual output |
+ Pass/Fail |
+
+
+ | RES001 |
+ LPC2148 |
+ ZY1000 |
+ Reset halt on a blank target |
+ Erase all the content of the flash |
+ Connect via the telnet interface and type
reset halt |
+ Reset should return without error and the output should contain
target state: halted |
+
+
+ > mdw 0 32
+ 0x00000000: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff
+ 0x00000020: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff
+ 0x00000040: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff
+ 0x00000060: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff
+ > reset halt
+ JTAG tap: lpc2148.cpu tap/device found: 0x4f1f0f0f (mfg: 0x787, part: 0xf1f0, ver: 0x4)
+ srst pulls trst - can not reset into halted mode. Issuing halt after reset.
+ target state: halted
+ target halted in Thumb state due to debug-request, current mode: Supervisor
+ cpsr: 0xa00000f3 pc: 0x7fffd2d6
+ >
+
+ |
+ PASS |
+
+
+ | RES002 |
+ LPC2148 |
+ ZY1000 |
+ Reset init on a blank target |
+ Erase all the content of the flash |
+ Connect via the telnet interface and type
reset init |
+ Reset should return without error and the output should contain
executing reset script 'name_of_the_script' |
+
+
+ > reset init
+ JTAG tap: lpc2148.cpu tap/device found: 0x4f1f0f0f (mfg: 0x787, part: 0xf1f0, ver: 0x4)
+ srst pulls trst - can not reset into halted mode. Issuing halt after reset.
+ target state: halted
+ target halted in Thumb state due to debug-request, current mode: Supervisor
+ cpsr: 0xa00000f3 pc: 0x7fffd2da
+ core state: ARM
+ >
+
+ |
+ PASS
+ NOTE! Even if there is no message, the reset script is being executed (proved by side effects) |
+
+
+ | RES003 |
+ LPC2148 |
+ ZY1000 |
+ Reset after a power cycle of the target |
+ Reset the target then power cycle the target |
+ Connect via the telnet interface and type
reset halt after the power was detected |
+ Reset should return without error and the output should contain
target state: halted |
+
+
+ nsed nSRST asserted.
+ nsed power dropout.
+ nsed power restore.
+ SRST took 186ms to deassert
+ JTAG tap: lpc2148.cpu tap/device found: 0x4f1f0f0f (mfg: 0x787, part: 0xf1f0, ver: 0x4)
+ srst pulls trst - can not reset into halted mode. Issuing halt after reset.
+ target state: halted
+ target halted in Thumb state due to debug-request, current mode: Supervisor
+ cpsr: 0xa00000f3 pc: 0x7fffd2d6
+ core state: ARM
+ > reset halt
+ JTAG tap: lpc2148.cpu tap/device found: 0x4f1f0f0f (mfg: 0x787, part: 0xf1f0, ver: 0x4)
+ srst pulls trst - can not reset into halted mode. Issuing halt after reset.
+ target state: halted
+ target halted in Thumb state due to debug-request, current mode: Supervisor
+ cpsr: 0xa00000f3 pc: 0x7fffd2d6
+ >
+
+ |
+ PASS |
+
+
+ | RES004 |
+ LPC2148 |
+ ZY1000 |
+ Reset halt on a blank target where reset halt is supported |
+ Erase all the content of the flash |
+ Connect via the telnet interface and type
reset halt |
+ Reset should return without error and the output should contain
target state: halted
pc = 0 |
+
+
+ > reset halt
+ JTAG tap: lpc2148.cpu tap/device found: 0x4f1f0f0f (mfg: 0x787, part: 0xf1f0, ver: 0x4)
+ srst pulls trst - can not reset into halted mode. Issuing halt after reset.
+ target state: halted
+ target halted in Thumb state due to debug-request, current mode: Supervisor
+ cpsr: 0xa00000f3 pc: 0x7fffd2d6
+ >
+
+ |
+ PASS |
+
+
+ | RES005 |
+ LPC2148 |
+ ZY1000 |
+ Reset halt on a blank target using return clock |
+ Erase all the content of the flash, set the configuration script to use RCLK |
+ Connect via the telnet interface and type
reset halt |
+ Reset should return without error and the output should contain
target state: halted |
+
+
+ > jtag_khz 0
+ RCLK - adaptive
+ > reset init
+ JTAG tap: lpc2148.cpu tap/device found: 0x4f1f0f0f (mfg: 0x787, part: 0xf1f0, ver: 0x4)
+ srst pulls trst - can not reset into halted mode. Issuing halt after reset.
+ target state: halted
+ target halted in Thumb state due to debug-request, current mode: Supervisor
+ cpsr: 0xa00000f3 pc: 0x7fffd2d6
+ core state: ARM
+ >
+
+ |
+ PASS |
+
+
+
+
+
+ | ID |
+ Target |
+ ZY1000 |
+ Description |
+ Initial state |
+ Input |
+ Expected output |
+ Actual output |
+ Pass/Fail |
+
+
+ | SPD001 |
+ LPC2148 |
+ ZY1000 |
+ 16MHz on normal operation |
+ Reset init the target according to RES002 |
+ Change speed and exercise a memory access over the JTAG, for example
mdw 0x0 32 |
+ The command should run without any errors. If any JTAG checking errors happen, the test failed |
+
+
+ > jtag_khz 16000
+ jtag_speed 4 => JTAG clk=16.000000
+ 16000 kHz
+ > reset halt
+ JTAG scan chain interrogation failed: all zeroes
+ Check JTAG interface, timings, target power, etc.
+ error: -100
+ Command handler execution failed
+ in procedure 'reset' called at file "command.c", line 638
+ called at file "/home/laurentiu/workspace/zy1000/build/../openocd/src/helper/command.c", line 352
+ invalid mode value encountered 0
+ cpsr contains invalid mode value - communication failure
+ ThumbEE -- incomplete support
+ target state: halted
+ target halted in ThumbEE state due to debug-request, current mode: System
+ cpsr: 0x1fffffff pc: 0xfffffffa
+ invalid mode value encountered 0
+ cpsr contains invalid mode value - communication failure
+ target state: halted
+ target halted in Thumb state due to debug-request, current mode: System
+ cpsr: 0xc00003ff pc: 0xfffffff0
+ invalid mode value encountered 0
+ cpsr contains invalid mode value - communication failure
+ invalid mode value encountered 0
+ cpsr contains invalid mode value - communication failure
+ invalid mode value encountered 0
+ cpsr contains invalid mode value - communication failure
+ invalid mode value encountered 0
+ cpsr contains invalid mode value - communication failure
+ ThumbEE -- incomplete support
+ target state: halted
+ target halted in ThumbEE state due to debug-request, current mode: System
+ cpsr: 0xffffffff pc: 0xfffffffa
+ >
+
+ |
+ FAIL |
+
+
+ | SPD002 |
+ LPC2148 |
+ ZY1000 |
+ 8MHz on normal operation |
+ Reset init the target according to RES002 |
+ Change speed and exercise a memory access over the JTAG, for example
mdw 0x0 32 |
+ The command should run without any errors. If any JTAG checking errors happen, the test failed |
+
+
+ > jtag_khz 8000
+ jtag_speed 8 => JTAG clk=8.000000
+ 8000 kHz
+ > reset halt
+ JTAG scan chain interrogation failed: all zeroes
+ Check JTAG interface, timings, target power, etc.
+ error: -100
+ Command handler execution failed
+ in procedure 'reset' called at file "command.c", line 638
+ called at file "/home/laurentiu/workspace/zy1000/build/../openocd/src/helper/command.c", line 352
+ invalid mode value encountered 0
+ cpsr contains invalid mode value - communication failure
+ invalid mode value encountered 0
+ cpsr contains invalid mode value - communication failure
+ >
+
+ |
+ FAIL |
+
+
+ | SPD003 |
+ LPC2148 |
+ ZY1000 |
+ 4MHz on normal operation |
+ Reset init the target according to RES002 |
+ Change speed and exercise a memory access over the JTAG, for example
mdw 0x0 32 |
+ The command should run without any errors. If any JTAG checking errors happen, the test failed |
+
+
+ > jtag_khz 4000
+ jtag_speed 16 => JTAG clk=4.000000
+ 4000 kHz
+ > reset halt
+ JTAG tap: lpc2148.cpu tap/device found: 0xc79f0f87 (mfg: 0x7c3, part: 0x79f0, ver: 0xc)
+ JTAG tap: lpc2148.cpu UNEXPECTED: 0xc79f0f87 (mfg: 0x7c3, part: 0x79f0, ver: 0xc)
+ JTAG tap: lpc2148.cpu expected 1 of 1: 0x4f1f0f0f (mfg: 0x787, part: 0xf1f0, ver: 0x4)
+ Unexpected idcode after end of chain: 64 0x0000007f
+ Unexpected idcode after end of chain: 160 0x0000007f
+ Unexpected idcode after end of chain: 192 0x0000007f
+ Unexpected idcode after end of chain: 320 0x0000007f
+ Unexpected idcode after end of chain: 352 0x0000007f
+ Unexpected idcode after end of chain: 384 0x0000007f
+ Unexpected idcode after end of chain: 480 0x0000007f
+ Unexpected idcode after end of chain: 512 0x0000007f
+ Unexpected idcode after end of chain: 544 0x0000007f
+ double-check your JTAG setup (interface, speed, missing TAPs, ...)
+ error: -100
+ Command handler execution failed
+ in procedure 'reset' called at file "command.c", line 638
+ called at file "/home/laurentiu/workspace/zy1000/build/../openocd/src/helper/command.c", line 352
+ >
+
+ |
+ FAIL |
+
+
+ | SPD004 |
+ LPC2148 |
+ ZY1000 |
+ 2MHz on normal operation |
+ Reset init the target according to RES002 |
+ Change speed and exercise a memory access over the JTAG, for example
mdw 0x0 32 |
+ The command should run without any errors. If any JTAG checking errors happen, the test failed |
+
+
+ > jtag_khz 2000
+ jtag_speed 32 => JTAG clk=2.000000
+ 2000 kHz
+ > reset halt
+ JTAG tap: lpc2148.cpu tap/device found: 0x4f1f0f0f (mfg: 0x787, part: 0xf1f0, ver: 0x4)
+ srst pulls trst - can not reset into halted mode. Issuing halt after reset.
+ target state: halted
+ target halted in Thumb state due to debug-request, current mode: Supervisor
+ cpsr: 0xa00000f3 pc: 0x7fffd2da
+ > mdw 0 32
+ 0x00000000: e59f4034 e3a05002 e5845000 e3a05003 e5845004 e59f201c e3a03000 e1020093
+ 0x00000020: e2822028 e1021093 e3c03007 e5023028 e51ff004 7fffd1c4 e002c014 e01fc000
+ 0x00000040: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff
+ 0x00000060: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff
+ >
+
+ |
+ PASS |
+
+
+ | SPD005 |
+ LPC2148 |
+ ZY1000 |
+ RCLK on normal operation |
+ Reset init the target according to RES002 |
+ Change speed and exercise a memory access over the JTAG, for example
mdw 0x0 32 |
+ The command should run without any errors. If any JTAG checking errors happen, the test failed |
+
+
+ > jtag_khz 0
+ RCLK - adaptive
+ > mdw 0 32
+ 0x00000000: e59f4034 e3a05002 e5845000 e3a05003 e5845004 e59f201c e3a03000 e1020093
+ 0x00000020: e2822028 e1021093 e3c03007 e5023028 e51ff004 7fffd1c4 e002c014 e01fc000
+ 0x00000040: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff
+ 0x00000060: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff
+ >
+
+ |
+ PASS |
+
+
+
+
+
+ | ID |
+ Target |
+ Interface |
+ Description |
+ Initial state |
+ Input |
+ Expected output |
+ Actual output |
+ Pass/Fail |
+
+
+ | DBG001 |
+ LPC2148 |
+ ZY1000 |
+ Load is working |
+ Reset init is working, RAM is accesible, GDB server is started |
+ On the console of the OS:
+ arm-elf-gdb test_ram.elf
+ (gdb) target remote ip:port
+ (gdb) load
+ |
+ Load should return without error, typical output looks like:
+
+ Loading section .text, size 0x14c lma 0x0
+ Start address 0x40, load size 332
+ Transfer rate: 180 bytes/sec, 332 bytes/write.
+
+ |
+
+ (gdb) load
+ Loading section .text, size 0x16c lma 0x40000000
+ Start address 0x40000040, load size 364
+ Transfer rate: 32 KB/sec, 364 bytes/write.
+ (gdb)
+ |
+ PASS |
+
+
+
+ | DBG002 |
+ LPC2148 |
+ ZY1000 |
+ Software breakpoint |
+ Load the test_ram.elf application, use instructions from GDB001 |
+ In the GDB console:
+
+ (gdb) monitor gdb_breakpoint_override soft
+ software breakpoints enabled
+ (gdb) break main
+ Breakpoint 1 at 0xec: file src/main.c, line 71.
+ (gdb) continue
+ Continuing.
+
+ |
+ The software breakpoint should be reached, a typical output looks like:
+
+ target state: halted
+ target halted in ARM state due to breakpoint, current mode: Supervisor
+ cpsr: 0x000000d3 pc: 0x000000ec
+
+ Breakpoint 1, main () at src/main.c:71
+ 71 DWORD a = 1;
+
+ |
+
+
+ (gdb) monitor gdb_breakpoint_override soft
+ force soft breakpoints
+ Current language: auto
+ The current source language is "auto; currently asm".
+ (gdb) break main
+ Breakpoint 1 at 0x4000010c: file src/main.c, line 71.
+ (gdb) c
+ Continuing.
+
+ Breakpoint 1, main () at src/main.c:71
+ 71 DWORD a = 1;
+ Current language: auto
+ The current source language is "auto; currently c".
+ (gdb)
+
+ |
+ PASS |
+
+
+ | DBG003 |
+ LPC2148 |
+ ZY1000 |
+ Single step in a RAM application |
+ Load the test_ram.elf application, use instructions from GDB001, break in main using the instructions from GDB002 |
+ In GDB, type
(gdb) step |
+ The next instruction should be reached, typical output:
+
+ (gdb) step
+ target state: halted
+ target halted in ARM state due to single step, current mode: Abort
+ cpsr: 0x20000097 pc: 0x000000f0
+ target state: halted
+ target halted in ARM state due to single step, current mode: Abort
+ cpsr: 0x20000097 pc: 0x000000f4
+ 72 DWORD b = 2;
+
+ |
+
+
+ (gdb) step
+ 72 DWORD b = 2;
+ (gdb)
+
+ |
+ PASS |
+
+
+ | DBG004 |
+ LPC2148 |
+ ZY1000 |
+ Software break points are working after a reset |
+ Load the test_ram.elf application, use instructions from GDB001, break in main using the instructions from GDB002 |
+ In GDB, type
+ (gdb) monitor reset init
+ (gdb) load
+ (gdb) continue
+ |
+ The breakpoint should be reached, typical output:
+
+ target state: halted
+ target halted in ARM state due to breakpoint, current mode: Supervisor
+ cpsr: 0x000000d3 pc: 0x000000ec
+
+ Breakpoint 1, main () at src/main.c:71
+ 71 DWORD a = 1;
+
+ |
+
+ (gdb) moni reset init
+ JTAG tap: lpc2148.cpu tap/device found: 0x4f1f0f0f (mfg: 0x787, part: 0xf1f0, ver: 0x4)
+ srst pulls trst - can not reset into halted mode. Issuing halt after reset.
+ target state: halted
+ target halted in Thumb state due to debug-request, current mode: Supervisor
+ cpsr: 0xa00000f3 pc: 0x7fffd2d6
+ core state: ARM
+ (gdb) load
+ Loading section .text, size 0x16c lma 0x40000000
+ Start address 0x40000040, load size 364
+ Transfer rate: 27 KB/sec, 364 bytes/write.
+ (gdb) c
+ Continuing.
+
+ Breakpoint 1, main () at src/main.c:71
+ 71 DWORD a = 1;
+ (gdb)
+ |
+ PASS |
+
+
+ | DBG005 |
+ LPC2148 |
+ ZY1000 |
+ Hardware breakpoint |
+ Flash the test_rom.elf application. Make this test after FLA004 has passed |
+ Be sure that gdb_memory_map and gdb_flash_program are enabled. In GDB, type
+
+ (gdb) monitor reset init
+ (gdb) load
+ Loading section .text, size 0x194 lma 0x100000
+ Start address 0x100040, load size 404
+ Transfer rate: 179 bytes/sec, 404 bytes/write.
+ (gdb) monitor gdb_breakpoint_override hard
+ force hard breakpoints
+ (gdb) break main
+ Breakpoint 1 at 0x100134: file src/main.c, line 69.
+ (gdb) continue
+
+ |
+ The breakpoint should be reached, typical output:
+
+ Continuing.
+
+ Breakpoint 1, main () at src/main.c:69
+ 69 DWORD a = 1;
+
+ |
+
+
+ (gdb) monitor gdb_breakpoint_override hard
+ force hard breakpoints
+ (gdb) break main
+ Breakpoint 1 at 0x10c: file src/main.c, line 71.
+ (gdb) continue
+ Continuing.
+ Note: automatically using hardware breakpoints for read-only addresses.
+
+ Breakpoint 1, main () at src/main.c:71
+ 71 DWORD a = 1;
+ Current language: auto
+ The current source language is "auto; currently c".
+ (gdb)
+
+ |
+ PASS NOTE: This test is failing from time to time, not able to describe a cause |
+
+
+ | DBG006 |
+ LPC2148 |
+ ZY1000 |
+ Hardware breakpoint is set after a reset |
+ Follow the instructions to flash and insert a hardware breakpoint from DBG005 |
+ In GDB, type
+
+ (gdb) monitor reset
+ (gdb) monitor reg pc 0x100000
+ pc (/32): 0x00100000
+ (gdb) continue
+
+ where the value inserted in PC is the start address of the application
+ |
+ The breakpoint should be reached, typical output:
+
+ Continuing.
+
+ Breakpoint 1, main () at src/main.c:69
+ 69 DWORD a = 1;
+
+ |
+
+
+ (gdb) monitor reset init
+ JTAG tap: lpc2148.cpu tap/device found: 0x4f1f0f0f (mfg: 0x787, part: 0xf1f0, ver: 0x4)
+ srst pulls trst - can not reset into halted mode. Issuing halt after reset.
+ target state: halted
+ target halted in ARM state due to debug-request, current mode: Supervisor
+ cpsr: 0x60000013 pc: 0x00000160
+ core state: ARM
+ (gdb) monitor reg pc 0x40
+ pc (/32): 0x00000040
+ (gdb) continue
+ Continuing.
+
+ Breakpoint 1, main () at src/main.c:71
+ 71 DWORD a = 1;
+ (gdb)
+
+ |
+ PASS |
+
+
+ | DBG007 |
+ LPC2148 |
+ ZY1000 |
+ Single step in ROM |
+ Flash the test_rom.elf application and set a breakpoint in main, use DBG005. Make this test after FLA004 has passed |
+ Be sure that gdb_memory_map and gdb_flash_program are enabled. In GDB, type
+
+ (gdb) monitor reset
+ (gdb) load
+ Loading section .text, size 0x194 lma 0x100000
+ Start address 0x100040, load size 404
+ Transfer rate: 179 bytes/sec, 404 bytes/write.
+ (gdb) monitor gdb_breakpoint_override hard
+ force hard breakpoints
+ (gdb) break main
+ Breakpoint 1 at 0x100134: file src/main.c, line 69.
+ (gdb) continue
+ Continuing.
+
+ Breakpoint 1, main () at src/main.c:69
+ 69 DWORD a = 1;
+ (gdb) step
+
+ |
+ The breakpoint should be reached, typical output:
+
+ target state: halted
+ target halted in ARM state due to single step, current mode: Supervisor
+ cpsr: 0x60000013 pc: 0x0010013c
+ 70 DWORD b = 2;
+
+ |
+
+ (gdb) load
+ Loading section .text, size 0x16c lma 0x0
+ Start address 0x40, load size 364
+ Transfer rate: 637 bytes/sec, 364 bytes/write.
+ (gdb) monitor gdb_breakpoint_override hard
+ force hard breakpoints
+ Current language: auto
+ The current source language is "auto; currently asm".
+ (gdb) break main
+ Breakpoint 1 at 0x10c: file src/main.c, line 71.
+ (gdb) continue
+ Continuing.
+ Note: automatically using hardware breakpoints for read-only addresses.
+
+ Breakpoint 1, main () at src/main.c:71
+ 71 DWORD a = 1;
+ Current language: auto
+ The current source language is "auto; currently c".
+ (gdb) step
+ 72 DWORD b = 2;
+ (gdb)
+
+ |
+ PASS |
+
+
+
+
+
+ | ID |
+ Target |
+ Interface |
+ Description |
+ Initial state |
+ Input |
+ Expected output |
+ Actual output |
+ Pass/Fail |
+
+
+ | RAM001 |
+ LPC2148 |
+ ZY1000 |
+ 32 bit Write/read RAM |
+ Reset init is working |
+ On the telnet interface
+ > mww ram_address 0xdeadbeef 16
+ > mdw ram_address 32
+
+ |
+ The commands should execute without error. A clear failure is a memory access exception. The result of running the commands should be a list of 16 locations 32bit long containing 0xdeadbeef.
+
+ > mww 0x0 0xdeadbeef 16
+ > mdw 0x0 32
+ 0x00000000: deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef
+ 0x00000020: deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef
+ 0x00000040: e1a00000 e59fa51c e59f051c e04aa000 00080017 00009388 00009388 00009388
+ 0x00000060: 00009388 0002c2c0 0002c2c0 000094f8 000094f4 00009388 00009388 00009388
+
+ |
+
+ > mww 0x40000000 0xdeadbeef 16
+ > mdw 0x40000000 32
+ 0x40000000: deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef
+ 0x40000020: deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef
+ 0x40000040: e1a00000 e1a00000 e1a00000 e1a00000 e1a00000 e1a00000 e1a00000 e1a00000
+ 0x40000060: e321f0db e59fd07c e321f0d7 e59fd078 e321f0d1 e59fd074 e321f0d2 e59fd070
+ >
+ |
+ PASS |
+
+
+ | RAM002 |
+ LPC2148 |
+ ZY1000 |
+ 16 bit Write/read RAM |
+ Reset init is working |
+ On the telnet interface
+ > mwh ram_address 0xbeef 16
+ > mdh ram_address 32
+
+ |
+ The commands should execute without error. A clear failure is a memory access exception. The result of running the commands should be a list of 16 locations 16bit long containing 0xbeef.
+
+ > mwh 0x0 0xbeef 16
+ > mdh 0x0 32
+ 0x00000000: beef beef beef beef beef beef beef beef beef beef beef beef beef beef beef beef
+ 0x00000020: 00e0 0000 021c 0000 0240 0000 026c 0000 0288 0000 0000 0000 0388 0000 0350 0000
+ >
+
+ |
+
+ > mwh 0x40000000 0xbeef 16
+ > mdh 0x40000000 32
+ 0x40000000: beef beef beef beef beef beef beef beef beef beef beef beef beef beef beef beef
+ 0x40000020: beef dead beef dead beef dead beef dead beef dead beef dead beef dead beef dead
+ >
+ |
+ PASS |
+
+
+ | RAM003 |
+ LPC2148 |
+ ZY1000 |
+ 8 bit Write/read RAM |
+ Reset init is working |
+ On the telnet interface
+ > mwb ram_address 0xab 16
+ > mdb ram_address 32
+
+ |
+ The commands should execute without error. A clear failure is a memory access exception. The result of running the commands should be a list of 16 locations 8bit long containing 0xab.
+
+ > mwb ram_address 0xab 16
+ > mdb ram_address 32
+ 0x00000000: ab ab ab ab ab ab ab ab ab ab ab ab ab ab ab ab 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+ >
+
+ |
+
+ > mwb 0x40000000 0xab 16
+ > mdb 0x40000000 32
+ 0x40000000: ab ab ab ab ab ab ab ab ab ab ab ab ab ab ab ab ef be ef be ef be ef be ef be ef be ef be ef be
+ >
+
+ |
+ PASS |
+
+
+
+
+
+
+
+ | ID |
+ Target |
+ Interface |
+ Description |
+ Initial state |
+ Input |
+ Expected output |
+ Actual output |
+ Pass/Fail |
+
+
+ | FLA001 |
+ LPC2148 |
+ ZY1000 |
+ Flash probe |
+ Reset init is working |
+ On the telnet interface:
+ > flash probe 0
+ |
+ The command should execute without error. The output should state the name of the flash and the starting address. An example of output:
+ flash 'ecosflash' found at 0x01000000
+ |
+
+
+ > flash probe 0
+ flash 'lpc2000' found at 0x00000000
+
+ |
+ PASS |
+
+
+ | FLA002 |
+ LPC2148 |
+ ZY1000 |
+ flash fillw |
+ Reset init is working, flash is probed |
+ On the telnet interface
+ > flash fillw 0x1000000 0xdeadbeef 16
+
+ |
+ The commands should execute without error. The output looks like:
+
+ wrote 64 bytes to 0x01000000 in 11.610000s (0.091516 kb/s)
+
+ To verify the contents of the flash:
+
+ > mdw 0x1000000 32
+ 0x01000000: deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef
+ 0x01000020: deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef
+ 0x01000040: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff
+ 0x01000060: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff
+
+ |
+
+ > flash fillw 0x0 0xdeadbeef 16
+ Verification will fail since checksum in image (0xdeadbeef) to be written to flash is different from calculated vector checksum (0xe93fc777).
+ To remove this warning modify build tools on developer PC to inject correct LPC vector checksum.
+ wrote 64 bytes to 0x00000000 in 0.040000s (1.563 kb/s)
+ > mdw 0 32
+ 0x00000000: deadbeef deadbeef deadbeef deadbeef deadbeef e93fc777 deadbeef deadbeef
+ 0x00000020: deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef
+ 0x00000040: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff
+ 0x00000060: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff
+ >
+ |
+ FAIL |
+
+
+ | FLA003 |
+ LPC2148 |
+ ZY1000 |
+ Flash erase |
+ Reset init is working, flash is probed |
+ On the telnet interface
+ > flash erase_address 0x1000000 0x2000
+
+ |
+ The commands should execute without error.
+
+ erased address 0x01000000 length 8192 in 4.970000s
+
+ To check that the flash has been erased, read at different addresses. The result should always be 0xff.
+
+ > mdw 0x1000000 32
+ 0x01000000: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff
+ 0x01000020: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff
+ 0x01000040: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff
+ 0x01000060: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff
+
+ |
+
+ > flash erase_address 0 0x2000
+ erased address 0x00000000 (length 8192) in 0.510000s (15.686 kb/s)
+ > mdw 0 32
+ 0x00000000: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff
+ 0x00000020: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff
+ 0x00000040: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff
+ 0x00000060: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff
+ >
+ |
+ PASS |
+
+
+
+ | FLA004 |
+ LPC2148 |
+ ZY1000 |
+ Loading to flash from GDB |
+ Reset init is working, flash is probed, connectivity to GDB server is working |
+ Start GDB using a ROM elf image, eg: arm-elf-gdb test_rom.elf.
+
+ (gdb) target remote ip:port
+ (gdb) monitor reset
+ (gdb) load
+ Loading section .text, size 0x194 lma 0x100000
+ Start address 0x100040, load size 404
+ Transfer rate: 179 bytes/sec, 404 bytes/write.
+ (gdb) monitor verify_image path_to_elf_file
+
+ |
+ The output should look like:
+
+ verified 404 bytes in 5.060000s
+
+ The failure message is something like:
+ Verify operation failed address 0x00200000. Was 0x00 instead of 0x18
+ |
+
+
+ (gdb) moni verify_image /tftp/10.0.0.194/test_rom.elf
+ checksum mismatch - attempting binary compare
+ Verify operation failed address 0x00000014. Was 0x58 instead of 0x60
+
+ Command handler execution failed
+ in procedure 'verify_image' called at file "command.c", line 647
+ called at file "command.c", line 361
+ (gdb)
+
+ |
+ FAIL |
+
+
+
+
+
\ No newline at end of file