X-Git-Url: https://review.openocd.org/gitweb?p=openocd.git;a=blobdiff_plain;f=tcl%2Ftarget%2Fti_dm6446.cfg;h=fa1e6e957c316cb74552198aa9daacee9fcc5153;hp=4dac3d5fafa43de34e35d6b51e2e3b48d0be70f7;hb=23836fc5be5cc57f04267bee10c451e667c95143;hpb=7280a52e6964d7e5c700670a7ff25cfd8a9d6316

diff --git a/tcl/target/ti_dm6446.cfg b/tcl/target/ti_dm6446.cfg
index 4dac3d5faf..fa1e6e957c 100644
--- a/tcl/target/ti_dm6446.cfg
+++ b/tcl/target/ti_dm6446.cfg
@@ -1,10 +1,10 @@
 #
-# Texas Instruments DaVinci family:  TMS320DM6446
+# Texas Instruments DaVinci family: TMS320DM6446
 #
 if { [info exists CHIPNAME] } {
-   set  _CHIPNAME $CHIPNAME
+   set _CHIPNAME $CHIPNAME
 } else {
-   set  _CHIPNAME dm6446
+   set _CHIPNAME dm6446
 }
 
 # TI boards default to EMU0/EMU1 *high* -- ARM and ETB are *disabled*
@@ -28,7 +28,7 @@ jtag configure $_CHIPNAME.dsp -event tap-enable \
 	"icepick_c_tapenable $_CHIPNAME.jrc 2"
 
 # Subsidiary TAP: ARM ETB11, with scan chain for 4K of ETM trace buffer
-if { [info exists ETB_TAPID ] } {
+if { [info exists ETB_TAPID] } {
    set _ETB_TAPID $ETB_TAPID
 } else {
    set _ETB_TAPID 0x2b900f0f
@@ -38,7 +38,7 @@ jtag configure $_CHIPNAME.etb -event tap-enable \
 	"icepick_c_tapenable $_CHIPNAME.jrc 1"
 
 # Subsidiary TAP: ARM926ejs with scan chains for ARM Debug, EmbeddedICE-RT, ETM.
-if { [info exists CPU_TAPID ] } {
+if { [info exists CPU_TAPID] } {
    set _CPU_TAPID $CPU_TAPID
 } else {
    set _CPU_TAPID 0x07926001
@@ -48,7 +48,7 @@ jtag configure $_CHIPNAME.arm -event tap-enable \
 	"icepick_c_tapenable $_CHIPNAME.jrc 0"
 
 # Primary TAP: ICEpick-C (JTAG route controller) and boundary scan
-if { [info exists JRC_TAPID ] } {
+if { [info exists JRC_TAPID] } {
    set _JRC_TAPID $JRC_TAPID
 } else {
    set _JRC_TAPID 0x0b70002f
@@ -59,7 +59,7 @@ jtag configure $_CHIPNAME.jrc -event setup \
 	"jtag tapenable $_CHIPNAME.etb; jtag tapenable $_CHIPNAME.arm"
 
 ################
-# GDB target:  the ARM, using SRAM1 for scratch.  SRAM0 (also 8K)
+# GDB target: the ARM, using SRAM1 for scratch.  SRAM0 (also 8K)
 # and the ETB memory (4K) are other options, while trace is unused.
 # Little-endian; use the OpenOCD default.
 set _TARGETNAME $_CHIPNAME.arm
@@ -70,8 +70,8 @@ $_TARGETNAME configure -work-area-phys 0x0000a000 -work-area-size 0x2000
 # be absolutely certain the JTAG clock will work with the worst-case
 # CLKIN = 20 MHz (best case: 30 MHz) even when no bootloader turns
 # on the PLL and starts using it.  OK to speed up after clock setup.
-jtag_rclk 1500
-$_TARGETNAME configure -event "reset-start" { jtag_rclk 1500 }
+adapter_khz 1500
+$_TARGETNAME configure -event "reset-start" { adapter_khz 1500 }
 
 arm7_9 fast_memory_access enable
 arm7_9 dcc_downloads enable