X-Git-Url: https://review.openocd.org/gitweb?p=openocd.git;a=blobdiff_plain;f=tcl%2Ftarget%2Fstm32f4x.cfg;h=b5ab200481b0543c3a5cace4a6bb55cec65cc544;hp=16beaa469d19e48b094d2b9e37cee4196156c388;hb=refs%2Fchanges%2F56%2F1856%2F2;hpb=e9976aa3a879ac45dc79a96f6a87cc9fcdf7aaca

diff --git a/tcl/target/stm32f4x.cfg b/tcl/target/stm32f4x.cfg
index 16beaa469d..b5ab200481 100644
--- a/tcl/target/stm32f4x.cfg
+++ b/tcl/target/stm32f4x.cfg
@@ -36,7 +36,7 @@ if { [info exists CPUTAPID] } {
    set _CPUTAPID $CPUTAPID
 } else {
   # See STM Document RM0090
-  # Section 32.6.2 - corresponds to Cortex-M4 r0p1
+  # Section 38.6.3 - corresponds to Cortex-M4 r0p1
    set _CPUTAPID 0x4ba00477
 }
 jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
@@ -45,13 +45,17 @@ if { [info exists BSTAPID] } {
    set _BSTAPID $BSTAPID
 } else {
   # See STM Document RM0090
-  # Section 32.6.3
-  set _BSTAPID 0x06413041
+  # Section 38.6.2
+  # STM32F405xx/07xx and STM32F415xx/17xx
+  set _BSTAPID1 0x06413041
+  # STM32F42xxx and STM32F43xxx
+  set _BSTAPID2 0x06419041
 }
-jtag newtap $_CHIPNAME bs -irlen 5 -expected-id $_BSTAPID
+jtag newtap $_CHIPNAME bs -irlen 5 -expected-id $_BSTAPID1 \
+	-expected-id $_BSTAPID2
 
 set _TARGETNAME $_CHIPNAME.cpu
-target create $_TARGETNAME cortex_m3 -endian $_ENDIAN -chain-position $_TARGETNAME
+target create $_TARGETNAME cortex_m -endian $_ENDIAN -chain-position $_TARGETNAME
 
 $_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
 
@@ -60,4 +64,4 @@ flash bank $_FLASHNAME stm32f2x 0 0 0 0 $_TARGETNAME
 
 # if srst is not fitted use SYSRESETREQ to
 # perform a soft reset
-cortex_m3 reset_config sysresetreq
+cortex_m reset_config sysresetreq