X-Git-Url: https://review.openocd.org/gitweb?p=openocd.git;a=blobdiff_plain;f=tcl%2Ftarget%2Fstellaris.cfg;h=3cab4d1406eaf761950ff8c1fb19001cd0d54312;hp=4235f9106c58eb5ae8615f3718ff752779456ff0;hb=HEAD;hpb=31b47688ca5015bc91fb3480135a9e4efd53586a diff --git a/tcl/target/stellaris.cfg b/tcl/target/stellaris.cfg index 4235f9106c..3cd91eb372 100644 --- a/tcl/target/stellaris.cfg +++ b/tcl/target/stellaris.cfg @@ -1,42 +1,65 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + # TI/Luminary Stellaris LM3S chip family +# Some devices have errata in returning their device class. +# DEVICECLASS is provided as a manual override +# Manual setting of a device class of 0xff is not allowed + +global _DEVICECLASS + +if { [info exists DEVICECLASS] } { + set _DEVICECLASS $DEVICECLASS +} else { + set _DEVICECLASS 0xff +} + +# Luminary chips support both JTAG and SWD transports. +# Adapt based on what transport is active. +source [find target/swj-dp.tcl] + +# For now we ignore the SPI and UART options, which +# are usable only for ISP style initial flash programming. + if { [info exists CHIPNAME] } { - set _CHIPNAME $CHIPNAME + set _CHIPNAME $CHIPNAME } else { - set _CHIPNAME lm3s + set _CHIPNAME lm3s } # CPU TAP ID 0x1ba00477 for early Sandstorm parts # CPU TAP ID 0x2ba00477 for later SandStorm parts, e.g. lm3s811 Rev C2 # CPU TAP ID 0x3ba00477 for Cortex-M3 r1p2 (on Fury, DustDevil) -# CPU TAP ID 0x4ba00477 for Cortex-M3 r2p0 (on Tempest) +# CPU TAP ID 0x4ba00477 for Cortex-M3 r2p0 (on Tempest, Firestorm) +# CPU TAP ID 0x4ba00477 for Cortex-M4 r0p1 (on Blizzard) # ... we'll ignore the JTAG version field, rather than list every # chip revision that turns up. -if { [info exists CPUTAPID ] } { +if { [info exists CPUTAPID] } { set _CPUTAPID $CPUTAPID } else { set _CPUTAPID 0x0ba00477 } -if { [info exists WORKAREASIZE ] } { +# SWD DAP, and JTAG TAP, take same params for now; +# ... even though SWD ignores all except TAPID, and +# JTAG shouldn't need anything more then irlen. (and TAPID). +swj_newdap $_CHIPNAME cpu -irlen 4 -irmask 0xf \ + -expected-id $_CPUTAPID -ignore-version +dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu + +if { [info exists WORKAREASIZE] } { set _WORKAREASIZE $WORKAREASIZE } else { - set _WORKAREASIZE 0x2000 + # default to 2K working area + set _WORKAREASIZE 0x800 } -jtag newtap $_CHIPNAME cpu -irlen 4 -irmask 0xf \ - -expected-id $_CPUTAPID -ignore-version - -# The "lm3s" variant uses a software reset rather than SRST. -# This stops the debug registers from being cleared; it works -# around an erratum which should be fixed in later silicon. set _TARGETNAME $_CHIPNAME.cpu -target create $_TARGETNAME cortex_m3 -chain-position $_CHIPNAME.cpu \ - -variant lm3s +target create $_TARGETNAME cortex_m -dap $_CHIPNAME.dap # 8K working area at base of ram, not backed up # -# NOTE: you may need or want to reconfigure the work area; +# NOTE: you may need or want to reconfigure the work area; # some parts have just 6K, and you may want to use other # addresses (at end of mem not beginning) or back it up. $_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE @@ -44,12 +67,113 @@ $_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE # JTAG speed ... slow enough to work with a 12 MHz RC oscillator; # LM3S parts don't support RTCK # -# NOTE: this may be increased by a reset-init handler, after it +# NOTE: this may be increased by a reset-init handler, after it # configures and enables the PLL. Or you might need to decrease # this, if you're using a slower clock. -adapter_khz 500 -$_TARGETNAME configure -event reset-start {adapter_khz 500} +adapter speed 500 + +source [find mem_helper.tcl] + +proc reset_peripherals {family} { + + source [find chip/ti/lm3s/lm3s.tcl] + + echo "Resetting Core Peripherals" + + # Disable the PLL and the system clock divider (nop if disabled) + mmw $SYSCTL_RCC 0 $SYSCTL_RCC_USESYSDIV + mmw $SYSCTL_RCC2 $SYSCTL_RCC2_BYPASS2 0 + + # RCC and RCC2 to their reset values + mww $SYSCTL_RCC [expr {0x078e3ad0 | ([mrw $SYSCTL_RCC] & $SYSCTL_RCC_MOSCDIS)}] + mww $SYSCTL_RCC2 0x07806810 + mww $SYSCTL_RCC 0x078e3ad1 + + # Reset the deep sleep clock configuration register + mww $SYSCTL_DSLPCLKCFG 0x07800000 + + # Reset the clock gating registers + mww $SYSCTL_RCGC0 0x00000040 + mww $SYSCTL_RCGC1 0 + mww $SYSCTL_RCGC2 0 + mww $SYSCTL_SCGC0 0x00000040 + mww $SYSCTL_SCGC1 0 + mww $SYSCTL_SCGC2 0 + mww $SYSCTL_DCGC0 0x00000040 + mww $SYSCTL_DCGC1 0 + mww $SYSCTL_DCGC2 0 + + # Reset the remaining SysCtl registers + mww $SYSCTL_PBORCTL 0 + mww $SYSCTL_IMC 0 + mww $SYSCTL_GPIOHBCTL 0 + mww $SYSCTL_MOSCCTL 0 + mww $SYSCTL_PIOSCCAL 0 + mww $SYSCTL_I2SMCLKCFG 0 + + # Reset the peripherals + mww $SYSCTL_SRCR0 0xffffffff + mww $SYSCTL_SRCR1 0xffffffff + mww $SYSCTL_SRCR2 0xffffffff + mww $SYSCTL_SRCR0 0 + mww $SYSCTL_SRCR1 0 + mww $SYSCTL_SRCR2 0 + + # Clear any pending SysCtl interrupts + mww $SYSCTL_MISC 0xffffffff + + # Wait for any pending flash operations to complete + while {[expr {[mrw $FLASH_FMC] & 0xffff}] != 0} { sleep 1 } + while {[expr {[mrw $FLASH_FMC2] & 0xffff}] != 0} { sleep 1 } + + # Reset the flash controller registers + mww $FLASH_FMA 0 + mww $FLASH_FCIM 0 + mww $FLASH_FCMISC 0xffffffff + mww $FLASH_FWBVAL 0 +} + +$_TARGETNAME configure -event reset-start { + adapter speed 500 + + # + # When nRST is asserted on most Stellaris devices, it clears some of + # the debug state. The ARMv7M and Cortex-M3 TRMs say that's wrong; + # and OpenOCD depends on those TRMs. So we won't use SRST on those + # chips. (Only power-on reset should affect debug state, beyond a + # few specified bits; not the chip's nRST input, wired to SRST.) + # + # REVISIT current errata specs don't seem to cover this issue. + # Do we have more details than this email? + # https://lists.berlios.de/pipermail + # /openocd-development/2008-August/003065.html + # + + global _DEVICECLASS + + if {$_DEVICECLASS != 0xff} { + set device_class $_DEVICECLASS + } else { + set device_class [expr {([mrw 0x400fe000] >> 16) & 0xff}] + } + + if {$device_class == 0 || $device_class == 1 || + $device_class == 3 || $device_class == 5 || $device_class == 0xa} { + if {![using_hla]} { + # Sandstorm, Fury, DustDevil, Blizzard and Snowflake are able to use NVIC SYSRESETREQ + cortex_m reset_config sysresetreq + } + } else { + if {![using_hla]} { + # Tempest and Firestorm default to using NVIC VECTRESET + # peripherals will need resetting manually, see proc reset_peripherals + cortex_m reset_config vectreset + } + # reset peripherals, based on code in + # http://www.ti.com/lit/er/spmz573a/spmz573a.pdf + reset_peripherals $device_class + } +} # flash configuration ... autodetects sizes, autoprobed flash bank $_CHIPNAME.flash stellaris 0 0 0 0 $_TARGETNAME -