X-Git-Url: https://review.openocd.org/gitweb?p=openocd.git;a=blobdiff_plain;f=tcl%2Ftarget%2Fpxa255.cfg;h=73518bf7e4af5b4bb58522fa85c48034214042e7;hp=44efdaa4b9987f9d2abafae5eace0a20104fafc8;hb=38ac08c1c25adf42cf20e48e10e6ddeab6a12d71;hpb=4a26390eec5b969c07684ab5d4b7e957011d71bd

diff --git a/tcl/target/pxa255.cfg b/tcl/target/pxa255.cfg
index 44efdaa4b9..73518bf7e4 100644
--- a/tcl/target/pxa255.cfg
+++ b/tcl/target/pxa255.cfg
@@ -1,19 +1,19 @@
 # PXA255 chip ... originally from Intel, PXA line was sold to Marvell.
-#  This chip is now at end-of-life.  Final orders have been taken.
+# This chip is now at end-of-life.  Final orders have been taken.
 
 if { [info exists CHIPNAME] } {
-   set  _CHIPNAME $CHIPNAME
+   set _CHIPNAME $CHIPNAME
 } else {
-   set  _CHIPNAME pxa255
+   set _CHIPNAME pxa255
 }
 
 if { [info exists ENDIAN] } {
-   set  _ENDIAN $ENDIAN
+   set _ENDIAN $ENDIAN
 } else {
-   set  _ENDIAN little
+   set _ENDIAN little
 }
 
-if { [info exists CPUTAPID ] } {
+if { [info exists CPUTAPID] } {
    set _CPUTAPID $CPUTAPID
 } else {
    set _CPUTAPID 0x69264013
@@ -28,8 +28,8 @@ target create $_TARGETNAME xscale -endian $_ENDIAN \
 # PXA255 comes out of reset using 3.6864 MHz oscillator.
 # Until the PLL kicks in, keep the JTAG clock slow enough
 # that we get no errors.
-jtag_khz 300
-$_TARGETNAME configure -event "reset-start" { jtag_khz 300 }
+adapter speed 300
+$_TARGETNAME configure -event "reset-start" { adapter speed 300 }
 
 # both TRST and SRST are *required* for debug
 # DCSR is often accessed with SRST active
@@ -38,11 +38,11 @@ reset_config trst_and_srst separate srst_nogate
 # reset processing that works with PXA
 proc init_reset {mode} {
 	# assert both resets; equivalent to power-on reset
-	jtag_reset 1 1
+	adapter assert trst assert srst
 
 	# drop TRST after at least 32 cycles
 	sleep 1
-	jtag_reset 0 1
+	adapter deassert trst assert srst
 
 	# minimum 32 TCK cycles to wake up the controller
 	runtest 50
@@ -51,7 +51,7 @@ proc init_reset {mode} {
 	jtag arp_init
 
 	# ... and take it out of reset
-	jtag_reset 0 0
+	adapter deassert trst deassert srst
 }
 
 proc jtag_init {} {