X-Git-Url: https://review.openocd.org/gitweb?p=openocd.git;a=blobdiff_plain;f=tcl%2Ftarget%2Fpsoc6.cfg;h=fc0c71159b66476be0dab6638015a76481fed878;hp=ad9aba569d20727511b34a78eaaed2a66e98829e;hb=4440bf1fcddce3501781496e2d6a9d0f12cba08d;hpb=2231da8ec4e7d7ae9b652f3dd1a7104f5a110f3f

diff --git a/tcl/target/psoc6.cfg b/tcl/target/psoc6.cfg
index ad9aba569d..fc0c71159b 100644
--- a/tcl/target/psoc6.cfg
+++ b/tcl/target/psoc6.cfg
@@ -82,19 +82,30 @@ proc psoc6_deassert_post { target } {
 	$target arp_examine
 
 	global RESET_MODE
+	global TARGET
+
 	if { $RESET_MODE ne "run" } {
 		$target arp_poll
 		$target arp_poll
 		set st [$target curstate]
+
 		if { $st eq "reset" } {
 			# we assume running state follows
 			# if reset accidentally halts, waiting is useless
 			catch { $target arp_waitstate running 100 }
 			set st [$target curstate]
 		}
+
 		if { $st eq "running" } {
 			echo "$target: Ran after reset and before halt..."
-			$target arp_halt
+			if { $target eq "${TARGET}.cm0" } {
+				# Try to cleanly reset whole system
+				# and halt the CM0 at entry point
+				psoc6 reset_halt
+				$target arp_waitstate halted 100
+			} else {
+				$target arp_halt
+			}
 		}
 	}
 }
@@ -133,3 +144,7 @@ if { $_ENABLE_CM0 } {
 	# Use CM0+ by default on dual-core devices
 	targets ${TARGET}.cm0
 }
+
+if {[using_jtag]} {
+	swj_newdap $_CHIPNAME bs -irlen 18 -expected-id 0x2e200069
+}