X-Git-Url: https://review.openocd.org/gitweb?p=openocd.git;a=blobdiff_plain;f=tcl%2Ftarget%2Fpic32mx.cfg;h=5e64cb84dd654fbd0b73ab0be265bd7b8b4f0672;hp=1561d7303eb5626d404c0de161b6ae9759168087;hb=ca45e700b1c57caca2ef08e665e3c7e3e02ac8d3;hpb=ba96fc3e9de935708cd5fa7c38e547dc7598087d

diff --git a/tcl/target/pic32mx.cfg b/tcl/target/pic32mx.cfg
index 1561d7303e..5e64cb84dd 100644
--- a/tcl/target/pic32mx.cfg
+++ b/tcl/target/pic32mx.cfg
@@ -1,58 +1,77 @@
-
 if { [info exists CHIPNAME] } {
-   set  _CHIPNAME $CHIPNAME
+   set _CHIPNAME $CHIPNAME
 } else {
-   set  _CHIPNAME pic32mx
+   set _CHIPNAME pic32mx
 }
 
 if { [info exists ENDIAN] } {
-   set  _ENDIAN $ENDIAN
+   set _ENDIAN $ENDIAN
 } else {
-   set  _ENDIAN little
+   set _ENDIAN little
 }
 
-if { [info exists CPUTAPID ] } {
+if { [info exists CPUTAPID] } {
    set _CPUTAPID $CPUTAPID
 } else {
-  # force an error till we get a good number
    set _CPUTAPID 0x30938053
 }
 
-jtag_nsrst_delay 100
-jtag_ntrst_delay 100
+# default working area is 16384
+if { [info exists WORKAREASIZE] } {
+   set _WORKAREASIZE $WORKAREASIZE
+} else {
+   set _WORKAREASIZE 0x4000
+}
 
-#use combined on interfaces or targets that can't set TRST/SRST separately
-reset_config srst_only
+adapter_nsrst_delay 100
+jtag_ntrst_delay 100
 
 #jtag scan chain
 #format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
-jtag newtap $_CHIPNAME cpu -irlen 5  -ircapture 0x1 -irmask 0x1f -expected-id $_CPUTAPID
+jtag newtap $_CHIPNAME cpu -irlen 5 -ircapture 0x1 -irmask 0x1f -expected-id $_CPUTAPID
 
 set _TARGETNAME $_CHIPNAME.cpu
 target create $_TARGETNAME mips_m4k -endian $_ENDIAN -chain-position $_TARGETNAME
 
-$_TARGETNAME configure -work-area-phys 0xa0000800 -work-area-size 16384 -work-area-backup 0
+#
+# At reset the pic32mx does not allow code execution from RAM
+# we have to setup the BMX registers to allow this.
+# One limitation is that we loose the first 2k of RAM.
+#
+
+global _PIC32MX_DATASIZE
+global _PIC32MX_PROGSIZE
+set _PIC32MX_DATASIZE 0x800
+set _PIC32MX_PROGSIZE [expr ($_WORKAREASIZE - $_PIC32MX_DATASIZE)]
 
+$_TARGETNAME configure -work-area-phys 0xa0000800 -work-area-size $_PIC32MX_PROGSIZE -work-area-backup 0
 $_TARGETNAME configure -event reset-init {
 	#
 	# from reset the pic32 cannot execute code in ram - enable ram execution
 	# minimum offset from start of ram is 2k
 	#
 
+	global _PIC32MX_DATASIZE
+	global _PIC32MX_PROGSIZE
+
 	# BMXCON
 	mww 0xbf882000 0x001f0040
-	# BMXDKPBA: 0xa0000800
-	mww 0xbf882010 0x00000800
-	# BMXDUDBA
-	mww 0xbf882020 0x00004000
-	# BMXDUPBA
-	mww 0xbf882030 0x00004000
+	# BMXDKPBA: 2k kernel data @ 0xa0000800
+	mww 0xbf882010 $_PIC32MX_DATASIZE
+	# BMXDUDBA: 16k kernel program @ 0xa0000800
+	mww 0xbf882020 $_PIC32MX_PROGSIZE
+	# BMXDUPBA: 0k user program
+	mww 0xbf882030 $_PIC32MX_PROGSIZE
 }
 
-set _FLASHNAME $_CHIPNAME.flash
-flash bank $_FLASHNAME pic32mx 0xbd000000 0 0 0 $_TARGETNAME
-set _FLASHNAME $_CHIPNAME.flash
-flash bank $_FLASHNAME pic32mx 0xbfc00000 0 0 0 $_TARGETNAME
+set _FLASHNAME $_CHIPNAME.flash0
+flash bank $_FLASHNAME pic32mx 0x1fc00000 0 0 0 $_TARGETNAME
+# add virtual banks for kseg0 and kseg1
+flash bank vbank0 virtual 0xbfc00000 0 0 0 $_TARGETNAME $_FLASHNAME
+flash bank vbank1 virtual 0x9fc00000 0 0 0 $_TARGETNAME $_FLASHNAME
 
-# For more information about the configuration files, take a look at:
-# openocd.texi
+set _FLASHNAME $_CHIPNAME.flash1
+flash bank $_FLASHNAME pic32mx 0x1d000000 0 0 0 $_TARGETNAME
+# add virtual banks for kseg0 and kseg1
+flash bank vbank2 virtual 0xbd000000 0 0 0 $_TARGETNAME $_FLASHNAME
+flash bank vbank3 virtual 0x9d000000 0 0 0 $_TARGETNAME $_FLASHNAME