X-Git-Url: https://review.openocd.org/gitweb?p=openocd.git;a=blobdiff_plain;f=tcl%2Ftarget%2Fpic32mx.cfg;h=202668b88ae57a5ed317f9b9b9fbe104e54c66cc;hp=a346c471c3128085fb56e2c7827f4e1f8eab14ce;hb=3f9d377ce788365844f9225064cb9b0f0b4542ef;hpb=2dfa5e9c844a5a3f8aaca146c874f13570b8f667

diff --git a/tcl/target/pic32mx.cfg b/tcl/target/pic32mx.cfg
index a346c471c3..202668b88a 100644
--- a/tcl/target/pic32mx.cfg
+++ b/tcl/target/pic32mx.cfg
@@ -14,29 +14,70 @@ if { [info exists ENDIAN] } {
 if { [info exists CPUTAPID ] } {
    set _CPUTAPID $CPUTAPID
 } else {
-  # force an error till we get a good number
+   # force an error till we get a good number
    set _CPUTAPID 0x30938053
 }
 
-jtag_nsrst_delay 100
-jtag_ntrst_delay 100
+# default working area is 16384
+if { [info exists WORKAREASIZE] } {
+   set  _WORKAREASIZE $WORKAREASIZE
+} else {
+   set  _WORKAREASIZE 0x4000
+}
 
-#use combined on interfaces or targets that can't set TRST/SRST separately
-reset_config srst_only
+
+adapter_nsrst_delay 100
+jtag_ntrst_delay 100
 
 #jtag scan chain
 #format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
-jtag newtap $_CHIPNAME cpu -irlen 5  -ircapture 0x1 -irmask 0x1f -expected-id $_CPUTAPID
+jtag newtap $_CHIPNAME cpu -irlen 5 -ircapture 0x1 -irmask 0x1f -expected-id $_CPUTAPID
 
 set _TARGETNAME $_CHIPNAME.cpu
 target create $_TARGETNAME mips_m4k -endian $_ENDIAN -chain-position $_TARGETNAME
 
-$_TARGETNAME configure -work-area-phys 0xa0000000 -work-area-size 16384 -work-area-backup 0
+#
+# At reset the pic32mx does not allow code execution from RAM
+# we have to setup the BMX registers to allow this.
+# One limitation is that we loose the first 2k of RAM.
+#
+
+global _PIC32MX_DATASIZE
+global _PIC32MX_PROGSIZE
+set _PIC32MX_DATASIZE 0x800
+set _PIC32MX_PROGSIZE [expr ($_WORKAREASIZE - $_PIC32MX_DATASIZE)]
+
+$_TARGETNAME configure -work-area-phys 0xa0000800 -work-area-size $_PIC32MX_PROGSIZE -work-area-backup 0
+$_TARGETNAME configure -event reset-init {
+	#
+	# from reset the pic32 cannot execute code in ram - enable ram execution
+	# minimum offset from start of ram is 2k
+	#
+
+	global _PIC32MX_DATASIZE
+	global _PIC32MX_PROGSIZE
+
+	# BMXCON
+	mww 0xbf882000 0x001f0040
+	# BMXDKPBA: 2k kernel data @ 0xa0000800
+	mww 0xbf882010 $_PIC32MX_DATASIZE
+	# BMXDUDBA: 16k kernel program @ 0xa0000800
+	mww 0xbf882020 $_PIC32MX_PROGSIZE
+	# BMXDUPBA: 0k user program
+	mww 0xbf882030 $_PIC32MX_PROGSIZE
+}
+
+set _FLASHNAME $_CHIPNAME.flash0
+flash bank $_FLASHNAME pic32mx 0x1fc00000 0 0 0 $_TARGETNAME
+# add virtual banks for kseg0 and kseg1
+flash bank vbank0 virtual 0xbfc00000 0 0 0 $_TARGETNAME $_FLASHNAME
+flash bank vbank1 virtual 0x9fc00000 0 0 0 $_TARGETNAME $_FLASHNAME
 
-set _FLASHNAME $_CHIPNAME.flash
-flash bank $_FLASHNAME pic32mx 0xbd000000 0 0 0 0
-set _FLASHNAME $_CHIPNAME.flash
-flash bank $_FLASHNAME pic32mx 0xbfc00000 0 0 0 0
+set _FLASHNAME $_CHIPNAME.flash1
+flash bank $_FLASHNAME pic32mx 0x1d000000 0 0 0 $_TARGETNAME
+# add virtual banks for kseg0 and kseg1
+flash bank vbank2 virtual 0xbd000000 0 0 0 $_TARGETNAME $_FLASHNAME
+flash bank vbank3 virtual 0x9d000000 0 0 0 $_TARGETNAME $_FLASHNAME
 
 # For more information about the configuration files, take a look at:
 # openocd.texi