X-Git-Url: https://review.openocd.org/gitweb?p=openocd.git;a=blobdiff_plain;f=tcl%2Ftarget%2Fomap3530.cfg;h=74edd7289fbdf8b5f89cad2fc4e92c04bf58305b;hp=84460705d173ac19f36711170de9caca56cda980;hb=ddce517e3a2144e27a26090aef7ef1a7f2270af1;hpb=f87985b61447115632721e18a04623464331c09b

diff --git a/tcl/target/omap3530.cfg b/tcl/target/omap3530.cfg
index 84460705d1..74edd7289f 100644
--- a/tcl/target/omap3530.cfg
+++ b/tcl/target/omap3530.cfg
@@ -34,28 +34,41 @@ if { [info exists JRC_TAPID ] } {
 jtag newtap $_CHIPNAME jrc -irlen 6 -ircapture 0x1 -irmask 0x3f \
 	-expected-id $_JRC_TAPID
 
-jtag configure $_CHIPNAME.jrc -event post-reset "runtest 100"
-
 # GDB target:  Cortex-A8, using DAP
-target create omap3.cpu cortex_a8 -chain-position $_CHIPNAME.dap
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME cortex_a8 -chain-position $_CHIPNAME.dap
+
+# SRAM: 64K at 0x4020.0000; use the first 16K
+$_TARGETNAME configure -work-area-phys 0x40200000 -work-area-size 0x4000
+
+###################
+
+# the reset sequence is event-driven
+# and kind of finicky...
 
-# FIXME much of this should be in reset event handlers
-proc omap3_dbginit { } {
-     poll off
-     sleep 100
+# some TCK tycles are required to activate the DEBUG power domain
+jtag configure $_CHIPNAME.jrc -event post-reset "runtest 100"
+
+# have the DAP "always" be active
+jtag configure $_CHIPNAME.jrc -event setup "jtag tapenable $_CHIPNAME.dap"
 
-     jtag tapenable omap3530.dap
-     targets
+proc omap3_dbginit {target} {
      # General Cortex A8 debug initialisation
      cortex_a8 dbginit
      # Enable DBGU signal for OMAP353x
-     omap3.cpu mww 0x5401d030 0x00002000
-     poll on
+     $target mww 0x5401d030 0x00002000
 }
 
-set PRM_RSTCTRL 0x48307250
-
-omap3.cpu configure -event reset-start "omap3.cpu mww $PRM_RSTCTRL 2"
-omap3.cpu configure -event reset-assert-pre "omap3_dbginit"
+# be absolutely certain the JTAG clock will work with the worst-case
+# 16.8MHz/2 = 8.4MHz core clock, even before a bootloader kicks in.
+# OK to speed up *after* PLL and clock tree setup.
+jtag_rclk 1000
+$_TARGETNAME configure -event "reset-start" { jtag_rclk 1000 }
 
+# Assume SRST is unavailable (e.g. TI-14 JTAG), so we must assert reset
+# ourselves using PRM_RSTCTRL.  RST_GS (2) is a warm reset, like ICEpick
+# would issue.  RST_DPLL3 (4) is a cold reset.
+set PRM_RSTCTRL 0x48307250
+$_TARGETNAME configure -event reset-assert "$_TARGETNAME mww $PRM_RSTCTRL 2"
 
+$_TARGETNAME configure -event reset-assert-post "omap3_dbginit $_TARGETNAME"