X-Git-Url: https://review.openocd.org/gitweb?p=openocd.git;a=blobdiff_plain;f=tcl%2Ftarget%2Fomap3530.cfg;h=078d7f24db97b3a431e8a7d8ba8b226bca019d3a;hp=3c7dd9cfe17c46046235501facee1231e808412f;hb=HEAD;hpb=7b3be0e21ec2065f77c1541b09e049b733361486

diff --git a/tcl/target/omap3530.cfg b/tcl/target/omap3530.cfg
index 3c7dd9cfe1..bd8b111a0b 100644
--- a/tcl/target/omap3530.cfg
+++ b/tcl/target/omap3530.cfg
@@ -1,11 +1,13 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 # TI OMAP3530
-#  http://focus.ti.com/docs/prod/folders/print/omap3530.html
+# http://focus.ti.com/docs/prod/folders/print/omap3530.html
 # Other OMAP3 chips remove DSP and/or the OpenGL support
 
-if { [info exists CHIPNAME] } {	
-   set  _CHIPNAME $CHIPNAME    
-} else {	 
-   set  _CHIPNAME omap3530
+if { [info exists CHIPNAME] } {
+   set _CHIPNAME $CHIPNAME
+} else {
+   set _CHIPNAME omap3530
 }
 
 # ICEpick-C ... used to route Cortex, DSP, and more not shown here
@@ -15,18 +17,18 @@ source [find target/icepick.cfg]
 jtag newtap $_CHIPNAME dsp -irlen 38 -ircapture 0x25 -irmask 0x3f -disable
 
 # Subsidiary TAP: CoreSight Debug Access Port (DAP)
-if { [info exists DAP_TAPID ] } {
+if { [info exists DAP_TAPID] } {
    set _DAP_TAPID $DAP_TAPID
 } else {
    set _DAP_TAPID 0x0b6d602f
 }
-jtag newtap $_CHIPNAME dap -irlen 4 -ircapture 0x1 -irmask 0xf \
+jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf \
 	-expected-id $_DAP_TAPID -disable
-jtag configure $_CHIPNAME.dap -event tap-enable \
+jtag configure $_CHIPNAME.cpu -event tap-enable \
 	"icepick_c_tapenable $_CHIPNAME.jrc 3"
 
 # Primary TAP: ICEpick-C (JTAG route controller) and boundary scan
-if { [info exists JRC_TAPID ] } {
+if { [info exists JRC_TAPID] } {
    set _JRC_TAPID $JRC_TAPID
 } else {
    set _JRC_TAPID 0x0b7ae02f
@@ -34,22 +36,42 @@ if { [info exists JRC_TAPID ] } {
 jtag newtap $_CHIPNAME jrc -irlen 6 -ircapture 0x1 -irmask 0x3f \
 	-expected-id $_JRC_TAPID
 
+# GDB target: Cortex-A8, using DAP
+set _TARGETNAME $_CHIPNAME.cpu
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
+target create $_TARGETNAME cortex_a -dap $_CHIPNAME.dap
+
+# SRAM: 64K at 0x4020.0000; use the first 16K
+$_TARGETNAME configure -work-area-phys 0x40200000 -work-area-size 0x4000
+
+###################
+
+# the reset sequence is event-driven
+# and kind of finicky...
+
+# some TCK tycles are required to activate the DEBUG power domain
 jtag configure $_CHIPNAME.jrc -event post-reset "runtest 100"
 
-# GDB target:  Cortex-A8, using DAP
-target create omap3.cpu cortex_a8 -chain-position $_CHIPNAME.dap
-
-# FIXME much of this should be in reset event handlers
-proc omap3_dbginit { } {
-     poll off
-     reset
-     sleep 500
-
-     jtag tapenable omap3530.dap
-     targets
-     # General Cortex A8 debug initialisation
-     cortex_a8 dbginit
-     # Enable DBGU singal for OMAP353x
-     omap3.cpu mww 0x5401d030 0x00002000
-     poll on
+# have the DAP "always" be active
+jtag configure $_CHIPNAME.jrc -event setup "jtag tapenable $_CHIPNAME.dap"
+
+proc omap3_dbginit {target} {
+     # General Cortex-A8 debug initialisation
+     cortex_a dbginit
+     # Enable DBGU signal for OMAP353x
+     $target mww phys 0x5401d030 0x00002000
 }
+
+# be absolutely certain the JTAG clock will work with the worst-case
+# 16.8MHz/2 = 8.4MHz core clock, even before a bootloader kicks in.
+# OK to speed up *after* PLL and clock tree setup.
+adapter speed 1000
+$_TARGETNAME configure -event "reset-start" { adapter speed 1000 }
+
+# Assume SRST is unavailable (e.g. TI-14 JTAG), so we must assert reset
+# ourselves using PRM_RSTCTRL.  RST_GS (2) is a warm reset, like ICEpick
+# would issue.  RST_DPLL3 (4) is a cold reset.
+set PRM_RSTCTRL 0x48307250
+$_TARGETNAME configure -event reset-assert "$_TARGETNAME mww $PRM_RSTCTRL 2"
+
+$_TARGETNAME configure -event reset-assert-post "omap3_dbginit $_TARGETNAME"