X-Git-Url: https://review.openocd.org/gitweb?p=openocd.git;a=blobdiff_plain;f=tcl%2Ftarget%2Fomap2420.cfg;h=86b0a80db2eafa90e15705af2edf48b252a3ec8a;hp=01557491f9f934f7a96f43a3eda0c75c6ecd6a0a;hb=3f9d377ce788365844f9225064cb9b0f0b4542ef;hpb=f1f54a0fc56b8025692b1ce60e0cc588c975e397

diff --git a/tcl/target/omap2420.cfg b/tcl/target/omap2420.cfg
index 01557491f9..86b0a80db2 100644
--- a/tcl/target/omap2420.cfg
+++ b/tcl/target/omap2420.cfg
@@ -1,24 +1,21 @@
 # Texas Instruments OMAP 2420
 #	http://www.ti.com/omap
+# as seen in Nokia N8x0 tablets
 
 if { [info exists CHIPNAME] } {
    set  _CHIPNAME $CHIPNAME
 } else {
    set  _CHIPNAME omap2420
 }
-if { [info exists ENDIAN] } {
-   set  _ENDIAN $ENDIAN
-} else {
-   set  _ENDIAN little
-}
 
 # NOTE: likes slowish clock on reset (1.5 MBit/s or less) or use RCLK
+reset_config srst_nogate
 
 # Subsidiary TAP:  ARM7TDMIr4 plus imaging ... must add via ICEpick (addr 6).
-jtag newtap $_CHIPNAME iva -irlen 4 -ircapture 0x1 -irmask 0x3f -disable
+jtag newtap $_CHIPNAME iva -irlen 4 -disable
 
 # Subsidiary TAP: C55x DSP ... must add via ICEpick (addr 2).
-jtag newtap $_CHIPNAME dsp -irlen 38 -ircapture 0x1 -irmask 0x3f -disable
+jtag newtap $_CHIPNAME dsp -irlen 38 -disable
 
 # Subsidiary TAP: ARM ETB11, with scan chain for 4K of ETM trace buffer
 if { [info exists ETB_TAPID ] } {
@@ -26,7 +23,7 @@ if { [info exists ETB_TAPID ] } {
 } else {
    set _ETB_TAPID 0x2b900f0f
 }
-jtag newtap $_CHIPNAME etb -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_ETB_TAPID
+jtag newtap $_CHIPNAME etb -irlen 4 -expected-id $_ETB_TAPID
 
 # Subsidiary TAP: ARM1136jf-s with scan chains for ARM Debug, EmbeddedICE-RT, ETM.
 if { [info exists CPU_TAPID ] } {
@@ -34,7 +31,7 @@ if { [info exists CPU_TAPID ] } {
 } else {
    set _CPU_TAPID 0x07b3602f
 }
-jtag newtap $_CHIPNAME arm -irlen 5 -ircapture 0x1 -irmask 0x1f -expected-id $_CPU_TAPID
+jtag newtap $_CHIPNAME arm -irlen 5 -expected-id $_CPU_TAPID
 
 # Primary TAP: ICEpick-B (JTAG route controller) and boundary scan
 if { [info exists JRC_TAPID ] } {
@@ -42,18 +39,23 @@ if { [info exists JRC_TAPID ] } {
 } else {
    set _JRC_TAPID 0x01ce4801
 }
-jtag newtap $_CHIPNAME jrc -irlen 2 -ircapture 0x1 -irmask 0x3 -expected-id $_JRC_TAPID
+jtag newtap $_CHIPNAME jrc -irlen 2 -expected-id $_JRC_TAPID
 
 # GDB target:  the ARM.
 set _TARGETNAME $_CHIPNAME.arm
-target create $_TARGETNAME arm11 -endian $_ENDIAN -chain-position $_TARGETNAME
+target create $_TARGETNAME arm11 -chain-position $_TARGETNAME
 
 # scratch:  framebuffer, may be initially unavailable in some chips
 $_TARGETNAME configure -work-area-phys 0x40210000
 $_TARGETNAME configure -work-area-size 0x00081000
 $_TARGETNAME configure -work-area-backup 0
 
-# trace setup
-# REVISIT ... as of 12-June-2009, OpenOCD's ETM code can't talk to ARM11 cores.
-#etm config $_TARGETNAME 16 normal full etb
-#etb config $_TARGETNAME $_CHIPNAME.etb
+# trace setup ... NOTE, "normal full" mode fudges the real ETMv3.1 mode
+etm config $_TARGETNAME 16 normal full etb
+etb config $_TARGETNAME $_CHIPNAME.etb
+
+# RM_RSTCTRL_WKUP.RST.GS - Trigger a global software reset, and
+# give it a chance to finish before we talk to the chip again.
+set RM_RSTCTRL_WKUP 0x48008450
+$_TARGETNAME configure -event reset-assert \
+	"halt; $_TARGETNAME mww $RM_RSTCTRL_WKUP 2; sleep 200"