X-Git-Url: https://review.openocd.org/gitweb?p=openocd.git;a=blobdiff_plain;f=tcl%2Ftarget%2Fnrf51.cfg;h=280dd4ff365609d56cddc62a82d565bf817f1e8f;hp=abb46fddaff974b91ed571dac84f48e24e4097b4;hb=bcaf775fc10d88d2c63c06bafada141895318b34;hpb=c7384117c66e8f18896ca09ab8095d6da16bb1e5

diff --git a/tcl/target/nrf51.cfg b/tcl/target/nrf51.cfg
index abb46fddaf..280dd4ff36 100644
--- a/tcl/target/nrf51.cfg
+++ b/tcl/target/nrf51.cfg
@@ -1,5 +1,5 @@
 #
-# script for Nordic nRF51 series, a CORTEX-M0 chip
+# script for Nordic nRF51 series, a Cortex-M0 chip
 #
 
 source [find target/swj-dp.tcl]
@@ -17,11 +17,11 @@ if { [info exists ENDIAN] } {
 }
 
 # Work-area is a space in RAM used for flash programming
-# By default use 2kB
+# By default use 16kB
 if { [info exists WORKAREASIZE] } {
    set _WORKAREASIZE $WORKAREASIZE
 } else {
-   set _WORKAREASIZE 0x800
+   set _WORKAREASIZE 0x4000
 }
 
 if { [info exists CPUTAPID] } {
@@ -50,3 +50,11 @@ flash bank $_CHIPNAME.uicr nrf51 0x10001000 0 1 1 $_TARGETNAME
 #  clock to 1Mhz should be OK
 #
 adapter_khz 1000
+
+proc enable_all_ram {} {
+	# nRF51822 Product Anomaly Notice (PAN) #16 explains that not all RAM banks
+	# are reliably enabled after reset on some revisions (contrary to spec.) So after
+	# resetting we enable all banks via the RAMON register
+	mww 0x40000524 0xF
+}
+$_TARGETNAME configure -event reset-end {  enable_all_ram }