X-Git-Url: https://review.openocd.org/gitweb?p=openocd.git;a=blobdiff_plain;f=tcl%2Ftarget%2Flpc2478.cfg;h=36b5c46936fd32811f2d5c4b958c8ed7d0c51d3c;hp=950ef63fd5ba8bdc3ff8f2b47b5a753ea3413892;hb=HEAD;hpb=b559b273b526b3077b3ca219eecc8df9f86efac0

diff --git a/tcl/target/lpc2478.cfg b/tcl/target/lpc2478.cfg
index 950ef63fd5..e4fd49d43b 100644
--- a/tcl/target/lpc2478.cfg
+++ b/tcl/target/lpc2478.cfg
@@ -1,50 +1,23 @@
-# NXP LPC2478 ARM7TDMI-S with 512kB Flash and 64kB Local On-Chip SRAM (98kB total), clocked with 4MHz internal RC oscillator
+# SPDX-License-Identifier: GPL-2.0-or-later
 
-if { [info exists CHIPNAME] } {
-	set  _CHIPNAME $CHIPNAME
-} else {
-	set  _CHIPNAME lpc2478
-}
-
-if { [info exists ENDIAN] } {
-	set  _ENDIAN $ENDIAN
-} else {
-	set  _ENDIAN little
-}
-
-if { [info exists CPUTAPID ] } {
-	set _CPUTAPID $CPUTAPID
-} else {
-	set _CPUTAPID 0x4f1f0f0f
-}
+# NXP LPC2478 ARM7TDMI-S with 512kB flash (8kB used by bootloader) and 98kB SRAM (16kB for ETH, 16kB for DMA, 2kB for RTC), clocked with 4MHz internal oscillator
 
-#delays on reset lines
-adapter_nsrst_delay 100
-jtag_ntrst_delay 100
+source [find target/lpc2xxx.cfg]
 
-# LPC2000 -> SRST causes TRST
-reset_config trst_and_srst srst_pulls_trst
+# parameters:
+# - core_freq_khz - frequency of core in kHz during flashing, usually equal to connected crystal or internal oscillator, e.g. 12000
+# - adapter_freq_khz - frequency of debug adapter in kHz, should be 8x slower than core_freq_khz, e.g. 1000
 
-jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
-
-set _TARGETNAME $_CHIPNAME.cpu
-target create $_TARGETNAME arm7tdmi -endian $_ENDIAN -chain-position $_TARGETNAME -variant arm7tdmi-s_r4
-
-# LPC2478 has 64kB of SRAM on its main system bus (so-called Local On-Chip SRAM)
-$_TARGETNAME configure -work-area-phys 0x40000000 -work-area-size 0x10000 -work-area-backup 0
-
-$_TARGETNAME configure -event reset-init {
-	# Force target into ARM state
-	arm core_state arm
-	# Do not remap 0x0000-0x0020 to anything but the Flash
-	mwb 0xE01FC040 0x01
+proc setup_lpc2478 {core_freq_khz adapter_freq_khz} {
+	# 504kB flash and 64kB SRAM
+	# setup_lpc2xxx <chip_name> <cputapid> <flash_size> <flash_variant> <workarea_size> <core_freq_khz> <adapter_freq_khz>
+	setup_lpc2xxx lpc2478 0x4f1f0f0f 0x7e000 lpc2000_v2 0x10000 $core_freq_khz $adapter_freq_khz
 }
 
-# LPC2378 has 512kB of FLASH, but upper 8kB are occupied by bootloader.
-# After reset the chip uses its internal 4MHz RC oscillator.
-# flash bank lpc2000 <base> <size> 0 0 <target#> <variant> <clock> [calc checksum]
-set _FLASHNAME $_CHIPNAME.flash
-flash bank $_FLASHNAME lpc2000 0x0 0x7D000 0 0 $_TARGETNAME lpc2000_v2 12000 calc_checksum
+proc init_targets {} {
+	# default to core clocked with 4MHz internal oscillator
+	echo "Warning - assuming default core clock 4MHz! Flashing may fail if actual core clock is different."
 
-# Try to use RCLK, if RCLK is not available use "normal" mode. 4MHz / 6 = 666kHz, so use 500.
-jtag_rclk 500
+	# setup_lpc2478 <core_freq_khz> <adapter_freq_khz>
+	setup_lpc2478 4000 500
+}