X-Git-Url: https://review.openocd.org/gitweb?p=openocd.git;a=blobdiff_plain;f=tcl%2Ftarget%2Flpc17xx.cfg;h=01a8cd3785e8e33c3fcd735d337759e5ff4e4052;hp=a64783dab2e75edb6119b5552eb7a8dc5785be71;hb=b7d2cdc0d4fc319169c60362708a67e2ff626525;hpb=564a5eb5375aa8117ee4fe48899f07490da8ae8a

diff --git a/tcl/target/lpc17xx.cfg b/tcl/target/lpc17xx.cfg
index a64783dab2..01a8cd3785 100644
--- a/tcl/target/lpc17xx.cfg
+++ b/tcl/target/lpc17xx.cfg
@@ -57,7 +57,7 @@ jtag_ntrst_delay 200
 swj_newdap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUTAPID
 
 set _TARGETNAME $_CHIPNAME.cpu
-target create $_TARGETNAME cortex_m3 -chain-position $_TARGETNAME
+target create $_TARGETNAME cortex_m -chain-position $_TARGETNAME
 
 # The LPC17xx devices have 8/16/32kB of SRAM In the ARMv7-M "Code" area (at 0x10000000)
 $_TARGETNAME configure -work-area-phys 0x10000000 -work-area-size $_CPURAMSIZE
@@ -94,4 +94,4 @@ $_TARGETNAME configure -event reset-init {
 
 # if srst is not fitted use VECTRESET to
 # perform a soft reset - SYSRESETREQ is not supported
-cortex_m3 reset_config vectreset
+cortex_m reset_config vectreset