X-Git-Url: https://review.openocd.org/gitweb?p=openocd.git;a=blobdiff_plain;f=tcl%2Ftarget%2Fimx6.cfg;h=f359346d7aa02d55d62d8939b8bf847c71f78efb;hp=4f7e98afd033e82b7649af714e80c23b48f70d8b;hb=23836fc5be5cc57f04267bee10c451e667c95143;hpb=0c8ec7c826c60391034fe5f0ea90f8538ac94b38

diff --git a/tcl/target/imx6.cfg b/tcl/target/imx6.cfg
index 4f7e98afd0..f359346d7a 100644
--- a/tcl/target/imx6.cfg
+++ b/tcl/target/imx6.cfg
@@ -1,4 +1,10 @@
-# Freescale i.MX6 series single/dual/quad core processor
+#
+# Freescale i.MX6 series
+#
+# Supports 6Q 6D 6QP 6DP 6DL 6S 6SL 6SLL
+#
+# Some imx6 chips have Cortex-A7 or an Cortex-M and need special handling
+#
 
 if { [info exists CHIPNAME] } {
    set  _CHIPNAME $CHIPNAME
@@ -8,30 +14,46 @@ if { [info exists CHIPNAME] } {
 
 # CoreSight Debug Access Port
 if { [info exists DAP_TAPID] } {
-        set _DAP_TAPID $DAP_TAPID
+    set _DAP_TAPID $DAP_TAPID
 } else {
-        set _DAP_TAPID 0x4ba00477
+    set _DAP_TAPID 0x4ba00477
 }
 
-jtag newtap $_CHIPNAME dap -irlen 4 -ircapture 0x01 -irmask 0x0f \
+jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x01 -irmask 0x0f \
         -expected-id $_DAP_TAPID
 
 # SDMA / no IDCODE
 jtag newtap $_CHIPNAME sdma -irlen 4 -ircapture 0x00 -irmask 0x0f
 
 # System JTAG Controller
+
+# List supported SJC TAPIDs from imx reference manuals:
+set _SJC_TAPID_6Q   0x0191c01d
+set _SJC_TAPID_6D   0x0191e01d
+set _SJC_TAPID_6QP  0x3191c01d
+set _SJC_TAPID_6DP  0x3191d01d
+set _SJC_TAPID_6DL  0x0891a01d
+set _SJC_TAPID_6S   0x0891b01d
+set _SJC_TAPID_6SL  0x0891f01d
+set _SJC_TAPID_6SLL 0x088c201d
+
+# Allow external override of the first SJC TAPID
 if { [info exists SJC_TAPID] } {
-        set _SJC_TAPID $SJC_TAPID
+    set _SJC_TAPID $SJC_TAPID
 } else {
-        set _SJC_TAPID 0x0191c01d
+    set _SJC_TAPID $_SJC_TAPID_6Q
 }
-set _SJC_TAPID2 0x2191c01d
-set _SJC_TAPID3 0x2191e01d
-set _SJC_TAPID4 0x1191c01d
 
 jtag newtap $_CHIPNAME sjc -irlen 5 -ircapture 0x01 -irmask 0x1f \
-        -expected-id $_SJC_TAPID -expected-id $_SJC_TAPID2 \
-        -expected-id $_SJC_TAPID3 -expected-id $_SJC_TAPID4
+        -ignore-version \
+        -expected-id $_SJC_TAPID \
+        -expected-id $_SJC_TAPID_6QP \
+        -expected-id $_SJC_TAPID_6DP \
+        -expected-id $_SJC_TAPID_6D \
+        -expected-id $_SJC_TAPID_6DL \
+        -expected-id $_SJC_TAPID_6S \
+        -expected-id $_SJC_TAPID_6SL \
+        -expected-id $_SJC_TAPID_6SLL
 
 # GDB target: Cortex-A9, using DAP, configuring only one core
 # Base addresses of cores:
@@ -40,7 +62,8 @@ jtag newtap $_CHIPNAME sjc -irlen 5 -ircapture 0x01 -irmask 0x1f \
 # core 2  -  0x82154000
 # core 3  -  0x82156000
 set _TARGETNAME $_CHIPNAME.cpu.0
-target create $_TARGETNAME cortex_a -chain-position $_CHIPNAME.dap \
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
+target create $_TARGETNAME cortex_a -dap $_CHIPNAME.dap \
         -coreid 0 -dbgbase 0x82150000
 
 # some TCK cycles are required to activate the DEBUG power domain
@@ -56,4 +79,3 @@ adapter_khz 1000
 $_TARGETNAME configure -event reset-start { adapter_khz 1000 }
 
 $_TARGETNAME configure -event reset-assert-post "imx6_dbginit $_TARGETNAME"
-$_TARGETNAME configure -event gdb-attach { halt }