X-Git-Url: https://review.openocd.org/gitweb?p=openocd.git;a=blobdiff_plain;f=tcl%2Ftarget%2Ficepick.cfg;h=a945bea8a155e324487dc8aaa8df7142bb3b962f;hp=13a6a5106b8a68930ef1a7c4dad73670c912e3b8;hb=5fd1cb0e5b4ec60d34109febac25443a9394b8f1;hpb=3201a104fe198fc40f515a99ea56621f90302e2b

diff --git a/tcl/target/icepick.cfg b/tcl/target/icepick.cfg
index 13a6a5106b..a945bea8a1 100644
--- a/tcl/target/icepick.cfg
+++ b/tcl/target/icepick.cfg
@@ -63,7 +63,8 @@ proc icepick_c_router {jrc rw block register payload} {
 	irscan $jrc [CONST IR_ROUTER] -endstate IRPAUSE
 
 	# ROUTER instructions are 32 bits wide
-	set old_dr_value [drscan $jrc 32 $new_dr_value -endstate DRPAUSE]
+	set old_dr_value 0x[drscan $jrc 32 $new_dr_value -endstate DRPAUSE]
+#	echo "\tOld router value:\t0x[format %x $old_dr_value]"
 }
 
 # Configure the icepick control register
@@ -89,39 +90,44 @@ proc icepick_c_tapenable {jrc port} {
 	# And never to enter RESET, which will disable the TAPs.
 
 	# first enable power and clock for TAP
-	icepick_c_router $jrc 1 0x2 $port 0x100048
+	icepick_c_router $jrc 1 0x2 $port 0x110048
 
 	# TRM states that the register should be read back here, skipped for now
 
 	# enable debug "default" mode
-	icepick_c_router $jrc 1 0x2 $port 0x102048
+	icepick_c_router $jrc 1 0x2 $port 0x112048
 
 	# TRM states that debug enable and debug mode should be read back and
 	# confirmed - skipped for now
 
 	# Finally select the tap
-	icepick_c_router $jrc 1 0x2 $port 0x102148
+	icepick_c_router $jrc 1 0x2 $port 0x112148
 
 	# Enter the bypass state
 	irscan $jrc [CONST IR_BYPASS] -endstate RUN/IDLE
 	runtest 10
 }
 
+# jrc	== TAP name for the ICEpick
+# coreid== core id number 0..15 (not same as port number!)
+proc icepick_d_set_core_control {jrc coreid value } {
+	icepick_c_router $jrc 1 0x6 $coreid $value
+}
+
 # jrc	== TAP name for the ICEpick
 # port	== a port number, 0..15
 # Follow the sequence described in
 # http://processors.wiki.ti.com/images/f/f6/Router_Scan_Sequence-ICEpick-D.pdf
-proc icepick_d_tapenable {jrc port} {
+proc icepick_d_tapenable {jrc port coreid { value 0x2008 } } {
 	# First CONNECT to the ICEPick
 	icepick_c_connect $jrc
+	icepick_c_setup $jrc
 
 	# Select the port
-	irscan $jrc [CONST IR_ROUTER] -endstate IRPAUSE
-	drscan $jrc 32 [expr 0xa0002108 + ($port << 24)] -endstate DRPAUSE
+	icepick_c_router $jrc 1 0x2 $port 0x2108
 
-	# Set 4 bit core ID to the Cortex-A
-	irscan $jrc [CONST IR_ROUTER] -endstate IRPAUSE
-	drscan $jrc 32 0xe0002008 -endstate DRPAUSE
+	# Set icepick core control for $coreid
+	icepick_d_set_core_control $jrc $coreid $value
 
 	# Enter the bypass state
 	irscan $jrc [CONST IF_BYPASS] -endstate RUN/IDLE