X-Git-Url: https://review.openocd.org/gitweb?p=openocd.git;a=blobdiff_plain;f=tcl%2Ftarget%2Fat91sam9260_ext_RAM_ext_flash.cfg;h=535ae0fb50e3ad39d9b9dfc66c2ed6ea93e29598;hp=f10a021c8de68f01f19ed48d332e4de923feae31;hb=3f9d377ce788365844f9225064cb9b0f0b4542ef;hpb=dbbc9c41f7db210b0a4e226540a28e0a8a5019bf

diff --git a/tcl/target/at91sam9260_ext_RAM_ext_flash.cfg b/tcl/target/at91sam9260_ext_RAM_ext_flash.cfg
index f10a021c8d..535ae0fb50 100644
--- a/tcl/target/at91sam9260_ext_RAM_ext_flash.cfg
+++ b/tcl/target/at91sam9260_ext_RAM_ext_flash.cfg
@@ -1,22 +1,18 @@
-
-
-
-jtag_khz 4
-
+jtag_rclk 4
 
 ######################################
 # Target:    Atmel AT91SAM9260
 ######################################
 
-if { [info exists CHIPNAME] } {	
-   set  _CHIPNAME $CHIPNAME    
-} else {	 
+if { [info exists CHIPNAME] } {
+   set  _CHIPNAME $CHIPNAME
+} else {
    set  _CHIPNAME at91sam9260
 }
 
-if { [info exists ENDIAN] } {	
-   set  _ENDIAN $ENDIAN    
-} else {	 
+if { [info exists ENDIAN] } {
+   set  _ENDIAN $ENDIAN
+} else {
    set  _ENDIAN little
 }
 
@@ -30,7 +26,7 @@ if { [info exists CPUTAPID ] } {
 reset_config trst_and_srst
 
 
-jtag_nsrst_delay 200
+adapter_nsrst_delay 200
 jtag_ntrst_delay 200
 
 
@@ -41,28 +37,32 @@ jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CP
 # Target configuration
 ######################
 
-set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
+set _TARGETNAME $_CHIPNAME.cpu
 target create $_TARGETNAME arm926ejs -endian $_ENDIAN -chain-position $_TARGETNAME -variant arm926ejs
 
-$_TARGETNAME invoke-event halted
-
 # Internal sram1 memory
-$_TARGETNAME configure -work-area-virt 0 -work-area-phys 0x00300000 -work-area-size 0x1000 -work-area-backup 1
+$_TARGETNAME configure -work-area-phys 0x00300000 -work-area-size 0x1000 -work-area-backup 1
 
 scan_chain
-$_TARGETNAME configure -event reset-deassert-post {at91sam_init}
+$_TARGETNAME configure -event reset-start {
+	# at reset chip runs at 32khz
+	jtag_rclk 8
+}
 
+$_TARGETNAME configure -event reset-init {at91sam_init}
 
 # Flash configuration
-#flash bank cfi <base> <size> <chip width> <bus width> <target#>
-flash bank cfi 0x10000000 0x01000000 2 2 $_TARGETNAME
+#flash bank <name> cfi <base> <size> <chip width> <bus width> <target>
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME cfi 0x10000000 0x01000000 2 2 $_TARGETNAME
 
+# Faster memory downloads. This is disabled automatically during
+# reset init since all reset init sequences are too short for
+# fast memory access
+arm7_9 dcc_downloads enable     
+arm7_9 fast_memory_access enable
 
 proc at91sam_init { } {
-	
-	# at reset chip runs at 32khz
-	jtag_khz 8
-	halt
 	mww 0xfffffd08 0xa5000501         # RSTC_MR : enable user reset
 	mww 0xfffffd44 0x00008000         # WDT_MR : disable watchdog
 
@@ -78,16 +78,13 @@ proc at91sam_init { } {
 	sleep 10                          # wait 10 ms
 
 	# Now run at anything fast... ie: 10mhz!
-	jtag_khz 10000                    # Increase JTAG Speed to 6 MHz
-	arm7_9 dcc_downloads enable       # Enable faster DCC downloads
+	jtag_rclk 10000                    # Increase JTAG Speed to 6 MHz
 
 	mww 0xffffec00 0x0a0a0a0a         # SMC_SETUP0 : Setup SMC for Intel NOR Flash JS28F128P30T85 128MBit
 	mww 0xffffec04 0x0b0b0b0b         # SMC_PULSE0
 	mww 0xffffec08 0x00160016         # SMC_CYCLE0
 	mww 0xffffec0c 0x00161003         # SMC_MODE0
 
-	flash probe 0                     # Identify flash bank 0
-
 	mww 0xfffff870 0xffff0000         # PIO_ASR : Select peripheral function for D15..D31
 	mww 0xfffff804 0xffff0000         # PIO_PDR : Disable PIO function for D15..D31
 
@@ -122,6 +119,3 @@ proc at91sam_init { } {
 	mww 0x20000000 0
 	mww 0xffffea04 0x5d2              # SDRAMC_TR : Set refresh timer count to 15us
 }
-
-
-