X-Git-Url: https://review.openocd.org/gitweb?p=openocd.git;a=blobdiff_plain;f=tcl%2Ftarget%2Famdm37x.cfg;h=6004070f7b1a96a3994b93c5016fcecc1e01bae3;hp=b1bd25ce8db815aecf6f24ae7e95d14128b25deb;hb=refs%2Fchanges%2F56%2F1856%2F2;hpb=59beb93752c096fdfa0257ec126ee3e650140eec diff --git a/tcl/target/amdm37x.cfg b/tcl/target/amdm37x.cfg index b1bd25ce8d..6004070f7b 100644 --- a/tcl/target/amdm37x.cfg +++ b/tcl/target/amdm37x.cfg @@ -4,8 +4,8 @@ # Copyright (C) 2009 by David Brownell # Copyright (C) 2009 by Magnus Lundin # -# TI AM/DM37x -# http://www.ti.com/litv/pdf/sprugn4b +# TI AM/DM37x Technical Reference Manual (Version R) +# http://www.ti.com/lit/ug/sprugn4r/sprugn4r.pdf # # This script is based on the AM3517 initialization. It should be considered # preliminary since it needs more complete testing and only the basic @@ -21,18 +21,18 @@ if { [info exists CHIPTYPE] } { if { [info exists CHIPNAME] } { - set _CHIPNAME $CHIPNAME + set _CHIPNAME $CHIPNAME } else { - set _CHIPNAME $CHIPTYPE + set _CHIPNAME $CHIPTYPE } switch $CHIPTYPE { dm37x { - # Primary TAP: ICEpick-C (JTAG route controller) and boundary scan + # Primary TAP: ICEPick-C (JTAG route controller) and boundary scan set _JRC_TAPID "-expected-id 0x2b89102f -expected-id 0x1b89102f -expected-id 0x0b89102f" } am35x { - # Primary TAP: ICEpick-C (JTAG route controller) and boundary scan + # Primary TAP: ICEPick-C (JTAG route controller) and boundary scan set _JRC_TAPID "-expected-id 0x0b7ae02f" } default { @@ -50,20 +50,20 @@ adapter_khz 10 ############################################################################### # JTAG setup # The OpenOCD commands are described in the TAP Declaration section -# http://openocd.berlios.de/doc/html/TAP-Declaration.html +# http://openocd.sourceforge.net/doc/html/TAP-Declaration.html ############################################################################### -# The AM/DM37x has an ICEpick module in it like many of TI's other devices. More -# can be read about this module in sprugn4b under chapter 27: "Debug and +# The AM/DM37x has an ICEPick module in it like many of TI's other devices. More +# can be read about this module in sprugn4r in chapter 27: "Debug and # Emulation". The module is used to route the JTAG chain to the various # subsystems in the chip. source [find target/icepick.cfg] # The TAP order should be described from the TDO connection in OpenOCD to the # TDI pin. The OpenOCD FAQ describes this in more detail: -# http://openocd.berlios.de/doc/html/FAQ.html +# http://openocd.sourceforge.net/doc/html/FAQ.html -# From SPRUGN4B CH27 the available secondary TAPs are in this order from TDO: +# From SPRUGN4R CH27 the available secondary TAPs are in this order from TDO: # # Device | TAP number # ---------|------------ @@ -77,9 +77,9 @@ source [find target/icepick.cfg] ###### # Start of Chain Description -# The Secondary TAPs all have enable functions defined for use with the ICEpick +# The Secondary TAPs all have enable functions defined for use with the ICEPick # Only the DAP is enabled. The AM37xx does not have the Sequencer or DSP but -# the TAP numbers for ICEpick do not change. +# the TAP numbers for ICEPick do not change. # # TODO: A disable function should also be added. ###### @@ -93,26 +93,26 @@ jtag configure $_CHIPNAME.dap -event tap-enable \ # These taps are only present in the DM37x series. if { $CHIPTYPE == "dm37x" } { # Secondary TAP: Sequencer (ARM968) it is not in the chain by default - # The ICEpick can be used to enable it in the chain. + # The ICEPick can be used to enable it in the chain. jtag newtap $_CHIPNAME arm2 -irlen 4 -ircapture 0x1 -irmask 0x0f -disable jtag configure $_CHIPNAME.arm2 -event tap-enable \ "icepick_c_tapenable $_CHIPNAME.jrc 2" # Secondary TAP: C64x+ DSP - it is not in the chain by default (-disable) - # The ICEpick can be used to enable it in the chain. + # The ICEPick can be used to enable it in the chain. jtag newtap $_CHIPNAME dsp -irlen 38 -ircapture 0x25 -irmask 0x3f -disable jtag configure $_CHIPNAME.dsp -event tap-enable \ "icepick_c_tapenable $_CHIPNAME.jrc 1" } # Secondary TAP: D2D it is not in the chain by default (-disable) -# The ICEpick can be used to enable it in the chain. +# The ICEPick can be used to enable it in the chain. # This IRLEN is probably incorrect - not sure where the documentation is. jtag newtap $_CHIPNAME d2d -irlen 4 -ircapture 0x1 -irmask 0x0f -disable jtag configure $_CHIPNAME.d2d -event tap-enable \ "icepick_c_tapenable $_CHIPNAME.jrc 0" -# Primary TAP: ICEpick - it is closest to TDI so last in the chain +# Primary TAP: ICEPick - it is closest to TDI so last in the chain eval "jtag newtap $_CHIPNAME jrc -irlen 6 -ircapture 0x1 -irmask 0x3f $_JRC_TAPID" ###### @@ -136,12 +136,12 @@ jtag configure $_CHIPNAME.jrc -event setup "jtag tapenable $_CHIPNAME.dap" ############################################################################### # Target Setup: # This section is described in the OpenOCD documentation under CPU Configuration -# http://openocd.berlios.de/doc/html/CPU-Configuration.html +# http://openocd.sourceforge.net/doc/html/CPU-Configuration.html ############################################################################### # Create the CPU target to be used with GDB: Cortex-A8, using DAP set _TARGETNAME $_CHIPNAME.cpu -target create $_TARGETNAME cortex_a8 -chain-position $_CHIPNAME.dap +target create $_TARGETNAME cortex_a -chain-position $_CHIPNAME.dap # The DM37x has 64K of SRAM starting at address 0x4020_0000. Allow the first # 16K to be used as a scratchpad for OpenOCD. @@ -200,7 +200,7 @@ $_TARGETNAME configure -event gdb-attach { # reset sequence. proc amdm37x_dbginit {target} { # General Cortex A8 debug initialisation - cortex_a8 dbginit + cortex_a dbginit # Enable DBGEN signal. This signal is described in the ARM v7 TRM, but # access to the signal appears to be implementation specific. TI does not