X-Git-Url: https://review.openocd.org/gitweb?p=openocd.git;a=blobdiff_plain;f=tcl%2Fboard%2Fstm32h7x_dual_qspi.cfg;fp=tcl%2Fboard%2Fstm32h7x_dual_qspi.cfg;h=bdff9c1b81cd1255c79cf95fa62246fc0a5359b8;hp=0000000000000000000000000000000000000000;hb=e44539d66c8929679321704768125df9ba7d5f67;hpb=475f42051e13d64bc4d1960306ad1d2ea3c7962a

diff --git a/tcl/board/stm32h7x_dual_qspi.cfg b/tcl/board/stm32h7x_dual_qspi.cfg
new file mode 100644
index 0000000000..bdff9c1b81
--- /dev/null
+++ b/tcl/board/stm32h7x_dual_qspi.cfg
@@ -0,0 +1,90 @@
+# stm32h754i-disco and stm32h750b-dk dual quad qspi.
+
+# QUADSPI initialization
+# qpi: 4-line mode
+proc qspi_init { qpi } {
+	global a
+	mmw 0x580244E0 0x000007FF 0				;# RCC_AHB4ENR |= GPIOAEN-GPIOKEN (enable clocks)
+	mmw 0x580244D4 0x00004000 0				;# RCC_AHB3ENR |= QSPIEN (enable clock)
+	sleep 1									;# Wait for clock startup
+
+	# PG06: BK1_NCS, PF10: CLK, PF06: BK1_IO3, PF07: BK1_IO2, PF09: BK1_IO1, PD11: BK1_IO0,
+	# PG14: BK2_IO3, PG09: BK2_IO2, PH03: BK2_IO1, PH02: BK2_IO0
+
+	# PD11:AF09:V, PF10:AF09:V, PF09:AF10:V, PF07:AF09:V, PF06:AF09:V, PG14:AF09:H
+	# PG09:AF09:V, PG06:AF10:H, PH03:AF09:V, PH02:AF09:V
+
+	# Port D: PD11:AF09:V
+	mmw 0x58020C00 0x00800000 0x00400000	;# MODER
+	mmw 0x58020C08 0x00C00000 0x00000000	;# OSPEEDR
+	mmw 0x58020C24 0x00009000 0x00006000	;# AFRH
+	# Port F: PF10:AF09:V, PF09:AF10:V, PF07:AF09:V, PF06:AF09:V
+	mmw 0x58021400 0x0028A000 0x00145000	;# MODER
+	mmw 0x58021408 0x003CF000 0x00000000	;# OSPEEDR
+	mmw 0x58021420 0x99000000 0x66000000	;# AFRL
+	mmw 0x58021424 0x000009A0 0x00000650	;# AFRH
+	# Port G: PG14:AF09:H, PG09:AF09:V, PG06:AF10:H
+	mmw 0x58021800 0x20082000 0x10041000	;# MODER
+	mmw 0x58021808 0x200C2000 0x10001000	;# OSPEEDR
+	mmw 0x58021820 0x0A000000 0x05000000	;# AFRL
+	mmw 0x58021824 0x09000090 0x06000060	;# AFRH
+	# Port H: PH03:AF09:V, PH02:AF09:V
+	mmw 0x58021C00 0x000000A0 0x00000050	;# MODER
+	mmw 0x58021C08 0x000000F0 0x00000000	;# OSPEEDR
+	mmw 0x58021C20 0x00009900 0x00006600	;# AFRL
+
+	# correct FSIZE is 0x1A, however, this causes trouble when
+	# reading the last bytes at end of bank in *memory mapped* mode
+
+	# for dual flash mode 2 * mt25ql512
+	mww 0x52005000 0x05500058				;# QUADSPI_CR: PRESCALER=5, APMS=1, FTHRES=0, FSEL=0, DFM=1, SSHIFT=1, TCEN=1
+	mww 0x52005004 0x001A0200				;# QUADSPI_DCR: FSIZE=0x1A, CSHT=0x02, CKMODE=0
+
+	mww 0x52005030 0x00001000				;# QUADSPI_LPTR: deactivate CS after 4096 clocks when FIFO is full
+	mww 0x52005014 0x0D002503				;# QUADSPI_CCR: FMODE=0x3, DMODE=0x1, DCYC=0x0, ADSIZE=0x3, ADMODE=0x1, IMODE=0x1
+	mmw 0x52005000 0x00000001 0				;# QUADSPI_CR: EN=1
+
+	# Exit QPI mode
+	mmw 0x52005000 0x00000002 0				;# QUADSPI_CR: ABORT=1
+	mww 0x52005014 0x000003F5				;# QUADSPI_CCR: FMODE=0x0, DMODE=0x0, DCYC=0x0, ADSIZE=0x0, ADMODE=0x0, IMODE=0x3, INSTR=Exit QPI
+	sleep 1
+
+	if { $qpi == 1 } {
+		# Write Enable
+		mmw 0x52005000 0x00000002 0			;# QUADSPI_CR: ABORT=1
+		mww 0x52005014 0x00000106			;# QUADSPI_CCR: FMODE=0x0, DMODE=0x0, DCYC=0x0, ADSIZE=0x0, ADMODE=0x0, IMODE=0x1, INSTR=Write Enable
+		sleep 1
+
+		# Configure dummy clocks via volatile configuration register
+		mmw 0x52005000 0x00000002 0			;# QUADSPI_CR: ABORT=1
+		mww 0x52005010 0x00000001			;# QUADSPI_DLR: 2 data bytes
+		mww 0x52005014 0x01000181			;# QUADSPI_CCR: FMODE=0x0, DMODE=0x1, DCYC=0x0, ADSIZE=0x0, ADMODE=0x0, IMODE=0x1, INSTR=Write Volatile Conf. Reg.
+		mwh 0x52005020 0xABAB				;# QUADSPI_DR: 0xAB 0xAB for 10 dummy clocks
+		sleep 1
+
+		# Write Enable
+		mmw 0x52005000 0x00000002 0			;# QUADSPI_CR: ABORT=1
+		mww 0x52005014 0x00000106			;# QUADSPI_CCR: FMODE=0x0, DMODE=0x0, DCYC=0x0, ADSIZE=0x0, ADMODE=0x0, IMODE=0x1, INSTR=Write Enable
+		sleep 1
+
+		# Enable QPI mode via enhanced volatile configuration register
+		mmw 0x52005000 0x00000002 0			;# QUADSPI_CR: ABORT=1
+		mww 0x52005010 0x00000001			;# QUADSPI_DLR: 2 data bytes
+		mww 0x52005014 0x01000161			;# QUADSPI_CCR: FMODE=0x0, DMODE=0x1, DCYC=0x0, ADSIZE=0x0, ADMODE=0x0, IMODE=0x1, INSTR=Write Enhanced Conf. Reg.
+		mwh 0x52005020 0x3F3F				;# QUADSPI_DR: 0x3F 0x3F to enable QPI and DPI mode
+		sleep 1
+
+		# Enter QPI mode
+		mmw 0x52005000 0x00000002 0			;# QUADSPI_CR: ABORT=1
+		mww 0x52005014 0x00000135			;# QUADSPI_CCR: FMODE=0x0, DMODE=0x0, DCYC=0x0, ADSIZE=0x0, ADMODE=0x0, IMODE=0x1, INSTR=Enter QPI
+		sleep 1
+
+		# memory-mapped fast read mode with 4-byte addresses and 10 dummy cycles (for read only)
+		mmw 0x52005000 0x00000002 0			;# QUADSPI_CR: ABORT=1
+		mww 0x52005014 0x0F283FEC			;# QUADSPI_CCR: FMODE=0x3, DMODE=0x3, DCYC=0xA, ADSIZE=0x3, ADMODE=0x3, IMODE=0x3, INSTR=Fast READ
+	} else {
+		# memory-mapped read mode with 4-byte addresses
+		mmw 0x52005000 0x00000002 0			;# QUADSPI_CR: ABORT=1
+		mww 0x52005014 0x0D003513			;# QUADSPI_CCR: FMODE=0x3, DMODE=0x1, DCYC=0x0, ADSIZE=0x3, ADMODE=0x1, IMODE=0x1, INSTR=READ
+	}
+}