X-Git-Url: https://review.openocd.org/gitweb?p=openocd.git;a=blobdiff_plain;f=tcl%2Fboard%2Fopenrd.cfg;h=fda01d1291c84381d20c89d1afb2132120ae69d8;hp=e8784d402558e6774e400a7a492a32f6f7ef13d6;hb=HEAD;hpb=3e1f5e7c64ea545f6e87b5fa1adb0c00358be505

diff --git a/tcl/board/openrd.cfg b/tcl/board/openrd.cfg
index e8784d4025..f6c8317700 100644
--- a/tcl/board/openrd.cfg
+++ b/tcl/board/openrd.cfg
@@ -1,8 +1,12 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 # Marvell OpenRD
 
-source [find interface/openrd.cfg]
+source [find interface/ftdi/openrd.cfg]
 source [find target/feroceon.cfg]
 
+adapter speed 2000
+
 $_TARGETNAME configure \
 	-work-area-phys 0x10000000 \
 	-work-area-size 65536 \
@@ -23,80 +27,80 @@ proc openrd_init { } {
 	# possible that initial tap examination failed.  So let's
 	# re-examine the target again here when nSRST is asserted which
 	# should then succeed.
-	jtag_reset 0 1
+	adapter assert srst
 	feroceon.cpu arp_examine
 	halt 0
-	jtag_reset 0 0
+	adapter deassert srst
 	wait_halt
 
-	arm926ejs cp15 0 0 1 0 0x00052078
-
-	mww 0xD0001400 0x43000C30 #  DDR SDRAM Configuration Register
-	mww 0xD0001404 0x37543000 #  Dunit Control Low Register
-	mww 0xD0001408 0x22125451 #  DDR SDRAM Timing (Low) Register
-	mww 0xD000140C 0x00000A33 #  DDR SDRAM Timing (High) Register
-	mww 0xD0001410 0x000000CC #  DDR SDRAM Address Control Register
-	mww 0xD0001414 0x00000000 #  DDR SDRAM Open Pages Control Register
-	mww 0xD0001418 0x00000000 #  DDR SDRAM Operation Register
-	mww 0xD000141C 0x00000C52 #  DDR SDRAM Mode Register
-	mww 0xD0001420 0x00000004 #  DDR SDRAM Extended Mode Register
-	mww 0xD0001424 0x0000F17F #  Dunit Control High Register
-	mww 0xD0001428 0x00085520 #  Dunit Control High Register
-	mww 0xD000147c 0x00008552 #  Dunit Control High Register
-	mww 0xD0001504 0x0FFFFFF1 #  CS0n Size Register
-	mww 0xD0001508 0x10000000 #  CS1n Base Register
-	mww 0xD000150C 0x0FFFFFF5 #  CS1n Size Register
-	mww 0xD0001514 0x00000000 #  CS2n Size Register
-	mww 0xD000151C 0x00000000 #  CS3n Size Register
-	mww 0xD0001494 0x00120012 #  DDR2 SDRAM ODT Control (Low) Register
-	mww 0xD0001498 0x00000000 #  DDR2 SDRAM ODT Control (High) REgister
-	mww 0xD000149C 0x0000E40F #  DDR2 Dunit ODT Control Register
-	mww 0xD0001480 0x00000001 #  DDR SDRAM Initialization Control Register
-	mww 0xD0020204 0x00000000 #  Main IRQ Interrupt Mask Register
-	mww 0xD0020204 0x00000000 #              "
-	mww 0xD0020204 0x00000000 #              "
-	mww 0xD0020204 0x00000000 #              "
-	mww 0xD0020204 0x00000000 #              "
-	mww 0xD0020204 0x00000000 #              "
-	mww 0xD0020204 0x00000000 #              "
-	mww 0xD0020204 0x00000000 #              "
-	mww 0xD0020204 0x00000000 #              "
-	mww 0xD0020204 0x00000000 #              "
-	mww 0xD0020204 0x00000000 #              "
-	mww 0xD0020204 0x00000000 #              "
-	mww 0xD0020204 0x00000000 #              "
-	mww 0xD0020204 0x00000000 #              "
-	mww 0xD0020204 0x00000000 #              "
-	mww 0xD0020204 0x00000000 #              "
-	mww 0xD0020204 0x00000000 #              "
-	mww 0xD0020204 0x00000000 #              "
-	mww 0xD0020204 0x00000000 #              "
-	mww 0xD0020204 0x00000000 #              "
-	mww 0xD0020204 0x00000000 #              "
-	mww 0xD0020204 0x00000000 #              "
-	mww 0xD0020204 0x00000000 #              "
-	mww 0xD0020204 0x00000000 #              "
-	mww 0xD0020204 0x00000000 #              "
-	mww 0xD0020204 0x00000000 #              "
-	mww 0xD0020204 0x00000000 #              "
-	mww 0xD0020204 0x00000000 #              "
-	mww 0xD0020204 0x00000000 #              "
-	mww 0xD0020204 0x00000000 #              "
-	mww 0xD0020204 0x00000000 #              "
-	mww 0xD0020204 0x00000000 #              "
-	mww 0xD0020204 0x00000000 #              "
-	mww 0xD0020204 0x00000000 #              "
-	mww 0xD0020204 0x00000000 #              "
-	mww 0xD0020204 0x00000000 #              "
-	mww 0xD0020204 0x00000000 #              "
-
-	mww 0xD0010000 0x01111111 #  MPP  0 to 7
-	mww 0xD0010004 0x11113322 #  MPP  8 to 15
-	mww 0xD0010008 0x00001111 #  MPP 16 to 23
-
-	mww 0xD0010418 0x003E07CF #  NAND Read Parameters REgister
-	mww 0xD001041C 0x000F0F0F #  NAND Write Parameters Register
-	mww 0xD0010470 0x01C7D943 #  NAND Flash Control Register
+	arm mcr 15 0 0 1 0 0x00052078
+
+	mww 0xD0001400 0x43000C30 ;#  DDR SDRAM Configuration Register
+	mww 0xD0001404 0x37543000 ;#  Dunit Control Low Register
+	mww 0xD0001408 0x22125451 ;#  DDR SDRAM Timing (Low) Register
+	mww 0xD000140C 0x00000A33 ;#  DDR SDRAM Timing (High) Register
+	mww 0xD0001410 0x000000CC ;#  DDR SDRAM Address Control Register
+	mww 0xD0001414 0x00000000 ;#  DDR SDRAM Open Pages Control Register
+	mww 0xD0001418 0x00000000 ;#  DDR SDRAM Operation Register
+	mww 0xD000141C 0x00000C52 ;#  DDR SDRAM Mode Register
+	mww 0xD0001420 0x00000004 ;#  DDR SDRAM Extended Mode Register
+	mww 0xD0001424 0x0000F17F ;#  Dunit Control High Register
+	mww 0xD0001428 0x00085520 ;#  Dunit Control High Register
+	mww 0xD000147c 0x00008552 ;#  Dunit Control High Register
+	mww 0xD0001504 0x0FFFFFF1 ;#  CS0n Size Register
+	mww 0xD0001508 0x10000000 ;#  CS1n Base Register
+	mww 0xD000150C 0x0FFFFFF5 ;#  CS1n Size Register
+	mww 0xD0001514 0x00000000 ;#  CS2n Size Register
+	mww 0xD000151C 0x00000000 ;#  CS3n Size Register
+	mww 0xD0001494 0x00120012 ;#  DDR2 SDRAM ODT Control (Low) Register
+	mww 0xD0001498 0x00000000 ;#  DDR2 SDRAM ODT Control (High) REgister
+	mww 0xD000149C 0x0000E40F ;#  DDR2 Dunit ODT Control Register
+	mww 0xD0001480 0x00000001 ;#  DDR SDRAM Initialization Control Register
+	mww 0xD0020204 0x00000000 ;#  Main IRQ Interrupt Mask Register
+	mww 0xD0020204 0x00000000 ;#              "
+	mww 0xD0020204 0x00000000 ;#              "
+	mww 0xD0020204 0x00000000 ;#              "
+	mww 0xD0020204 0x00000000 ;#              "
+	mww 0xD0020204 0x00000000 ;#              "
+	mww 0xD0020204 0x00000000 ;#              "
+	mww 0xD0020204 0x00000000 ;#              "
+	mww 0xD0020204 0x00000000 ;#              "
+	mww 0xD0020204 0x00000000 ;#              "
+	mww 0xD0020204 0x00000000 ;#              "
+	mww 0xD0020204 0x00000000 ;#              "
+	mww 0xD0020204 0x00000000 ;#              "
+	mww 0xD0020204 0x00000000 ;#              "
+	mww 0xD0020204 0x00000000 ;#              "
+	mww 0xD0020204 0x00000000 ;#              "
+	mww 0xD0020204 0x00000000 ;#              "
+	mww 0xD0020204 0x00000000 ;#              "
+	mww 0xD0020204 0x00000000 ;#              "
+	mww 0xD0020204 0x00000000 ;#              "
+	mww 0xD0020204 0x00000000 ;#              "
+	mww 0xD0020204 0x00000000 ;#              "
+	mww 0xD0020204 0x00000000 ;#              "
+	mww 0xD0020204 0x00000000 ;#              "
+	mww 0xD0020204 0x00000000 ;#              "
+	mww 0xD0020204 0x00000000 ;#              "
+	mww 0xD0020204 0x00000000 ;#              "
+	mww 0xD0020204 0x00000000 ;#              "
+	mww 0xD0020204 0x00000000 ;#              "
+	mww 0xD0020204 0x00000000 ;#              "
+	mww 0xD0020204 0x00000000 ;#              "
+	mww 0xD0020204 0x00000000 ;#              "
+	mww 0xD0020204 0x00000000 ;#              "
+	mww 0xD0020204 0x00000000 ;#              "
+	mww 0xD0020204 0x00000000 ;#              "
+	mww 0xD0020204 0x00000000 ;#              "
+	mww 0xD0020204 0x00000000 ;#              "
+
+	mww 0xD0010000 0x01111111 ;#  MPP  0 to 7
+	mww 0xD0010004 0x11113322 ;#  MPP  8 to 15
+	mww 0xD0010008 0x00001111 ;#  MPP 16 to 23
+
+	mww 0xD0010418 0x003E07CF ;#  NAND Read Parameters REgister
+	mww 0xD001041C 0x000F0F0F ;#  NAND Write Parameters Register
+	mww 0xD0010470 0x01C7D943 ;#  NAND Flash Control Register
 
 }
 
@@ -120,4 +124,3 @@ proc openrd_load_uboot { } {
 	resume 0x00600000
 
 }
-