X-Git-Url: https://review.openocd.org/gitweb?p=openocd.git;a=blobdiff_plain;f=tcl%2Fboard%2Fimx35pdk.cfg;h=b5aa752fa248ec86bd30f9a56a5a785bb2d428fd;hp=3e0bf6b33ee67122fdf6f27a7dfa720159574737;hb=30da7c67cec8b315972377b5389735ff11f6042c;hpb=55f4e430e8c1c7382d27695c56e8ca95ba7b7dec

diff --git a/tcl/board/imx35pdk.cfg b/tcl/board/imx35pdk.cfg
index 3e0bf6b33e..b5aa752fa2 100644
--- a/tcl/board/imx35pdk.cfg
+++ b/tcl/board/imx35pdk.cfg
@@ -1,35 +1,15 @@
 # The IMX35PDK eval board has a single IMX35 chip
 source [find target/imx35.cfg]
+source [find target/imx.cfg]
 $_TARGETNAME configure -event reset-init { imx35pdk_init }
 
-memwrite burst disable
-#arm11 no_increment enable
-
-
-global TARGETNAME 
-set TARGETNAME $_TARGETNAME
-
-# rewrite commands of the form below to arm11 mcr...
-#	Data.Set c15:0x042f %long 0x40000015
-proc setc15 {regs value} {
-	global TARGETNAME 
-
-	echo [format "set p15 0x%04x, 0x%08x" $regs $value] 
-
-	arm11 mcr $TARGETNAME 15 [expr ($regs>>12)&0x7] [expr ($regs>>0)&0xf] [expr ($regs>>4)&0xf] [expr ($regs>>8)&0x7] $value 
-}
+# Stick to *really* low clock rate or reset will fail
+# without RTCK / RCLK
+jtag_rclk 10
 
 proc imx35pdk_init { } {
 	
-	
-	echo "Target Setup: initialize DRAM controller and peripherals"
-	
-#	Data.Set c15:0x01 %long 0x00050078
-	setc15 0x01 0x00050078
-	
-	echo "configuring CP15 for enabling the peripheral bus"
-#	Data.Set c15:0x042f %long 0x40000015
-	setc15 0x042f 0x40000015
+	imx3x_reset
 	
 	mww 0x43f00040 0x00000000
 	mww 0x43f00044 0x00000000
@@ -47,8 +27,8 @@ proc imx35pdk_init { } {
 	mww 0x53f00004 0x77777777
 	
 	# clock setup
-	mww 0x53F80004 0x00821000 # first need to set IPU_HND_BYP
-	mww 0x53F80004 0x00821000 #arm clock is 399Mhz and ahb clock is 133Mhz.
+	mww 0x53F80004 0x00821000 ;# first need to set IPU_HND_BYP
+	mww 0x53F80004 0x00821000 ;#arm clock is 399Mhz and ahb clock is 133Mhz.
 	
 	#=================================================
 	# WEIM config
@@ -142,8 +122,8 @@ proc imx35pdk_init { } {
 	mww 0x43FAC474 0x00000006
 	mww 0x43FAC478 0x00000006
 	mww 0x43FAC47c 0x00000006
-	mww 0x43FAC480 0x00000006	# CSD0
-	mww 0x43FAC484 0x00000006	# CSD1
+	mww 0x43FAC480 0x00000006	;# CSD0
+	mww 0x43FAC484 0x00000006	;# CSD1
 	mww 0x43FAC488 0x00000006
 	mww 0x43FAC48c 0x00000006
 	mww 0x43FAC490 0x00000006
@@ -151,12 +131,12 @@ proc imx35pdk_init { } {
 	mww 0x43FAC498 0x00000006
 	mww 0x43FAC49c 0x00000006
 	mww 0x43FAC4A0 0x00000006	
-	mww 0x43FAC4A4 0x00000006	# RAS
-	mww 0x43FAC4A8 0x00000006	# CAS
-	mww 0x43FAC4Ac 0x00000006	# SDWE
-	mww 0x43FAC4B0 0x00000006 	# SDCKE0
-	mww 0x43FAC4B4 0x00000006  # SDCKE1
-	mww 0x43FAC4B8 0x00000002  # SDCLK
+	mww 0x43FAC4A4 0x00000006	;# RAS
+	mww 0x43FAC4A8 0x00000006	;# CAS
+	mww 0x43FAC4Ac 0x00000006	;# SDWE
+	mww 0x43FAC4B0 0x00000006 	;# SDCKE0
+	mww 0x43FAC4B4 0x00000006  ;# SDCKE1
+	mww 0x43FAC4B8 0x00000002  ;# SDCLK
 	
 	# SDQS0 through SDQS3
 	mww 0x43FAC4Bc 0x00000082
@@ -231,7 +211,7 @@ proc imx35pdk_init { } {
 	# DDR2 : Load reg EMR1 -- OCD default
 	mwb 0x82000780 0xda
 	# DDR2 : Load reg EMR1 -- OCD exit
-	mwb 0x82000400 0xda	# ODT disabled
+	mwb 0x82000400 0xda	;# ODT disabled
 	
 	# ESD_ESDCTL0 : select normal-operation mode
 	# DSIZ=32-bit, BL=8, COL=10-bit, ROW=13-bit
@@ -249,10 +229,10 @@ proc imx35pdk_init { } {
 	# Adjust the ESDCDLY5 register
 	#***********************************************
 	# Vary DQS_ABS_OFFSET5 for writes
-	mww 0xB8001020 0x00F48000	# this is the default value
-	mww 0xB8001024 0x00F48000	# this is the default value
-	mww 0xB8001028 0x00F48000	# this is the default value
-	mww 0xB800102c 0x00F48000	# this is the default value
+	mww 0xB8001020 0x00F48000	;# this is the default value
+	mww 0xB8001024 0x00F48000	;# this is the default value
+	mww 0xB8001028 0x00F48000	;# this is the default value
+	mww 0xB800102c 0x00F48000	;# this is the default value
 	
 	
 	#Then you can make force measure with the dedicated bit (Bit 7 at ESDMISC)