X-Git-Url: https://review.openocd.org/gitweb?p=openocd.git;a=blobdiff_plain;f=tcl%2Fboard%2Fatmel_at91sam9rl-ek.cfg;h=e18d1fdf3a3242dbc1bb6602aa0c80eaf5ec9d5f;hp=3b932bf4c1165a3e088e5a71b0b8716c2f523299;hb=30da7c67cec8b315972377b5389735ff11f6042c;hpb=af3f77a1777e4f28ec1a14122f4800ca3467e4c7

diff --git a/tcl/board/atmel_at91sam9rl-ek.cfg b/tcl/board/atmel_at91sam9rl-ek.cfg
index 3b932bf4c1..e18d1fdf3a 100644
--- a/tcl/board/atmel_at91sam9rl-ek.cfg
+++ b/tcl/board/atmel_at91sam9rl-ek.cfg
@@ -22,36 +22,36 @@ $_TARGETNAME configure -event reset-start {
 }
 
 $_TARGETNAME configure -event reset-init {
-        mww 0xfffffd44 0x00008000         # WDT_MR : disable watchdog
+        mww 0xfffffd44 0x00008000         ;# WDT_MR : disable watchdog
 
-	mww 0xfffffc20 0x00004001         # CKGR_MOR : enable the main oscillator
-        sleep 20                          # wait 20 ms
-        mww 0xfffffc30 0x00000001         # PMC_MCKR : switch to main oscillator
-        sleep 10                          # wait 10 ms
-        mww 0xfffffc28 0x2031bf03         # CKGR_PLLR: Set PLL Register for 200 MHz
-        sleep 20                          # wait 20 ms
-        mww 0xfffffc30 0x00000101         # PMC_MCKR : Select prescaler (divide by 2)
-        sleep 10                          # wait 10 ms
-        mww 0xfffffc30 0x00000102         # PMC_MCKR : Clock from PLL is selected (100 MHz)
-        sleep 10                          # wait 10 ms
+	mww 0xfffffc20 0x00004001         ;# CKGR_MOR : enable the main oscillator
+        sleep 20                          ;# wait 20 ms
+        mww 0xfffffc30 0x00000001         ;# PMC_MCKR : switch to main oscillator
+        sleep 10                          ;# wait 10 ms
+        mww 0xfffffc28 0x2031bf03         ;# CKGR_PLLR: Set PLL Register for 200 MHz
+        sleep 20                          ;# wait 20 ms
+        mww 0xfffffc30 0x00000101         ;# PMC_MCKR : Select prescaler (divide by 2)
+        sleep 10                          ;# wait 10 ms
+        mww 0xfffffc30 0x00000102         ;# PMC_MCKR : Clock from PLL is selected (100 MHz)
+        sleep 10                          ;# wait 10 ms
 
 	# Increase JTAG Speed to 6 MHz if RCLK is not supported
         jtag_rclk 6000
 
-	arm7_9 dcc_downloads enable       # Enable faster DCC downloads
+	arm7_9 dcc_downloads enable       ;# Enable faster DCC downloads
 
-	mww 0xfffff670 0xffff0000         # PIO_ASR  : Select peripheral function for D16..D31 (PIOB)
-        mww 0xfffff604 0xffff0000         # PIO_PDR  : Disable PIO function for D16..D31 (PIOB)
+	mww 0xfffff670 0xffff0000         ;# PIO_ASR  : Select peripheral function for D16..D31 (PIOB)
+        mww 0xfffff604 0xffff0000         ;# PIO_PDR  : Disable PIO function for D16..D31 (PIOB)
 
-        mww 0xffffef20 0x00010002         # EBI_CSA  : Assign EBI Chip Select 1 to SDRAM, VDDIOMSEL set for +3V3 memory
+        mww 0xffffef20 0x00010002         ;# EBI_CSA  : Assign EBI Chip Select 1 to SDRAM, VDDIOMSEL set for +3V3 memory
 
-	mww 0xffffea08 0x85227259         # SDRAMC_CR : Configure SDRAM (2 x Micron MT48LC16M16A2 : 4M x 16Bit x 4 Banks)
+	mww 0xffffea08 0x85227259         ;# SDRAMC_CR : Configure SDRAM (2 x Micron MT48LC16M16A2 : 4M x 16Bit x 4 Banks)
 
-	mww 0xffffea00 0x1                # SDRAMC_MR : issue a NOP command
+	mww 0xffffea00 0x1                ;# SDRAMC_MR : issue a NOP command
 	mww 0x20000000 0
-	mww 0xffffea00 0x2                # SDRAMC_MR : issue an 'All Banks Precharge' command
+	mww 0xffffea00 0x2                ;# SDRAMC_MR : issue an 'All Banks Precharge' command
 	mww 0x20000000 0
-	mww 0xffffea00 0x4                # SDRAMC_MR : issue 8 x 'Auto-Refresh' Command
+	mww 0xffffea00 0x4                ;# SDRAMC_MR : issue 8 x 'Auto-Refresh' Command
 	mww 0x20000000 0
 	mww 0xffffea00 0x4
 	mww 0x20000000 0
@@ -67,9 +67,9 @@ $_TARGETNAME configure -event reset-init {
 	mww 0x20000000 0
 	mww 0xffffea00 0x4
 	mww 0x20000000 0
-	mww 0xffffea00 0x3                # SDRAMC_MR : issue a 'Load Mode Register' command
+	mww 0xffffea00 0x3                ;# SDRAMC_MR : issue a 'Load Mode Register' command
 	mww 0x20000000 0
-	mww 0xffffea00 0x0                # SDRAMC_MR : normal mode
+	mww 0xffffea00 0x0                ;# SDRAMC_MR : normal mode
 	mww 0x20000000 0
-	mww 0xffffea04 0x2b6              # SDRAMC_TR : Set refresh timer count to 7us
+	mww 0xffffea04 0x2b6              ;# SDRAMC_TR : Set refresh timer count to 7us
 }