X-Git-Url: https://review.openocd.org/gitweb?p=openocd.git;a=blobdiff_plain;f=tcl%2Fboard%2Fat91sam9g20-ek.cfg;h=4740471c896cb81168136c5cbcafcc46b0497521;hp=c9deb144b0fe87ee1f94a495ea167d533366839a;hb=HEAD;hpb=bb5f713e44c4025673565008a7aa5211e9d0c94e diff --git a/tcl/board/at91sam9g20-ek.cfg b/tcl/board/at91sam9g20-ek.cfg index c9deb144b0..4740471c89 100644 --- a/tcl/board/at91sam9g20-ek.cfg +++ b/tcl/board/at91sam9g20-ek.cfg @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + ################################################################################################# # # # Author: Gary Carlson (gcarlson@carlson-minot.com) # @@ -5,64 +7,57 @@ # # ################################################################################################# -# Define basic characteristics for the CPU. The AT91SAM9G20 processor is a subtle variant of -# the AT91SAM9260 and shares the same tap ID as it. - -set _CHIPNAME at91sam9g20 -set _ENDIAN little -set _CPUTAPID 0x0792603f - -# Set reset type. Note that the AT91SAM9G20-EK board has the trst signal disconnected. In theory this script -# therefore should require "srst_only". With some J-Link debuggers at least, "srst_only" causes a temporary USB -# communication fault. This appears to be more likely attributed to an internal proprietary firmware quirk inside the -# dongle itself. Using "trst_and_srst" works fine, however. So if you can't beat them -- join them. If you are using -# something other the a J-Link dongle you may be able to change this back to "srst_only". +source [find target/at91sam9g20.cfg] -reset_config trst_and_srst +set _FLASHTYPE nandflash_cs3 -# Set up the CPU and generate a new jtag tap for AT91SAM9G20. +# Set reset type. Note that the AT91SAM9G20-EK board has the trst signal disconnected. Therefore +# the reset needs to be configured for "srst_only". If for some reason, a zero-ohm jumper is +# added to the board to connect the trst signal, then this parameter may need to be changed. -jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID +reset_config srst_only -# Use caution changing the delays listed below. These seem to be affected by the board and type of -# debugger dongle. A value of 200 ms seems to work reliably for the configuration listed in the file header above. - -jtag_nsrst_delay 200 +adapter srst delay 200 jtag_ntrst_delay 200 -# Set fallback clock to 1/6 of worst-case clock speed (which would be the 32.768 kHz slow clock). - -jtag_rclk 5 - -set _TARGETNAME [format "%s.cpu" $_CHIPNAME] -target create $_TARGETNAME arm926ejs -endian $_ENDIAN -chain-position $_TARGETNAME -variant arm926ejs - -# Establish internal SRAM memory work areas that are important to pre-bootstrap loaders, etc. The -# AT91SAM9G20 has two SRAM areas, one starting at 0x00200000 and the other starting at 0x00300000. -# Both areas are 16 kB long. - -$_TARGETNAME configure -work-area-virt 0 -work-area-phys 0x00200000 -work-area-size 0x4000 -work-area-backup 1 -$_TARGETNAME configure -work-area-virt 0 -work-area-phys 0x00300000 -work-area-size 0x4000 -work-area-backup 1 - # If you don't want to execute built-in boot rom code (and there are good reasons at times not to do that) in the # AT91SAM9 family, the microcontroller is a lump on a log without initialization. Because this family has # some powerful features, we want to have a special function that handles "reset init". To do this we declare # an event handler where these special activities can take place. scan_chain -$_TARGETNAME configure -event reset-init {at91sam9g20_init} +$_TARGETNAME configure -event reset-init {at91sam9g20_reset_init} +$_TARGETNAME configure -event reset-start {at91sam9g20_reset_start} # NandFlash configuration and definition -# Future TBD + +nand device nandflash_cs3 at91sam9 $_TARGETNAME 0x40000000 0xfffffe800 +at91sam9 cle 0 22 +at91sam9 ale 0 21 +at91sam9 rdy_busy 0 0xfffff800 13 +at91sam9 ce 0 0xfffff800 14 proc read_register {register} { - set result "" - ocd_mem2array result 32 $register 1 - return $result(0) + return [read_memory $register 32 1] } -proc at91sam9g20_init { } { - +proc at91sam9g20_reset_start { } { + + # Make sure that the the jtag is running slow, since there are a number of different ways the board + # can be configured coming into this state that can cause communication problems with the jtag + # adapter. Also since this call can be made following a "reset init" where fast memory accesses + # are enabled, need to temporarily shut this down so that the RSTC_MR register can be written at slower + # jtag speed without causing GDB keep alive problem. + + arm7_9 fast_memory_access disable + adapter speed 2 ;# Slow-speed oscillator enabled at reset, so run jtag speed slow. + halt ;# Make sure processor is halted, or error will result in following steps. + wait_halt 10000 + mww 0xfffffd08 0xa5000501 ;# RSTC_MR : enable user reset. +} + +proc at91sam9g20_reset_init { } { + # At reset AT91SAM9G20 chip runs on slow clock (32.768 kHz). To shift over to a normal clock requires # a number of steps that must be carefully performed. The process outline below follows the # recommended procedure outlined in the AT91SAM9G20 technical manual. @@ -72,34 +67,31 @@ proc at91sam9g20_init { } { # means the master clock (MCLK) must be at or below 133 MHz or timing errors will occur. The processor # core can operate up to 400 MHz and therefore PCLK must be at or below this to function properly. - jtag_khz 2 # Slow-speed oscillator enabled at reset, so run jtag speed slow. - halt # Make sure processor is halted, or error will result in following steps. - mww 0xfffffd08 0xa5000501 # RSTC_MR : enable user reset. - mww 0xfffffd44 0x00008000 # WDT_MR : disable watchdog. + mww 0xfffffd44 0x00008000 ;# WDT_MR : disable watchdog. # Enable the main 18.432 MHz oscillator in CKGR_MOR register. # Wait for MOSCS in PMC_SR to assert indicating oscillator is again stable after change to CKGR_MOR. mww 0xfffffc20 0x00004001 - while { [expr [read_register 0xfffffc68] & 0x01] != 1 } { sleep 1 } + while { [expr {[read_register 0xfffffc68] & 0x01}] != 1 } { sleep 1 } # Set PLLA Register for 792.576 MHz (divider: bypass, multiplier: 43). # Wait for LOCKA signal in PMC_SR to assert indicating PLLA is stable. mww 0xfffffc28 0x202a3f01 - while { [expr [read_register 0xfffffc68] & 0x02] != 2 } { sleep 1 } + while { [expr {[read_register 0xfffffc68] & 0x02}] != 2 } { sleep 1 } # Set master system clock prescaler divide by 6 and processor clock divide by 2 in PMC_MCKR. # Wait for MCKRDY signal from PMC_SR to assert. mww 0xfffffc30 0x00000101 - while { [expr [read_register 0xfffffc68] & 0x08] != 8 } { sleep 1 } - + while { [expr {[read_register 0xfffffc68] & 0x08}] != 8 } { sleep 1 } + # Now change PMC_MCKR register to select PLLA. # Wait for MCKRDY signal from PMC_SR to assert. mww 0xfffffc30 0x00001302 - while { [expr [read_register 0xfffffc68] & 0x08] != 8 } { sleep 1 } + while { [expr {[read_register 0xfffffc68] & 0x08}] != 8 } { sleep 1 } # Processor and master clocks are now operating and stable at maximum frequency possible: # -> MCLK = 132.096 MHz @@ -107,11 +99,12 @@ proc at91sam9g20_init { } { # Switch over to adaptive clocking. - jtag_khz 0 + adapter speed 0 - # Enable faster DCC downloads. + # Enable faster DCC downloads and memory accesses. arm7_9 dcc_downloads enable + arm7_9 fast_memory_access enable # To be able to use external SDRAM, several peripheral configuration registers must # be modified. The first change is made to PIO_ASR to select peripheral functions @@ -129,16 +122,34 @@ proc at91sam9g20_init { } { # The AT91SAM9G20-EK evaluation board has built-in NandFlash. The exact physical timing characteristics # for the memory type used on the current board (MT29F2G08AACWP) can be established by setting - # four registers in order: SMC_SETUP3, SMC_PULSE3, SMC_CYCLE3, and SMC_MODE3. + # a number of registers. The first step involves setting up the general I/O pins on the processor + # to be able to interface and support the external memory. - mww 0xffffec30 0x00020002 - mww 0xffffec34 0x04040404 - mww 0xffffec38 0x00070007 - mww 0xffffec3c 0x00030003 + mww 0xfffffc10 0x00000010 ;# PMC_PCER : enable PIOC clock + mww 0xfffff800 0x00006000 ;# PIOC_PER : enable PIO function for 13(RDY/~BSY) and 14(~CS) + mww 0xfffff810 0x00004000 ;# PIOC_OER : enable output on 14 + mww 0xfffff814 0x00002000 ;# PIOC_ODR : disable output on 13 + mww 0xfffff830 0x00004000 ;# PIOC_SODR : set 14 to disable NAND - # Identify NandFlash bank 0. Disabled at the moment because a memory driver is not yet complete. + # The exact physical timing characteristics for the memory type used on the current board + # (MT29F2G08AACWP) can be established by setting four registers in order: SMC_SETUP3, + # SMC_PULSE3, SMC_CYCLE3, and SMC_MODE3. Computing the exact values of these registers + # is a little tedious to do here. If you have questions about how to do this, Atmel has + # a decent application note #6255B that covers this process. -# nand probe 0 + mww 0xffffec30 0x00020002 ;# SMC_SETUP3 : 2 clock cycle setup for NRD and NWE + mww 0xffffec34 0x04040404 ;# SMC_PULSE3 : 4 clock cycle pulse for all signals + mww 0xffffec38 0x00070006 ;# SMC_CYCLE3 : 7 clock cycle NRD and 6 NWE cycle + mww 0xffffec3C 0x00020003 ;# SMC_MODE3 : NRD and NWE control, no NWAIT, 8-bit DBW, + + mww 0xffffe800 0x00000001 ;# ECC_CR : reset the ECC parity registers + mww 0xffffe804 0x00000002 ;# ECC_MR : page size is 2112 words (word is 8 bits) + + # Identify NandFlash bank 0. + + nand probe nandflash_cs3 + + # The AT91SAM9G20-EK evaluation board has built-in serial data flash also. # Now setup SDRAM. This is tricky and configuration is very important for reliability! The current calculations # are based on 2 x Micron MT48LC16M16A2-75 memory (4 M x 16 bit x 4 banks). If you use this file as a reference @@ -154,7 +165,7 @@ proc at91sam9g20_init { } { # TRC = 9 cycles # TWR = 2 cycles # 9 column, 13 row, 4 banks - # refresh equal to or less then 7.8 us for commerical/industrial rated devices + # refresh equal to or less then 7.8 us for commercial/industrial rated devices # # Thus SDRAM_CR = 0xa6339279 @@ -201,4 +212,3 @@ proc at91sam9g20_init { } { mww 0xffffea04 0x0000039c } -