X-Git-Url: https://review.openocd.org/gitweb?p=openocd.git;a=blobdiff_plain;f=tcl%2Fboard%2Fat91sam9g20-ek.cfg;fp=tcl%2Fboard%2Fat91sam9g20-ek.cfg;h=03296c50e314287b868ed6c2515d82945d843bf7;hp=9e0413a1963d4f22ca2827c1959dd2acbf1a3fcd;hb=5df5e89cf3caf02dc6f49a5d3c8aa8b1349a1dbf;hpb=6d3cb807aaa60c4a4cd8ed49ae7860097bc1b3ce

diff --git a/tcl/board/at91sam9g20-ek.cfg b/tcl/board/at91sam9g20-ek.cfg
index 9e0413a196..03296c50e3 100644
--- a/tcl/board/at91sam9g20-ek.cfg
+++ b/tcl/board/at91sam9g20-ek.cfg
@@ -139,13 +139,13 @@ proc at91sam9g20_reset_init { } {
 	# (MT29F2G08AACWP) can be established by setting four registers in order:  SMC_SETUP3,
 	# SMC_PULSE3, SMC_CYCLE3, and SMC_MODE3.  Computing the exact values of these registers
 	# is a little tedious to do here.  If you have questions about how to do this, Atmel has
-	# a decent application note #6255B that covers this process. 
+	# a decent application note #6255B that covers this process.
 
 	mww 0xffffec30 0x00020002	;# SMC_SETUP3 : 2 clock cycle setup for NRD and NWE
 	mww 0xffffec34 0x04040404	;# SMC_PULSE3 : 4 clock cycle pulse for all signals
 	mww 0xffffec38 0x00070006	;# SMC_CYCLE3 : 7 clock cycle NRD and 6 NWE cycle
-	mww 0xffffec3C 0x00020003	;# SMC_MODE3 : NRD and NWE control, no NWAIT, 8-bit DBW, 
-   
+	mww 0xffffec3C 0x00020003	;# SMC_MODE3 : NRD and NWE control, no NWAIT, 8-bit DBW,
+
 	mww 0xffffe800 0x00000001	;# ECC_CR : reset the ECC parity registers
 	mww 0xffffe804 0x00000002	;# ECC_MR : page size is 2112 words (word is 8 bits)