X-Git-Url: https://review.openocd.org/gitweb?p=openocd.git;a=blobdiff_plain;f=tcl%2Fboard%2Fat91rm9200-dk.cfg;h=9a6f89e6fbaf89c2cbfdbae8b2de8b9d7d20a572;hp=900ee351d1167127c72620b77a3b3b6e8dbf3fae;hb=71af49ca7fb11b0bd0c1ba9578826f49288b68ef;hpb=86a7d813a165fda2816b8152342219b6c4ae2fc4

diff --git a/tcl/board/at91rm9200-dk.cfg b/tcl/board/at91rm9200-dk.cfg
index 900ee351d1..9a6f89e6fb 100644
--- a/tcl/board/at91rm9200-dk.cfg
+++ b/tcl/board/at91rm9200-dk.cfg
@@ -16,7 +16,7 @@ proc at91rm9200_dk_init { } {
     # Try to run at 1khz... Yea, that slow!
     # Chip is really running @ 32khz
     jtag_khz 8
-    
+
     mww 0xfffffc64 0xffffffff
     ##  disable all clocks but system clock
     mww 0xfffffc04 0xfffffffe
@@ -37,14 +37,14 @@ proc at91rm9200_dk_init { } {
     mww 0xfffffc30 0x202
     ## Sleep some - (go read)
     sleep 100
-    
+
     #========================================
     # CPU now runs at 180mhz
     # SYS runs at 60mhz.
     jtag_khz 40000
     #========================================
-    
-    
+
+
     ##  set memc for all memories
     mww 0xffffff60 0x02
     ##  program smc controller
@@ -55,7 +55,7 @@ proc at91rm9200_dk_init { } {
     mww 0xffffff80 0x02
     ##  touch sdram chip to make it work
     mww 0x20000000 0
-    ##  sdram controller mode register 
+    ##  sdram controller mode register
     mww 0xffffff90 0x04
     mww 0x20000000 0
     mww 0x20000000 0