X-Git-Url: https://review.openocd.org/gitweb?p=openocd.git;a=blobdiff_plain;f=src%2Ftarget%2Fxscale.h;h=a86edb2fba6a35bc091060ee475cf38ee2e89fb4;hp=6cfe76e65b2131a8cb24e1ee5321dd7b4cf7dfda;hb=f19ac83152b54a204b8148815a538d868973e1e1;hpb=8b994145b849c40b0a195c3fb332b9770b2f9097

diff --git a/src/target/xscale.h b/src/target/xscale.h
index 6cfe76e65b..a86edb2fba 100644
--- a/src/target/xscale.h
+++ b/src/target/xscale.h
@@ -16,88 +16,81 @@
  *   GNU General Public License for more details.                          *
  *                                                                         *
  *   You should have received a copy of the GNU General Public License     *
- *   along with this program; if not, write to the                         *
- *   Free Software Foundation, Inc.,                                       *
- *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
+ *   along with this program.  If not, see <http://www.gnu.org/licenses/>. *
  ***************************************************************************/
-#ifndef XSCALE_H
-#define XSCALE_H
 
-#include "armv4_5.h"
+#ifndef OPENOCD_TARGET_XSCALE_H
+#define OPENOCD_TARGET_XSCALE_H
+
+#include "arm.h"
 #include "armv4_5_mmu.h"
 #include "trace.h"
 
 #define	XSCALE_COMMON_MAGIC 0x58534341
 
-typedef struct xscale_jtag_s
-{
-	/* position in JTAG scan chain */
-	jtag_tap_t *tap;
-
-	/* IR length and instructions */
-	int ir_length;
-	uint32_t dbgrx;
-	uint32_t dbgtx;
-	uint32_t ldic;
-	uint32_t dcsr;
-} xscale_jtag_t;
-
-enum xscale_debug_reason
-{
+/* These four JTAG instructions are architecturally defined.
+ * Lengths are core-specific; originally 5 bits, later 7.
+ */
+#define XSCALE_DBGRX	0x02
+#define XSCALE_DBGTX	0x10
+#define XSCALE_LDIC	0x07
+#define XSCALE_SELDCSR	0x09
+
+/* Possible CPU types */
+#define	XSCALE_IXP4XX_PXA2XX	0x0
+#define	XSCALE_PXA3XX		0x4
+
+enum xscale_debug_reason {
 	XSCALE_DBG_REASON_GENERIC,
 	XSCALE_DBG_REASON_RESET,
 	XSCALE_DBG_REASON_TB_FULL,
 };
 
-enum xscale_trace_entry_type
-{
+enum xscale_trace_entry_type {
 	XSCALE_TRACE_MESSAGE = 0x0,
 	XSCALE_TRACE_ADDRESS = 0x1,
 };
 
-typedef struct xscale_trace_entry_s
-{
+struct xscale_trace_entry {
 	uint8_t data;
 	enum xscale_trace_entry_type type;
-} xscale_trace_entry_t;
+};
 
-typedef struct xscale_trace_data_s
-{
-	xscale_trace_entry_t *entries;
+struct xscale_trace_data {
+	struct xscale_trace_entry *entries;
 	int depth;
 	uint32_t chkpt0;
 	uint32_t chkpt1;
 	uint32_t last_instruction;
-	struct xscale_trace_data_s *next;
-} xscale_trace_data_t;
+	unsigned int num_checkpoints;
+	struct xscale_trace_data *next;
+};
 
-typedef struct xscale_trace_s
-{
-	trace_status_t capture_status;	/* current state of capture run */
-	struct image_s *image;					/* source for target opcodes */
-	xscale_trace_data_t *data;		/* linked list of collected trace data */
-	int buffer_enabled;				/* whether trace buffer is enabled */
-	int buffer_fill;				/* maximum number of trace runs to read (-1 for wrap-around) */
-	int pc_ok;
-	uint32_t current_pc;
-	armv4_5_state_t core_state;		/* current core state (ARM, Thumb, Jazelle) */
-} xscale_trace_t;
-
-typedef struct xscale_common_s
-{
-	int common_magic;
+enum trace_mode {
+	XSCALE_TRACE_DISABLED,
+	XSCALE_TRACE_FILL,
+	XSCALE_TRACE_WRAP
+};
 
-	/* XScale registers (CP15, DBG) */
-	reg_cache_t *reg_cache;
+struct xscale_trace {
+	struct image *image;					/* source for target opcodes */
+	struct xscale_trace_data *data;		/* linked list of collected trace data */
+	int buffer_fill;				/* maximum number of trace runs to read */
+	int fill_counter;				/* running count during trace collection */
+	enum trace_mode mode;
+	enum arm_state core_state;	/* current core state (ARM, Thumb) */
+};
 
-	/* pxa250, pxa255, pxa27x, ixp42x, ... */
-	char *variant;
+struct xscale_common {
+	/* armv4/5 common stuff */
+	struct arm arm;
 
-	xscale_jtag_t jtag_info;
+	int common_magic;
+
+	/* XScale registers (CP15, DBG) */
+	struct reg_cache *reg_cache;
 
 	/* current state of the debug handler */
-	int handler_installed;
-	int handler_running;
 	uint32_t handler_address;
 
 	/* target-endian buffers with exception vectors */
@@ -129,31 +122,32 @@ typedef struct xscale_common_s
 
 	uint8_t vector_catch;
 
-	xscale_trace_t trace;
+	struct xscale_trace trace;
 
 	int arch_debug_reason;
 
-	/* armv4/5 common stuff */
-	armv4_5_common_t armv4_5_common;
-
 	/* MMU/Caches */
-	armv4_5_mmu_common_t armv4_5_mmu;
+	struct armv4_5_mmu_common armv4_5_mmu;
 	uint32_t cp15_control_reg;
 
-	/* possible future enhancements that go beyond XScale common stuff */
-	void *arch_info;
-
 	int fast_memory_access;
-} xscale_common_t;
 
-typedef struct xscale_reg_s
+	/* CPU variant */
+	int xscale_variant;
+};
+
+static inline struct xscale_common *
+target_to_xscale(struct target *target)
 {
+	return container_of(target->arch_info, struct xscale_common, arm);
+}
+
+struct xscale_reg {
 	int dbg_handler_number;
-	target_t *target;
-} xscale_reg_t;
+	struct target *target;
+};
 
-enum
-{
+enum {
 	XSCALE_MAINID,		/* 0 */
 	XSCALE_CACHETYPE,
 	XSCALE_CTRL,
@@ -178,6 +172,17 @@ enum
 	XSCALE_TXRXCTRL,
 };
 
-#define ERROR_XSCALE_NO_TRACE_DATA	(-1500)
+#define ERROR_XSCALE_NO_TRACE_DATA	(-700)
+
+/* DCSR bit and field definitions */
+#define DCSR_TR	(1 << 16)
+#define DCSR_TU	(1 << 17)
+#define DCSR_TS	(1 << 18)
+#define DCSR_TA	(1 << 19)
+#define DCSR_TD	(1 << 20)
+#define DCSR_TI	(1 << 22)
+#define DCSR_TF	(1 << 23)
+#define DCSR_TRAP_MASK \
+	(DCSR_TF | DCSR_TI | DCSR_TD | DCSR_TA | DCSR_TS | DCSR_TU | DCSR_TR)
 
-#endif /* XSCALE_H */
+#endif /* OPENOCD_TARGET_XSCALE_H */