X-Git-Url: https://review.openocd.org/gitweb?p=openocd.git;a=blobdiff_plain;f=src%2Ftarget%2Fxscale.c;h=c3b8d3358822724130cb2109759da7be57c2021f;hp=022204705e1e4fdb3ba5cbbb454319398772ed81;hb=40580e2d71ac56131a5da7e5f67a0b63450e4f24;hpb=270f9aa0213e34b490b551be86dd4a5217cf0c35 diff --git a/src/target/xscale.c b/src/target/xscale.c index 022204705e..c3b8d33588 100644 --- a/src/target/xscale.c +++ b/src/target/xscale.c @@ -229,7 +229,7 @@ int xscale_jtag_set_instr(jtag_tap_t *tap, u32 new_instr) field.in_value = NULL; jtag_set_check_value(&field, tap->expected, tap->expected_mask, NULL); - jtag_add_ir_scan(1, &field, -1); + jtag_add_ir_scan(1, &field, TAP_INVALID); free(field.out_value); } @@ -252,7 +252,7 @@ int xscale_read_dcsr(target_t *target) u8 field2_check_value = 0x0; u8 field2_check_mask = 0x1; - jtag_add_end_state(TAP_PD); + jtag_add_end_state(TAP_DRPAUSE); xscale_jtag_set_instr(xscale->jtag_info.tap, xscale->jtag_info.dcsr); buf_set_u32(&field0, 1, 1, xscale->hold_rst); @@ -282,7 +282,7 @@ int xscale_read_dcsr(target_t *target) fields[2].in_value = NULL; jtag_set_check_value(fields+2, &field2_check_value, &field2_check_mask, NULL); - jtag_add_dr_scan(3, fields, -1); + jtag_add_dr_scan(3, fields, TAP_INVALID); if ((retval = jtag_execute_queue()) != ERROR_OK) { @@ -300,9 +300,9 @@ int xscale_read_dcsr(target_t *target) fields[1].out_value = xscale->reg_cache->reg_list[XSCALE_DCSR].value; fields[1].in_value = NULL; - jtag_add_end_state(TAP_RTI); + jtag_add_end_state(TAP_IDLE); - jtag_add_dr_scan(3, fields, -1); + jtag_add_dr_scan(3, fields, TAP_INVALID); /* DANGER!!! this must be here. It will make sure that the arguments * to jtag_set_check_value() does not go out of scope! */ @@ -318,7 +318,7 @@ int xscale_receive(target_t *target, u32 *buffer, int num_words) armv4_5_common_t *armv4_5 = target->arch_info; xscale_common_t *xscale = armv4_5->arch_info; - enum tap_state path[3]; + tap_state_t path[3]; scan_field_t fields[3]; u8 *field0 = malloc(num_words * 1); @@ -332,9 +332,9 @@ int xscale_receive(target_t *target, u32 *buffer, int num_words) int i; - path[0] = TAP_SDS; - path[1] = TAP_CD; - path[2] = TAP_SD; + path[0] = TAP_DRSELECT; + path[1] = TAP_DRCAPTURE; + path[2] = TAP_DRSHIFT; fields[0].tap = xscale->jtag_info.tap; fields[0].num_bits = 3; @@ -353,8 +353,6 @@ int xscale_receive(target_t *target, u32 *buffer, int num_words) fields[1].in_check_value = NULL; fields[1].in_check_mask = NULL; - - fields[2].tap = xscale->jtag_info.tap; fields[2].num_bits = 1; fields[2].out_value = NULL; @@ -362,9 +360,9 @@ int xscale_receive(target_t *target, u32 *buffer, int num_words) fields[2].in_value = NULL; jtag_set_check_value(fields+2, &field2_check_value, &field2_check_mask, NULL); - jtag_add_end_state(TAP_RTI); + jtag_add_end_state(TAP_IDLE); xscale_jtag_set_instr(xscale->jtag_info.tap, xscale->jtag_info.dbgtx); - jtag_add_runtest(1, -1); /* ensures that we're in the TAP_RTI state as the above could be a no-op */ + jtag_add_runtest(1, TAP_INVALID); /* ensures that we're in the TAP_IDLE state as the above could be a no-op */ /* repeat until all words have been collected */ int attempts=0; @@ -379,7 +377,7 @@ int xscale_receive(target_t *target, u32 *buffer, int num_words) fields[1].in_handler_priv = (u8*)&field1[i]; jtag_add_pathmove(3, path); - jtag_add_dr_scan(3, fields, TAP_RTI); + jtag_add_dr_scan(3, fields, TAP_IDLE); words_scheduled++; } @@ -429,8 +427,8 @@ int xscale_read_tx(target_t *target, int consume) { armv4_5_common_t *armv4_5 = target->arch_info; xscale_common_t *xscale = armv4_5->arch_info; - enum tap_state path[3]; - enum tap_state noconsume_path[6]; + tap_state_t path[3]; + tap_state_t noconsume_path[6]; int retval; struct timeval timeout, now; @@ -442,20 +440,20 @@ int xscale_read_tx(target_t *target, int consume) u8 field2_check_value = 0x0; u8 field2_check_mask = 0x1; - jtag_add_end_state(TAP_RTI); + jtag_add_end_state(TAP_IDLE); xscale_jtag_set_instr(xscale->jtag_info.tap, xscale->jtag_info.dbgtx); - path[0] = TAP_SDS; - path[1] = TAP_CD; - path[2] = TAP_SD; + path[0] = TAP_DRSELECT; + path[1] = TAP_DRCAPTURE; + path[2] = TAP_DRSHIFT; - noconsume_path[0] = TAP_SDS; - noconsume_path[1] = TAP_CD; - noconsume_path[2] = TAP_E1D; - noconsume_path[3] = TAP_PD; - noconsume_path[4] = TAP_E2D; - noconsume_path[5] = TAP_SD; + noconsume_path[0] = TAP_DRSELECT; + noconsume_path[1] = TAP_DRCAPTURE; + noconsume_path[2] = TAP_DREXIT1; + noconsume_path[3] = TAP_DRPAUSE; + noconsume_path[4] = TAP_DREXIT2; + noconsume_path[5] = TAP_DRSHIFT; fields[0].tap = xscale->jtag_info.tap; fields[0].num_bits = 3; @@ -474,8 +472,6 @@ int xscale_read_tx(target_t *target, int consume) fields[1].in_check_value = NULL; fields[1].in_check_mask = NULL; - - fields[2].tap = xscale->jtag_info.tap; fields[2].num_bits = 1; fields[2].out_value = NULL; @@ -499,7 +495,7 @@ int xscale_read_tx(target_t *target, int consume) jtag_add_pathmove(sizeof(noconsume_path)/sizeof(*noconsume_path), noconsume_path); } - jtag_add_dr_scan(3, fields, TAP_RTI); + jtag_add_dr_scan(3, fields, TAP_IDLE); if ((retval = jtag_execute_queue()) != ERROR_OK) { @@ -551,7 +547,7 @@ int xscale_write_rx(target_t *target) u8 field2_check_value = 0x0; u8 field2_check_mask = 0x1; - jtag_add_end_state(TAP_RTI); + jtag_add_end_state(TAP_IDLE); xscale_jtag_set_instr(xscale->jtag_info.tap, xscale->jtag_info.dbgrx); @@ -572,8 +568,6 @@ int xscale_write_rx(target_t *target) fields[1].in_check_value = NULL; fields[1].in_check_mask = NULL; - - fields[2].tap = xscale->jtag_info.tap; fields[2].num_bits = 1; fields[2].out_value = &field2; @@ -588,7 +582,7 @@ int xscale_write_rx(target_t *target) LOG_DEBUG("polling RX"); for (;;) { - jtag_add_dr_scan(3, fields, TAP_RTI); + jtag_add_dr_scan(3, fields, TAP_IDLE); if ((retval = jtag_execute_queue()) != ERROR_OK) { @@ -617,7 +611,7 @@ int xscale_write_rx(target_t *target) /* set rx_valid */ field2 = 0x1; - jtag_add_dr_scan(3, fields, TAP_RTI); + jtag_add_dr_scan(3, fields, TAP_IDLE); if ((retval = jtag_execute_queue()) != ERROR_OK) { @@ -640,7 +634,7 @@ int xscale_send(target_t *target, u8 *buffer, int count, int size) int done_count = 0; - jtag_add_end_state(TAP_RTI); + jtag_add_end_state(TAP_IDLE); xscale_jtag_set_instr(xscale->jtag_info.tap, xscale->jtag_info.dbgrx); @@ -683,7 +677,7 @@ int xscale_send(target_t *target, u8 *buffer, int count, int size) 3, bits, t, - TAP_RTI); + TAP_IDLE); buffer += size; } @@ -726,7 +720,7 @@ int xscale_write_dcsr(target_t *target, int hold_rst, int ext_dbg_brk) if (ext_dbg_brk != -1) xscale->external_debug_break = ext_dbg_brk; - jtag_add_end_state(TAP_RTI); + jtag_add_end_state(TAP_IDLE); xscale_jtag_set_instr(xscale->jtag_info.tap, xscale->jtag_info.dcsr); buf_set_u32(&field0, 1, 1, xscale->hold_rst); @@ -749,8 +743,6 @@ int xscale_write_dcsr(target_t *target, int hold_rst, int ext_dbg_brk) fields[1].in_check_value = NULL; fields[1].in_check_mask = NULL; - - fields[2].tap = xscale->jtag_info.tap; fields[2].num_bits = 1; fields[2].out_value = &field2; @@ -758,7 +750,7 @@ int xscale_write_dcsr(target_t *target, int hold_rst, int ext_dbg_brk) fields[2].in_value = NULL; jtag_set_check_value(fields+2, &field2_check_value, &field2_check_mask, NULL); - jtag_add_dr_scan(3, fields, -1); + jtag_add_dr_scan(3, fields, TAP_INVALID); if ((retval = jtag_execute_queue()) != ERROR_OK) { @@ -796,7 +788,7 @@ int xscale_load_ic(target_t *target, int mini, u32 va, u32 buffer[8]) LOG_DEBUG("loading miniIC at 0x%8.8x", va); - jtag_add_end_state(TAP_RTI); + jtag_add_end_state(TAP_IDLE); xscale_jtag_set_instr(xscale->jtag_info.tap, xscale->jtag_info.ldic); /* LDIC */ /* CMD is b010 for Main IC and b011 for Mini IC */ @@ -830,7 +822,7 @@ int xscale_load_ic(target_t *target, int mini, u32 va, u32 buffer[8]) fields[1].in_handler = NULL; fields[1].in_handler_priv = NULL; - jtag_add_dr_scan(2, fields, -1); + jtag_add_dr_scan(2, fields, TAP_INVALID); fields[0].num_bits = 32; fields[0].out_value = packet; @@ -842,7 +834,7 @@ int xscale_load_ic(target_t *target, int mini, u32 va, u32 buffer[8]) { buf_set_u32(packet, 0, 32, buffer[word]); cmd = parity(*((u32*)packet)); - jtag_add_dr_scan(2, fields, -1); + jtag_add_dr_scan(2, fields, TAP_INVALID); } jtag_execute_queue(); @@ -859,7 +851,7 @@ int xscale_invalidate_ic_line(target_t *target, u32 va) scan_field_t fields[2]; - jtag_add_end_state(TAP_RTI); + jtag_add_end_state(TAP_IDLE); xscale_jtag_set_instr(xscale->jtag_info.tap, xscale->jtag_info.ldic); /* LDIC */ /* CMD for invalidate IC line b000, bits [6:4] b000 */ @@ -888,7 +880,7 @@ int xscale_invalidate_ic_line(target_t *target, u32 va) fields[1].in_handler = NULL; fields[1].in_handler_priv = NULL; - jtag_add_dr_scan(2, fields, -1); + jtag_add_dr_scan(2, fields, TAP_INVALID); return ERROR_OK; } @@ -1458,17 +1450,18 @@ static int xscale_step_inner(struct target_s *target, int current, u32 address, armv4_5_common_t *armv4_5 = target->arch_info; xscale_common_t *xscale = armv4_5->arch_info; - u32 current_pc, next_pc; + u32 next_pc; int retval; int i; - target->debug_reason = DBG_REASON_SINGLESTEP; /* calculate PC of next instruction */ if ((retval = arm_simulate_step(target, &next_pc)) != ERROR_OK) { - u32 current_opcode; + u32 current_opcode, current_pc; + current_pc = buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32); + target_read_u32(target, current_pc, ¤t_opcode); LOG_ERROR("BUG: couldn't calculate PC of next instruction, current opcode was 0x%8.8x", current_opcode); return retval; @@ -1597,7 +1590,7 @@ int xscale_assert_reset(target_t *target) /* select DCSR instruction (set endstate to R-T-I to ensure we don't * end up in T-L-R, which would reset JTAG */ - jtag_add_end_state(TAP_RTI); + jtag_add_end_state(TAP_IDLE); xscale_jtag_set_instr(xscale->jtag_info.tap, xscale->jtag_info.dcsr); /* set Hold reset, Halt mode and Trap Reset */ @@ -1620,7 +1613,7 @@ int xscale_assert_reset(target_t *target) if (target->reset_halt) { - int retval; + int retval; if ((retval = target_halt(target))!=ERROR_OK) return retval; } @@ -1638,7 +1631,7 @@ int xscale_deassert_reset(target_t *target) u32 binary_size; u32 buf_cnt; - int i; + u32 i; int retval; breakpoint_t *breakpoint = target->breakpoints; @@ -1671,7 +1664,7 @@ int xscale_deassert_reset(target_t *target) /* wait 300ms; 150 and 100ms were not enough */ jtag_add_sleep(300*1000); - jtag_add_runtest(2030, TAP_RTI); + jtag_add_runtest(2030, TAP_IDLE); jtag_execute_queue(); /* set Hold reset, Halt mode and Trap Reset */ @@ -1718,7 +1711,7 @@ int xscale_deassert_reset(target_t *target) for (; buf_cnt < 32; buf_cnt += 4) { - cache_line[buf_cnt / 4] = 0xe1a08008; + cache_line[buf_cnt / 4] = 0xe1a08008; } /* only load addresses other than the reset vectors */ @@ -1734,7 +1727,7 @@ int xscale_deassert_reset(target_t *target) xscale_load_ic(target, 1, 0x0, xscale->low_vectors); xscale_load_ic(target, 1, 0xffff0000, xscale->high_vectors); - jtag_add_runtest(30, TAP_RTI); + jtag_add_runtest(30, TAP_IDLE); jtag_add_sleep(100000); @@ -1766,19 +1759,16 @@ int xscale_deassert_reset(target_t *target) jtag_add_reset(0, 0); } - return ERROR_OK; } int xscale_soft_reset_halt(struct target_s *target) { - return ERROR_OK; } int xscale_read_core_reg(struct target_s *target, int num, enum armv4_5_mode mode) { - return ERROR_OK; } @@ -1938,7 +1928,7 @@ int xscale_read_memory(struct target_s *target, u32 address, u32 size, u32 count armv4_5_common_t *armv4_5 = target->arch_info; xscale_common_t *xscale = armv4_5->arch_info; u32 *buf32; - int i; + u32 i; int retval; LOG_DEBUG("address: 0x%8.8x, size: 0x%8.8x, count: 0x%8.8x", address, size, count); @@ -2243,7 +2233,6 @@ int xscale_set_breakpoint(struct target_s *target, breakpoint_t *breakpoint) } return ERROR_OK; - } int xscale_add_breakpoint(struct target_s *target, breakpoint_t *breakpoint) @@ -2262,10 +2251,6 @@ int xscale_add_breakpoint(struct target_s *target, breakpoint_t *breakpoint) LOG_INFO("no breakpoint unit available for hardware breakpoint"); return ERROR_TARGET_RESOURCE_NOT_AVAILABLE; } - else - { - xscale->ibcr_available--; - } if ((breakpoint->length != 2) && (breakpoint->length != 4)) { @@ -2273,6 +2258,11 @@ int xscale_add_breakpoint(struct target_s *target, breakpoint_t *breakpoint) return ERROR_TARGET_RESOURCE_NOT_AVAILABLE; } + if (breakpoint->type == BKPT_HARD) + { + xscale->ibcr_available--; + } + return ERROR_OK; } @@ -2943,7 +2933,7 @@ int xscale_analyze_trace(target_t *target, command_context_t *cmd_ctx) (((instruction.type == ARM_B) || (instruction.type == ARM_BL) || (instruction.type == ARM_BLX)) && - (instruction.info.b_bl_bx_blx.target_address != -1))) + (instruction.info.b_bl_bx_blx.target_address != ~0UL))) { xscale->trace.current_pc = instruction.info.b_bl_bx_blx.target_address; } @@ -3040,7 +3030,6 @@ int xscale_init_target(struct command_context_s *cmd_ctx, struct target_s *targe int xscale_quit(void) { - return ERROR_OK; } @@ -3266,7 +3255,6 @@ static int xscale_virt2phys(struct target_s *target, u32 virtual, u32 *physical) int domain; u32 ap; - if ((retval = xscale_get_arch_pointers(target, &armv4_5, &xscale)) != ERROR_OK) { return retval; @@ -3294,7 +3282,6 @@ static int xscale_mmu(struct target_s *target, int *enabled) return ERROR_OK; } - int xscale_handle_mmu_command(command_context_t *cmd_ctx, char *cmd, char **args, int argc) { target_t *target = get_current_target(cmd_ctx); @@ -3380,7 +3367,7 @@ int xscale_handle_idcache_command(command_context_t *cmd_ctx, char *cmd, char ** command_print(cmd_ctx, "icache %s", (xscale->armv4_5_mmu.armv4_5_cache.i_cache_enabled) ? "enabled" : "disabled"); if (dcache) - command_print(cmd_ctx, "dcache %s", (xscale->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled) ? "enabled" : "disabled"); + command_print(cmd_ctx, "dcache %s", (xscale->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled) ? "enabled" : "disabled"); return ERROR_OK; }