X-Git-Url: https://review.openocd.org/gitweb?p=openocd.git;a=blobdiff_plain;f=src%2Ftarget%2Fxscale.c;h=82a2c571e843930403832c44eb16a5a5fa0d79a2;hp=d92dde1c640e61a5543a5c0ae57a628e8b585746;hb=5e837387aa7260518cf43f53b66ee917d8660802;hpb=3c2eabd20f5182c53f0bfb0c6f2a9f2595434e87 diff --git a/src/target/xscale.c b/src/target/xscale.c index d92dde1c64..82a2c571e8 100644 --- a/src/target/xscale.c +++ b/src/target/xscale.c @@ -2,9 +2,12 @@ * Copyright (C) 2006, 2007 by Dominic Rath * * Dominic.Rath@gmx.de * * * - * Copyright (C) 2007,2008 Øyvind Harboe * + * Copyright (C) 2007,2008 Øyvind Harboe * * oyvind.harboe@zylin.com * * * + * Copyright (C) 2009 Michael Schwingen * + * michael@schwingen.org * + * * * This program is free software; you can redistribute it and/or modify * * it under the terms of the GNU General Public License as published by * * the Free Software Foundation; either version 2 of the License, or * @@ -32,90 +35,41 @@ #include "time_support.h" #include "image.h" -/* cli handling */ -int xscale_register_commands(struct command_context_s *cmd_ctx); - -/* forward declarations */ -int xscale_target_create(struct target_s *target, Jim_Interp *interp); -int xscale_init_target(struct command_context_s *cmd_ctx, struct target_s *target); -int xscale_quit(void); - -int xscale_arch_state(struct target_s *target); -int xscale_poll(target_t *target); -int xscale_halt(target_t *target); -int xscale_resume(struct target_s *target, int current, uint32_t address, int handle_breakpoints, int debug_execution); -int xscale_step(struct target_s *target, int current, uint32_t address, int handle_breakpoints); -int xscale_debug_entry(target_t *target); -int xscale_restore_context(target_t *target); - -int xscale_assert_reset(target_t *target); -int xscale_deassert_reset(target_t *target); -int xscale_soft_reset_halt(struct target_s *target); - -int xscale_set_reg_u32(reg_t *reg, uint32_t value); - -int xscale_read_core_reg(struct target_s *target, int num, enum armv4_5_mode mode); -int xscale_write_core_reg(struct target_s *target, int num, enum armv4_5_mode mode, uint32_t value); - -int xscale_read_memory(struct target_s *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer); -int xscale_write_memory(struct target_s *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer); -int xscale_bulk_write_memory(target_t *target, uint32_t address, uint32_t count, uint8_t *buffer); - -int xscale_add_breakpoint(struct target_s *target, breakpoint_t *breakpoint); -int xscale_remove_breakpoint(struct target_s *target, breakpoint_t *breakpoint); -int xscale_set_breakpoint(struct target_s *target, breakpoint_t *breakpoint); -int xscale_unset_breakpoint(struct target_s *target, breakpoint_t *breakpoint); -int xscale_add_watchpoint(struct target_s *target, watchpoint_t *watchpoint); -int xscale_remove_watchpoint(struct target_s *target, watchpoint_t *watchpoint); -void xscale_enable_watchpoints(struct target_s *target); -void xscale_enable_breakpoints(struct target_s *target); -static int xscale_virt2phys(struct target_s *target, uint32_t virtual, uint32_t *physical); -static int xscale_mmu(struct target_s *target, int *enabled); - -int xscale_read_trace(target_t *target); - -target_type_t xscale_target = -{ - .name = "xscale", - - .poll = xscale_poll, - .arch_state = xscale_arch_state, - - .target_request_data = NULL, - - .halt = xscale_halt, - .resume = xscale_resume, - .step = xscale_step, - - .assert_reset = xscale_assert_reset, - .deassert_reset = xscale_deassert_reset, - .soft_reset_halt = xscale_soft_reset_halt, - .get_gdb_reg_list = armv4_5_get_gdb_reg_list, +/* + * Important XScale documents available as of October 2009 include: + * + * Intel XScale® Core Developer’s Manual, January 2004 + * Order Number: 273473-002 + * This has a chapter detailing debug facilities, and punts some + * details to chip-specific microarchitecture documentats. + * + * Hot-Debug for Intel XScale® Core Debug White Paper, May 2005 + * Document Number: 273539-005 + * Less detailed than the developer's manual, but summarizes those + * missing details (for most XScales) and gives LOTS of notes about + * debugger/handler interaction issues. Presents a simpler reset + * and load-handler sequence than the arch doc. (Note, OpenOCD + * doesn't currently support "Hot-Debug" as defined there.) + * + * Chip-specific microarchitecture documents may also be useful. + */ - .read_memory = xscale_read_memory, - .write_memory = xscale_write_memory, - .bulk_write_memory = xscale_bulk_write_memory, - .checksum_memory = arm7_9_checksum_memory, - .blank_check_memory = arm7_9_blank_check_memory, - .run_algorithm = armv4_5_run_algorithm, - - .add_breakpoint = xscale_add_breakpoint, - .remove_breakpoint = xscale_remove_breakpoint, - .add_watchpoint = xscale_add_watchpoint, - .remove_watchpoint = xscale_remove_watchpoint, - - .register_commands = xscale_register_commands, - .target_create = xscale_target_create, - .init_target = xscale_init_target, - .quit = xscale_quit, +/* forward declarations */ +static int xscale_resume(struct target_s *, int current, + uint32_t address, int handle_breakpoints, int debug_execution); +static int xscale_debug_entry(target_t *); +static int xscale_restore_context(target_t *); +static int xscale_get_reg(reg_t *reg); +static int xscale_set_reg(reg_t *reg, uint8_t *buf); +static int xscale_set_breakpoint(struct target_s *, breakpoint_t *); +static int xscale_set_watchpoint(struct target_s *, watchpoint_t *); +static int xscale_unset_breakpoint(struct target_s *, breakpoint_t *); +static int xscale_read_trace(target_t *); - .virt2phys = xscale_virt2phys, - .mmu = xscale_mmu -}; -char* xscale_reg_list[] = +static char *const xscale_reg_list[] = { "XSCALE_MAINID", /* 0 */ "XSCALE_CACHETYPE", @@ -141,7 +95,7 @@ char* xscale_reg_list[] = "XSCALE_TXRXCTRL", }; -xscale_reg_t xscale_reg_arch_info[] = +static const xscale_reg_t xscale_reg_arch_info[] = { {XSCALE_MAINID, NULL}, {XSCALE_CACHETYPE, NULL}, @@ -167,12 +121,21 @@ xscale_reg_t xscale_reg_arch_info[] = {-1, NULL}, /* TXRXCTRL implicit access via JTAG */ }; -int xscale_reg_arch_type = -1; +static int xscale_reg_arch_type = -1; -int xscale_get_reg(reg_t *reg); -int xscale_set_reg(reg_t *reg, uint8_t *buf); +/* convenience wrapper to access XScale specific registers */ +static int xscale_set_reg_u32(reg_t *reg, uint32_t value) +{ + uint8_t buf[4]; -int xscale_get_arch_pointers(target_t *target, armv4_5_common_t **armv4_5_p, xscale_common_t **xscale_p) + buf_set_u32(buf, 0, 32, value); + + return xscale_set_reg(reg, buf); +} + + +static int xscale_get_arch_pointers(target_t *target, + armv4_5_common_t **armv4_5_p, xscale_common_t **xscale_p) { armv4_5_common_t *armv4_5 = target->arch_info; xscale_common_t *xscale = armv4_5->arch_info; @@ -195,9 +158,9 @@ int xscale_get_arch_pointers(target_t *target, armv4_5_common_t **armv4_5_p, xsc return ERROR_OK; } -int xscale_jtag_set_instr(jtag_tap_t *tap, uint32_t new_instr) +static int xscale_jtag_set_instr(jtag_tap_t *tap, uint32_t new_instr) { - if (tap==NULL) + if (tap == NULL) return ERROR_FAIL; if (buf_get_u32(tap->cur_instr, 0, tap->ir_length) != new_instr) @@ -223,7 +186,7 @@ int xscale_jtag_set_instr(jtag_tap_t *tap, uint32_t new_instr) return ERROR_OK; } -int xscale_read_dcsr(target_t *target) +static int xscale_read_dcsr(target_t *target) { armv4_5_common_t *armv4_5 = target->arch_info; xscale_common_t *xscale = armv4_5->arch_info; @@ -239,24 +202,23 @@ int xscale_read_dcsr(target_t *target) uint8_t field2_check_mask = 0x1; jtag_set_end_state(TAP_DRPAUSE); - xscale_jtag_set_instr(xscale->jtag_info.tap, xscale->jtag_info.dcsr); + xscale_jtag_set_instr(target->tap, XSCALE_SELDCSR); buf_set_u32(&field0, 1, 1, xscale->hold_rst); buf_set_u32(&field0, 2, 1, xscale->external_debug_break); - fields[0].tap = xscale->jtag_info.tap; + fields[0].tap = target->tap; fields[0].num_bits = 3; fields[0].out_value = &field0; uint8_t tmp; fields[0].in_value = &tmp; - fields[1].tap = xscale->jtag_info.tap; + fields[1].tap = target->tap; fields[1].num_bits = 32; fields[1].out_value = NULL; fields[1].in_value = xscale->reg_cache->reg_list[XSCALE_DCSR].value; - - fields[2].tap = xscale->jtag_info.tap; + fields[2].tap = target->tap; fields[2].num_bits = 1; fields[2].out_value = &field2; uint8_t tmp2; @@ -264,8 +226,8 @@ int xscale_read_dcsr(target_t *target) jtag_add_dr_scan(3, fields, jtag_get_end_state()); - jtag_check_value_mask(fields+0, &field0_check_value, &field0_check_mask); - jtag_check_value_mask(fields+2, &field2_check_value, &field2_check_mask); + jtag_check_value_mask(fields + 0, &field0_check_value, &field0_check_mask); + jtag_check_value_mask(fields + 2, &field2_check_value, &field2_check_mask); if ((retval = jtag_execute_queue()) != ERROR_OK) { @@ -293,23 +255,20 @@ int xscale_read_dcsr(target_t *target) } -static void xscale_getbuf(uint8_t *in) +static void xscale_getbuf(jtag_callback_data_t arg) { - *((uint32_t *)in)=buf_get_u32(in, 0, 32); + uint8_t *in = (uint8_t *)arg; + *((uint32_t *)in) = buf_get_u32(in, 0, 32); } -int xscale_receive(target_t *target, uint32_t *buffer, int num_words) +static int xscale_receive(target_t *target, uint32_t *buffer, int num_words) { - if (num_words==0) + if (num_words == 0) return ERROR_INVALID_ARGUMENTS; - int retval=ERROR_OK; - armv4_5_common_t *armv4_5 = target->arch_info; - xscale_common_t *xscale = armv4_5->arch_info; - + int retval = ERROR_OK; tap_state_t path[3]; scan_field_t fields[3]; - uint8_t *field0 = malloc(num_words * 1); uint8_t field0_check_value = 0x2; uint8_t field0_check_mask = 0x6; @@ -325,20 +284,20 @@ int xscale_receive(target_t *target, uint32_t *buffer, int num_words) path[1] = TAP_DRCAPTURE; path[2] = TAP_DRSHIFT; - fields[0].tap = xscale->jtag_info.tap; + fields[0].tap = target->tap; fields[0].num_bits = 3; fields[0].out_value = NULL; fields[0].in_value = NULL; fields[0].check_value = &field0_check_value; fields[0].check_mask = &field0_check_mask; - fields[1].tap = xscale->jtag_info.tap; + fields[1].tap = target->tap; fields[1].num_bits = 32; fields[1].out_value = NULL; fields[1].check_value = NULL; fields[1].check_mask = NULL; - fields[2].tap = xscale->jtag_info.tap; + fields[2].tap = target->tap; fields[2].num_bits = 1; fields[2].out_value = NULL; fields[2].in_value = NULL; @@ -346,11 +305,11 @@ int xscale_receive(target_t *target, uint32_t *buffer, int num_words) fields[2].check_mask = &field2_check_mask; jtag_set_end_state(TAP_IDLE); - xscale_jtag_set_instr(xscale->jtag_info.tap, xscale->jtag_info.dbgtx); + xscale_jtag_set_instr(target->tap, XSCALE_DBGTX); jtag_add_runtest(1, jtag_get_end_state()); /* ensures that we're in the TAP_IDLE state as the above could be a no-op */ /* repeat until all words have been collected */ - int attempts=0; + int attempts = 0; while (words_done < num_words) { /* schedule reads */ @@ -361,11 +320,11 @@ int xscale_receive(target_t *target, uint32_t *buffer, int num_words) jtag_add_pathmove(3, path); - fields[1].in_value = (uint8_t *)(field1+i); + fields[1].in_value = (uint8_t *)(field1 + i); jtag_add_dr_scan_check(3, fields, jtag_set_end_state(TAP_IDLE)); - jtag_add_callback(xscale_getbuf, (uint8_t *)(field1+i)); + jtag_add_callback(xscale_getbuf, (jtag_callback_data_t)(field1 + i)); words_scheduled++; } @@ -385,18 +344,18 @@ int xscale_receive(target_t *target, uint32_t *buffer, int num_words) int j; for (j = i; j < num_words - 1; j++) { - field0[j] = field0[j+1]; - field1[j] = field1[j+1]; + field0[j] = field0[j + 1]; + field1[j] = field1[j + 1]; } words_scheduled--; } } - if (words_scheduled==0) + if (words_scheduled == 0) { if (attempts++==1000) { LOG_ERROR("Failed to receiving data from debug handler after 1000 attempts"); - retval=ERROR_TARGET_TIMEOUT; + retval = ERROR_TARGET_TIMEOUT; break; } } @@ -412,7 +371,7 @@ int xscale_receive(target_t *target, uint32_t *buffer, int num_words) return retval; } -int xscale_read_tx(target_t *target, int consume) +static int xscale_read_tx(target_t *target, int consume) { armv4_5_common_t *armv4_5 = target->arch_info; xscale_common_t *xscale = armv4_5->arch_info; @@ -431,7 +390,7 @@ int xscale_read_tx(target_t *target, int consume) jtag_set_end_state(TAP_IDLE); - xscale_jtag_set_instr(xscale->jtag_info.tap, xscale->jtag_info.dbgtx); + xscale_jtag_set_instr(target->tap, XSCALE_DBGTX); path[0] = TAP_DRSELECT; path[1] = TAP_DRCAPTURE; @@ -444,18 +403,17 @@ int xscale_read_tx(target_t *target, int consume) noconsume_path[4] = TAP_DREXIT2; noconsume_path[5] = TAP_DRSHIFT; - fields[0].tap = xscale->jtag_info.tap; + fields[0].tap = target->tap; fields[0].num_bits = 3; fields[0].out_value = NULL; fields[0].in_value = &field0_in; - fields[1].tap = xscale->jtag_info.tap; + fields[1].tap = target->tap; fields[1].num_bits = 32; fields[1].out_value = NULL; fields[1].in_value = xscale->reg_cache->reg_list[XSCALE_TX].value; - - fields[2].tap = xscale->jtag_info.tap; + fields[2].tap = target->tap; fields[2].num_bits = 1; fields[2].out_value = NULL; uint8_t tmp; @@ -479,8 +437,8 @@ int xscale_read_tx(target_t *target, int consume) jtag_add_dr_scan(3, fields, jtag_set_end_state(TAP_IDLE)); - jtag_check_value_mask(fields+0, &field0_check_value, &field0_check_mask); - jtag_check_value_mask(fields+2, &field2_check_value, &field2_check_mask); + jtag_check_value_mask(fields + 0, &field0_check_value, &field0_check_mask); + jtag_check_value_mask(fields + 2, &field2_check_value, &field2_check_mask); if ((retval = jtag_execute_queue()) != ERROR_OK) { @@ -498,7 +456,7 @@ int xscale_read_tx(target_t *target, int consume) { goto done; } - if (debug_level>=3) + if (debug_level >= 3) { LOG_DEBUG("waiting 100ms"); alive_sleep(100); /* avoid flooding the logs */ @@ -515,7 +473,7 @@ int xscale_read_tx(target_t *target, int consume) return ERROR_OK; } -int xscale_write_rx(target_t *target) +static int xscale_write_rx(target_t *target) { armv4_5_common_t *armv4_5 = target->arch_info; xscale_common_t *xscale = armv4_5->arch_info; @@ -534,20 +492,19 @@ int xscale_write_rx(target_t *target) jtag_set_end_state(TAP_IDLE); - xscale_jtag_set_instr(xscale->jtag_info.tap, xscale->jtag_info.dbgrx); + xscale_jtag_set_instr(target->tap, XSCALE_DBGRX); - fields[0].tap = xscale->jtag_info.tap; + fields[0].tap = target->tap; fields[0].num_bits = 3; fields[0].out_value = &field0_out; fields[0].in_value = &field0_in; - fields[1].tap = xscale->jtag_info.tap; + fields[1].tap = target->tap; fields[1].num_bits = 32; fields[1].out_value = xscale->reg_cache->reg_list[XSCALE_RX].value; fields[1].in_value = NULL; - - fields[2].tap = xscale->jtag_info.tap; + fields[2].tap = target->tap; fields[2].num_bits = 1; fields[2].out_value = &field2; uint8_t tmp; @@ -562,8 +519,8 @@ int xscale_write_rx(target_t *target) { jtag_add_dr_scan(3, fields, jtag_set_end_state(TAP_IDLE)); - jtag_check_value_mask(fields+0, &field0_check_value, &field0_check_mask); - jtag_check_value_mask(fields+2, &field2_check_value, &field2_check_mask); + jtag_check_value_mask(fields + 0, &field0_check_value, &field0_check_mask); + jtag_check_value_mask(fields + 2, &field2_check_value, &field2_check_mask); if ((retval = jtag_execute_queue()) != ERROR_OK) { @@ -579,7 +536,7 @@ int xscale_write_rx(target_t *target) } if (!(field0_in & 1)) goto done; - if (debug_level>=3) + if (debug_level >= 3) { LOG_DEBUG("waiting 100ms"); alive_sleep(100); /* avoid flooding the logs */ @@ -604,20 +561,16 @@ int xscale_write_rx(target_t *target) } /* send count elements of size byte to the debug handler */ -int xscale_send(target_t *target, uint8_t *buffer, int count, int size) +static int xscale_send(target_t *target, uint8_t *buffer, int count, int size) { - armv4_5_common_t *armv4_5 = target->arch_info; - xscale_common_t *xscale = armv4_5->arch_info; uint32_t t[3]; int bits[3]; - int retval; - int done_count = 0; jtag_set_end_state(TAP_IDLE); - xscale_jtag_set_instr(xscale->jtag_info.tap, xscale->jtag_info.dbgrx); + xscale_jtag_set_instr(target->tap, XSCALE_DBGRX); bits[0]=3; t[0]=0; @@ -654,7 +607,7 @@ int xscale_send(target_t *target, uint8_t *buffer, int count, int size) LOG_ERROR("BUG: size neither 4, 2 nor 1"); exit(-1); } - jtag_add_dr_out(xscale->jtag_info.tap, + jtag_add_dr_out(target->tap, 3, bits, t, @@ -671,7 +624,7 @@ int xscale_send(target_t *target, uint8_t *buffer, int count, int size) return ERROR_OK; } -int xscale_send_u32(target_t *target, uint32_t value) +static int xscale_send_u32(target_t *target, uint32_t value) { armv4_5_common_t *armv4_5 = target->arch_info; xscale_common_t *xscale = armv4_5->arch_info; @@ -680,7 +633,7 @@ int xscale_send_u32(target_t *target, uint32_t value) return xscale_write_rx(target); } -int xscale_write_dcsr(target_t *target, int hold_rst, int ext_dbg_brk) +static int xscale_write_dcsr(target_t *target, int hold_rst, int ext_dbg_brk) { armv4_5_common_t *armv4_5 = target->arch_info; xscale_common_t *xscale = armv4_5->arch_info; @@ -702,24 +655,23 @@ int xscale_write_dcsr(target_t *target, int hold_rst, int ext_dbg_brk) xscale->external_debug_break = ext_dbg_brk; jtag_set_end_state(TAP_IDLE); - xscale_jtag_set_instr(xscale->jtag_info.tap, xscale->jtag_info.dcsr); + xscale_jtag_set_instr(target->tap, XSCALE_SELDCSR); buf_set_u32(&field0, 1, 1, xscale->hold_rst); buf_set_u32(&field0, 2, 1, xscale->external_debug_break); - fields[0].tap = xscale->jtag_info.tap; + fields[0].tap = target->tap; fields[0].num_bits = 3; fields[0].out_value = &field0; uint8_t tmp; fields[0].in_value = &tmp; - fields[1].tap = xscale->jtag_info.tap; + fields[1].tap = target->tap; fields[1].num_bits = 32; fields[1].out_value = xscale->reg_cache->reg_list[XSCALE_DCSR].value; fields[1].in_value = NULL; - - fields[2].tap = xscale->jtag_info.tap; + fields[2].tap = target->tap; fields[2].num_bits = 1; fields[2].out_value = &field2; uint8_t tmp2; @@ -727,8 +679,8 @@ int xscale_write_dcsr(target_t *target, int hold_rst, int ext_dbg_brk) jtag_add_dr_scan(3, fields, jtag_get_end_state()); - jtag_check_value_mask(fields+0, &field0_check_value, &field0_check_mask); - jtag_check_value_mask(fields+2, &field2_check_value, &field2_check_mask); + jtag_check_value_mask(fields + 0, &field0_check_value, &field0_check_mask); + jtag_check_value_mask(fields + 2, &field2_check_value, &field2_check_mask); if ((retval = jtag_execute_queue()) != ERROR_OK) { @@ -743,65 +695,52 @@ int xscale_write_dcsr(target_t *target, int hold_rst, int ext_dbg_brk) } /* parity of the number of bits 0 if even; 1 if odd. for 32 bit words */ -unsigned int parity (unsigned int v) +static unsigned int parity (unsigned int v) { - unsigned int ov = v; + // unsigned int ov = v; v ^= v >> 16; v ^= v >> 8; v ^= v >> 4; v &= 0xf; - LOG_DEBUG("parity of 0x%x is %i", ov, (0x6996 >> v) & 1); + // LOG_DEBUG("parity of 0x%x is %i", ov, (0x6996 >> v) & 1); return (0x6996 >> v) & 1; } -int xscale_load_ic(target_t *target, int mini, uint32_t va, uint32_t buffer[8]) +static int xscale_load_ic(target_t *target, uint32_t va, uint32_t buffer[8]) { - armv4_5_common_t *armv4_5 = target->arch_info; - xscale_common_t *xscale = armv4_5->arch_info; uint8_t packet[4]; uint8_t cmd; int word; - scan_field_t fields[2]; - LOG_DEBUG("loading miniIC at 0x%8.8x", va); + LOG_DEBUG("loading miniIC at 0x%8.8" PRIx32 "", va); + /* LDIC into IR */ jtag_set_end_state(TAP_IDLE); - xscale_jtag_set_instr(xscale->jtag_info.tap, xscale->jtag_info.ldic); /* LDIC */ + xscale_jtag_set_instr(target->tap, XSCALE_LDIC); - /* CMD is b010 for Main IC and b011 for Mini IC */ - if (mini) - buf_set_u32(&cmd, 0, 3, 0x3); - else - buf_set_u32(&cmd, 0, 3, 0x2); - - buf_set_u32(&cmd, 3, 3, 0x0); + /* CMD is b011 to load a cacheline into the Mini ICache. + * Loading into the main ICache is deprecated, and unused. + * It's followed by three zero bits, and 27 address bits. + */ + buf_set_u32(&cmd, 0, 6, 0x3); /* virtual address of desired cache line */ buf_set_u32(packet, 0, 27, va >> 5); - fields[0].tap = xscale->jtag_info.tap; + fields[0].tap = target->tap; fields[0].num_bits = 6; fields[0].out_value = &cmd; - fields[0].in_value = NULL; - - - - - fields[1].tap = xscale->jtag_info.tap; + fields[1].tap = target->tap; fields[1].num_bits = 27; fields[1].out_value = packet; - fields[1].in_value = NULL; - - - - jtag_add_dr_scan(2, fields, jtag_get_end_state()); + /* rest of packet is a cacheline: 8 instructions, with parity */ fields[0].num_bits = 32; fields[0].out_value = packet; @@ -819,22 +758,17 @@ int xscale_load_ic(target_t *target, int mini, uint32_t va, uint32_t buffer[8]) jtag_add_dr_scan(2, fields, jtag_get_end_state()); } - jtag_execute_queue(); - - return ERROR_OK; + return jtag_execute_queue(); } -int xscale_invalidate_ic_line(target_t *target, uint32_t va) +static int xscale_invalidate_ic_line(target_t *target, uint32_t va) { - armv4_5_common_t *armv4_5 = target->arch_info; - xscale_common_t *xscale = armv4_5->arch_info; uint8_t packet[4]; uint8_t cmd; - scan_field_t fields[2]; jtag_set_end_state(TAP_IDLE); - xscale_jtag_set_instr(xscale->jtag_info.tap, xscale->jtag_info.ldic); /* LDIC */ + xscale_jtag_set_instr(target->tap, XSCALE_LDIC); /* CMD for invalidate IC line b000, bits [6:4] b000 */ buf_set_u32(&cmd, 0, 6, 0x0); @@ -842,32 +776,22 @@ int xscale_invalidate_ic_line(target_t *target, uint32_t va) /* virtual address of desired cache line */ buf_set_u32(packet, 0, 27, va >> 5); - fields[0].tap = xscale->jtag_info.tap; + fields[0].tap = target->tap; fields[0].num_bits = 6; fields[0].out_value = &cmd; - fields[0].in_value = NULL; - - - - - fields[1].tap = xscale->jtag_info.tap; + fields[1].tap = target->tap; fields[1].num_bits = 27; fields[1].out_value = packet; - fields[1].in_value = NULL; - - - - jtag_add_dr_scan(2, fields, jtag_get_end_state()); return ERROR_OK; } -int xscale_update_vectors(target_t *target) +static int xscale_update_vectors(target_t *target) { armv4_5_common_t *armv4_5 = target->arch_info; xscale_common_t *xscale = armv4_5->arch_info; @@ -885,10 +809,10 @@ int xscale_update_vectors(target_t *target) } else { - retval=target_read_u32(target, 0xffff0000 + 4*i, &xscale->high_vectors[i]); + retval = target_read_u32(target, 0xffff0000 + 4*i, &xscale->high_vectors[i]); if (retval == ERROR_TARGET_TIMEOUT) return retval; - if (retval!=ERROR_OK) + if (retval != ERROR_OK) { /* Some of these reads will fail as part of normal execution */ xscale->high_vectors[i] = ARMV4_5_B(0xfffffe, 0); @@ -904,10 +828,10 @@ int xscale_update_vectors(target_t *target) } else { - retval=target_read_u32(target, 0x0 + 4*i, &xscale->low_vectors[i]); + retval = target_read_u32(target, 0x0 + 4*i, &xscale->low_vectors[i]); if (retval == ERROR_TARGET_TIMEOUT) return retval; - if (retval!=ERROR_OK) + if (retval != ERROR_OK) { /* Some of these reads will fail as part of normal execution */ xscale->low_vectors[i] = ARMV4_5_B(0xfffffe, 0); @@ -926,23 +850,23 @@ int xscale_update_vectors(target_t *target) xscale_invalidate_ic_line(target, 0x0); xscale_invalidate_ic_line(target, 0xffff0000); - xscale_load_ic(target, 1, 0x0, xscale->low_vectors); - xscale_load_ic(target, 1, 0xffff0000, xscale->high_vectors); + xscale_load_ic(target, 0x0, xscale->low_vectors); + xscale_load_ic(target, 0xffff0000, xscale->high_vectors); return ERROR_OK; } -int xscale_arch_state(struct target_s *target) +static int xscale_arch_state(struct target_s *target) { armv4_5_common_t *armv4_5 = target->arch_info; xscale_common_t *xscale = armv4_5->arch_info; - char *state[] = + static const char *state[] = { "disabled", "enabled" }; - char *arch_dbg_reason[] = + static const char *arch_dbg_reason[] = { "", "\n(processor reset)", "\n(trace buffer full)" }; @@ -954,11 +878,11 @@ int xscale_arch_state(struct target_s *target) } LOG_USER("target halted in %s state due to %s, current mode: %s\n" - "cpsr: 0x%8.8x pc: 0x%8.8x\n" + "cpsr: 0x%8.8" PRIx32 " pc: 0x%8.8" PRIx32 "\n" "MMU: %s, D-Cache: %s, I-Cache: %s" "%s", armv4_5_state_strings[armv4_5->core_state], - Jim_Nvp_value2name_simple( nvp_target_debug_reason, target->debug_reason )->name , + Jim_Nvp_value2name_simple(nvp_target_debug_reason, target->debug_reason)->name , armv4_5_mode_strings[armv4_5_mode_to_number(armv4_5->core_mode)], buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32), buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32), @@ -970,9 +894,9 @@ int xscale_arch_state(struct target_s *target) return ERROR_OK; } -int xscale_poll(target_t *target) +static int xscale_poll(target_t *target) { - int retval=ERROR_OK; + int retval = ERROR_OK; armv4_5_common_t *armv4_5 = target->arch_info; xscale_common_t *xscale = armv4_5->arch_info; @@ -1014,7 +938,7 @@ int xscale_poll(target_t *target) return retval; } -int xscale_debug_entry(target_t *target) +static int xscale_debug_entry(target_t *target) { armv4_5_common_t *armv4_5 = target->arch_info; xscale_common_t *xscale = armv4_5->arch_info; @@ -1027,24 +951,24 @@ int xscale_debug_entry(target_t *target) /* clear external dbg break (will be written on next DCSR read) */ xscale->external_debug_break = 0; - if ((retval=xscale_read_dcsr(target))!=ERROR_OK) + if ((retval = xscale_read_dcsr(target)) != ERROR_OK) return retval; /* get r0, pc, r1 to r7 and cpsr */ - if ((retval=xscale_receive(target, buffer, 10))!=ERROR_OK) + if ((retval = xscale_receive(target, buffer, 10)) != ERROR_OK) return retval; /* move r0 from buffer to register cache */ buf_set_u32(armv4_5->core_cache->reg_list[0].value, 0, 32, buffer[0]); - armv4_5->core_cache->reg_list[15].dirty = 1; - armv4_5->core_cache->reg_list[15].valid = 1; - LOG_DEBUG("r0: 0x%8.8x", buffer[0]); + armv4_5->core_cache->reg_list[0].dirty = 1; + armv4_5->core_cache->reg_list[0].valid = 1; + LOG_DEBUG("r0: 0x%8.8" PRIx32 "", buffer[0]); /* move pc from buffer to register cache */ buf_set_u32(armv4_5->core_cache->reg_list[15].value, 0, 32, buffer[1]); armv4_5->core_cache->reg_list[15].dirty = 1; armv4_5->core_cache->reg_list[15].valid = 1; - LOG_DEBUG("pc: 0x%8.8x", buffer[1]); + LOG_DEBUG("pc: 0x%8.8" PRIx32 "", buffer[1]); /* move data from buffer to register cache */ for (i = 1; i <= 7; i++) @@ -1052,13 +976,13 @@ int xscale_debug_entry(target_t *target) buf_set_u32(armv4_5->core_cache->reg_list[i].value, 0, 32, buffer[1 + i]); armv4_5->core_cache->reg_list[i].dirty = 1; armv4_5->core_cache->reg_list[i].valid = 1; - LOG_DEBUG("r%i: 0x%8.8x", i, buffer[i + 1]); + LOG_DEBUG("r%i: 0x%8.8" PRIx32 "", i, buffer[i + 1]); } buf_set_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32, buffer[9]); armv4_5->core_cache->reg_list[ARMV4_5_CPSR].dirty = 1; armv4_5->core_cache->reg_list[ARMV4_5_CPSR].valid = 1; - LOG_DEBUG("cpsr: 0x%8.8x", buffer[9]); + LOG_DEBUG("cpsr: 0x%8.8" PRIx32 "", buffer[9]); armv4_5->core_mode = buffer[9] & 0x1f; if (armv4_5_mode_to_number(armv4_5->core_mode) == -1) @@ -1144,7 +1068,7 @@ int xscale_debug_entry(target_t *target) xscale->arch_debug_reason = XSCALE_DBG_REASON_TB_FULL; pc -= 4; break; - case 0x7: /* Reserved */ + case 0x7: /* Reserved (may flag Hot-Debug support) */ default: LOG_ERROR("Method of Entry is 'Reserved'"); exit(-1); @@ -1195,13 +1119,13 @@ int xscale_debug_entry(target_t *target) return ERROR_OK; } -int xscale_halt(target_t *target) +static int xscale_halt(target_t *target) { armv4_5_common_t *armv4_5 = target->arch_info; xscale_common_t *xscale = armv4_5->arch_info; LOG_DEBUG("target->state: %s", - Jim_Nvp_value2name_simple( nvp_target_state, target->state )->name); + target_state_name(target)); if (target->state == TARGET_HALTED) { @@ -1230,7 +1154,7 @@ int xscale_halt(target_t *target) return ERROR_OK; } -int xscale_enable_single_step(struct target_s *target, uint32_t next_pc) +static int xscale_enable_single_step(struct target_s *target, uint32_t next_pc) { armv4_5_common_t *armv4_5 = target->arch_info; xscale_common_t *xscale= armv4_5->arch_info; @@ -1252,26 +1176,52 @@ int xscale_enable_single_step(struct target_s *target, uint32_t next_pc) } } - if ((retval=xscale_set_reg_u32(ibcr0, next_pc | 0x1))!=ERROR_OK) + if ((retval = xscale_set_reg_u32(ibcr0, next_pc | 0x1)) != ERROR_OK) return retval; return ERROR_OK; } -int xscale_disable_single_step(struct target_s *target) +static int xscale_disable_single_step(struct target_s *target) { armv4_5_common_t *armv4_5 = target->arch_info; xscale_common_t *xscale= armv4_5->arch_info; reg_t *ibcr0 = &xscale->reg_cache->reg_list[XSCALE_IBCR0]; int retval; - if ((retval=xscale_set_reg_u32(ibcr0, 0x0))!=ERROR_OK) + if ((retval = xscale_set_reg_u32(ibcr0, 0x0)) != ERROR_OK) return retval; return ERROR_OK; } -int xscale_resume(struct target_s *target, int current, uint32_t address, int handle_breakpoints, int debug_execution) +static void xscale_enable_watchpoints(struct target_s *target) +{ + watchpoint_t *watchpoint = target->watchpoints; + + while (watchpoint) + { + if (watchpoint->set == 0) + xscale_set_watchpoint(target, watchpoint); + watchpoint = watchpoint->next; + } +} + +static void xscale_enable_breakpoints(struct target_s *target) +{ + breakpoint_t *breakpoint = target->breakpoints; + + /* set any pending breakpoints */ + while (breakpoint) + { + if (breakpoint->set == 0) + xscale_set_breakpoint(target, breakpoint); + breakpoint = breakpoint->next; + } +} + +static int xscale_resume(struct target_s *target, int current, + uint32_t address, int handle_breakpoints, int debug_execution) { armv4_5_common_t *armv4_5 = target->arch_info; xscale_common_t *xscale= armv4_5->arch_info; @@ -1296,7 +1246,7 @@ int xscale_resume(struct target_s *target, int current, uint32_t address, int ha } /* update vector tables */ - if ((retval=xscale_update_vectors(target))!=ERROR_OK) + if ((retval = xscale_update_vectors(target)) != ERROR_OK) return retval; /* current = 1: continue on current pc, otherwise continue at
*/ @@ -1320,7 +1270,7 @@ int xscale_resume(struct target_s *target, int current, uint32_t address, int ha uint32_t next_pc; /* there's a breakpoint at the current PC, we have to step over it */ - LOG_DEBUG("unset breakpoint at 0x%8.8x", breakpoint->address); + LOG_DEBUG("unset breakpoint at 0x%8.8" PRIx32 "", breakpoint->address); xscale_unset_breakpoint(target, breakpoint); /* calculate PC of next instruction */ @@ -1328,7 +1278,7 @@ int xscale_resume(struct target_s *target, int current, uint32_t address, int ha { uint32_t current_opcode; target_read_u32(target, current_pc, ¤t_opcode); - LOG_ERROR("BUG: couldn't calculate PC of next instruction, current opcode was 0x%8.8x", current_opcode); + LOG_ERROR("BUG: couldn't calculate PC of next instruction, current opcode was 0x%8.8" PRIx32 "", current_opcode); } LOG_DEBUG("enable single-step"); @@ -1349,18 +1299,18 @@ int xscale_resume(struct target_s *target, int current, uint32_t address, int ha /* send CPSR */ xscale_send_u32(target, buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32)); - LOG_DEBUG("writing cpsr with value 0x%8.8x", buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32)); + LOG_DEBUG("writing cpsr with value 0x%8.8" PRIx32 "", buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32)); for (i = 7; i >= 0; i--) { /* send register */ xscale_send_u32(target, buf_get_u32(armv4_5->core_cache->reg_list[i].value, 0, 32)); - LOG_DEBUG("writing r%i with value 0x%8.8x", i, buf_get_u32(armv4_5->core_cache->reg_list[i].value, 0, 32)); + LOG_DEBUG("writing r%i with value 0x%8.8" PRIx32 "", i, buf_get_u32(armv4_5->core_cache->reg_list[i].value, 0, 32)); } /* send PC */ xscale_send_u32(target, buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32)); - LOG_DEBUG("writing PC with value 0x%8.8x", buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32)); + LOG_DEBUG("writing PC with value 0x%8.8" PRIx32 "", buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32)); /* wait for and process debug entry */ xscale_debug_entry(target); @@ -1368,7 +1318,7 @@ int xscale_resume(struct target_s *target, int current, uint32_t address, int ha LOG_DEBUG("disable single-step"); xscale_disable_single_step(target); - LOG_DEBUG("set breakpoint at 0x%8.8x", breakpoint->address); + LOG_DEBUG("set breakpoint at 0x%8.8" PRIx32 "", breakpoint->address); xscale_set_breakpoint(target, breakpoint); } } @@ -1392,18 +1342,18 @@ int xscale_resume(struct target_s *target, int current, uint32_t address, int ha /* send CPSR */ xscale_send_u32(target, buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32)); - LOG_DEBUG("writing cpsr with value 0x%8.8x", buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32)); + LOG_DEBUG("writing cpsr with value 0x%8.8" PRIx32 "", buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32)); for (i = 7; i >= 0; i--) { /* send register */ xscale_send_u32(target, buf_get_u32(armv4_5->core_cache->reg_list[i].value, 0, 32)); - LOG_DEBUG("writing r%i with value 0x%8.8x", i, buf_get_u32(armv4_5->core_cache->reg_list[i].value, 0, 32)); + LOG_DEBUG("writing r%i with value 0x%8.8" PRIx32 "", i, buf_get_u32(armv4_5->core_cache->reg_list[i].value, 0, 32)); } /* send PC */ xscale_send_u32(target, buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32)); - LOG_DEBUG("writing PC with value 0x%8.8x", buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32)); + LOG_DEBUG("writing PC with value 0x%8.8" PRIx32 "", buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32)); target->debug_reason = DBG_REASON_NOTHALTED; @@ -1427,7 +1377,8 @@ int xscale_resume(struct target_s *target, int current, uint32_t address, int ha return ERROR_OK; } -static int xscale_step_inner(struct target_s *target, int current, uint32_t address, int handle_breakpoints) +static int xscale_step_inner(struct target_s *target, int current, + uint32_t address, int handle_breakpoints) { armv4_5_common_t *armv4_5 = target->arch_info; xscale_common_t *xscale = armv4_5->arch_info; @@ -1445,61 +1396,61 @@ static int xscale_step_inner(struct target_s *target, int current, uint32_t addr current_pc = buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32); target_read_u32(target, current_pc, ¤t_opcode); - LOG_ERROR("BUG: couldn't calculate PC of next instruction, current opcode was 0x%8.8x", current_opcode); + LOG_ERROR("BUG: couldn't calculate PC of next instruction, current opcode was 0x%8.8" PRIx32 "", current_opcode); return retval; } LOG_DEBUG("enable single-step"); - if ((retval=xscale_enable_single_step(target, next_pc))!=ERROR_OK) + if ((retval = xscale_enable_single_step(target, next_pc)) != ERROR_OK) return retval; /* restore banked registers */ - if ((retval=xscale_restore_context(target))!=ERROR_OK) + if ((retval = xscale_restore_context(target)) != ERROR_OK) return retval; /* send resume request (command 0x30 or 0x31) * clean the trace buffer if it is to be enabled (0x62) */ if (xscale->trace.buffer_enabled) { - if ((retval=xscale_send_u32(target, 0x62))!=ERROR_OK) + if ((retval = xscale_send_u32(target, 0x62)) != ERROR_OK) return retval; - if ((retval=xscale_send_u32(target, 0x31))!=ERROR_OK) + if ((retval = xscale_send_u32(target, 0x31)) != ERROR_OK) return retval; } else - if ((retval=xscale_send_u32(target, 0x30))!=ERROR_OK) + if ((retval = xscale_send_u32(target, 0x30)) != ERROR_OK) return retval; /* send CPSR */ - if ((retval=xscale_send_u32(target, buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32)))!=ERROR_OK) + if ((retval = xscale_send_u32(target, buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32))) != ERROR_OK) return retval; - LOG_DEBUG("writing cpsr with value 0x%8.8x", buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32)); + LOG_DEBUG("writing cpsr with value 0x%8.8" PRIx32 "", buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32)); for (i = 7; i >= 0; i--) { /* send register */ - if ((retval=xscale_send_u32(target, buf_get_u32(armv4_5->core_cache->reg_list[i].value, 0, 32)))!=ERROR_OK) + if ((retval = xscale_send_u32(target, buf_get_u32(armv4_5->core_cache->reg_list[i].value, 0, 32))) != ERROR_OK) return retval; - LOG_DEBUG("writing r%i with value 0x%8.8x", i, buf_get_u32(armv4_5->core_cache->reg_list[i].value, 0, 32)); + LOG_DEBUG("writing r%i with value 0x%8.8" PRIx32 "", i, buf_get_u32(armv4_5->core_cache->reg_list[i].value, 0, 32)); } /* send PC */ - if ((retval=xscale_send_u32(target, buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32)))!=ERROR_OK) + if ((retval = xscale_send_u32(target, buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32))) != ERROR_OK) return retval; - LOG_DEBUG("writing PC with value 0x%8.8x", buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32)); + LOG_DEBUG("writing PC with value 0x%8.8" PRIx32, buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32)); target_call_event_callbacks(target, TARGET_EVENT_RESUMED); /* registers are now invalid */ - if ((retval=armv4_5_invalidate_core_regs(target))!=ERROR_OK) + if ((retval = armv4_5_invalidate_core_regs(target)) != ERROR_OK) return retval; /* wait for and process debug entry */ - if ((retval=xscale_debug_entry(target))!=ERROR_OK) + if ((retval = xscale_debug_entry(target)) != ERROR_OK) return retval; LOG_DEBUG("disable single-step"); - if ((retval=xscale_disable_single_step(target))!=ERROR_OK) + if ((retval = xscale_disable_single_step(target)) != ERROR_OK) return retval; target_call_event_callbacks(target, TARGET_EVENT_HALTED); @@ -1507,7 +1458,8 @@ static int xscale_step_inner(struct target_s *target, int current, uint32_t addr return ERROR_OK; } -int xscale_step(struct target_s *target, int current, uint32_t address, int handle_breakpoints) +static int xscale_step(struct target_s *target, int current, + uint32_t address, int handle_breakpoints) { armv4_5_common_t *armv4_5 = target->arch_info; breakpoint_t *breakpoint = target->breakpoints; @@ -1530,7 +1482,7 @@ int xscale_step(struct target_s *target, int current, uint32_t address, int hand /* if we're at the reset vector, we have to simulate the step */ if (current_pc == 0x0) { - if ((retval=arm_simulate_step(target, NULL))!=ERROR_OK) + if ((retval = arm_simulate_step(target, NULL)) != ERROR_OK) return retval; current_pc = buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32); @@ -1544,7 +1496,7 @@ int xscale_step(struct target_s *target, int current, uint32_t address, int hand if (handle_breakpoints) if ((breakpoint = breakpoint_find(target, buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32)))) { - if ((retval=xscale_unset_breakpoint(target, breakpoint))!=ERROR_OK) + if ((retval = xscale_unset_breakpoint(target, breakpoint)) != ERROR_OK) return retval; } @@ -1561,19 +1513,19 @@ int xscale_step(struct target_s *target, int current, uint32_t address, int hand } -int xscale_assert_reset(target_t *target) +static int xscale_assert_reset(target_t *target) { armv4_5_common_t *armv4_5 = target->arch_info; xscale_common_t *xscale = armv4_5->arch_info; LOG_DEBUG("target->state: %s", - Jim_Nvp_value2name_simple( nvp_target_state, target->state )->name); + target_state_name(target)); /* select DCSR instruction (set endstate to R-T-I to ensure we don't * end up in T-L-R, which would reset JTAG */ jtag_set_end_state(TAP_IDLE); - xscale_jtag_set_instr(xscale->jtag_info.tap, xscale->jtag_info.dcsr); + xscale_jtag_set_instr(target->tap, XSCALE_SELDCSR); /* set Hold reset, Halt mode and Trap Reset */ buf_set_u32(xscale->reg_cache->reg_list[XSCALE_DCSR].value, 30, 1, 0x1); @@ -1581,7 +1533,7 @@ int xscale_assert_reset(target_t *target) xscale_write_dcsr(target, 1, 0); /* select BYPASS, because having DCSR selected caused problems on the PXA27x */ - xscale_jtag_set_instr(xscale->jtag_info.tap, 0x7f); + xscale_jtag_set_instr(target->tap, 0x7f); jtag_execute_queue(); /* assert reset */ @@ -1596,26 +1548,17 @@ int xscale_assert_reset(target_t *target) if (target->reset_halt) { int retval; - if ((retval = target_halt(target))!=ERROR_OK) + if ((retval = target_halt(target)) != ERROR_OK) return retval; } return ERROR_OK; } -int xscale_deassert_reset(target_t *target) +static int xscale_deassert_reset(target_t *target) { armv4_5_common_t *armv4_5 = target->arch_info; xscale_common_t *xscale = armv4_5->arch_info; - - fileio_t debug_handler; - uint32_t address; - uint32_t binary_size; - - uint32_t buf_cnt; - uint32_t i; - int retval; - breakpoint_t *breakpoint = target->breakpoints; LOG_DEBUG("-"); @@ -1640,6 +1583,11 @@ int xscale_deassert_reset(target_t *target) if (!xscale->handler_installed) { + uint32_t address; + unsigned buf_cnt; + const uint8_t *buffer = xscale_debug_handler; + int retval; + /* release SRST */ jtag_add_reset(0, 0); @@ -1654,36 +1602,26 @@ int xscale_deassert_reset(target_t *target) buf_set_u32(xscale->reg_cache->reg_list[XSCALE_DCSR].value, 16, 1, 0x1); xscale_write_dcsr(target, 1, 0); - /* Load debug handler */ - if (fileio_open(&debug_handler, "xscale/debug_handler.bin", FILEIO_READ, FILEIO_BINARY) != ERROR_OK) - { - return ERROR_OK; - } - - if ((binary_size = debug_handler.size) % 4) - { - LOG_ERROR("debug_handler.bin: size not a multiple of 4"); - exit(-1); - } - - if (binary_size > 0x800) - { - LOG_ERROR("debug_handler.bin: larger than 2kb"); - exit(-1); - } - - binary_size = CEIL(binary_size, 32) * 32; - + /* Load the debug handler into the mini-icache. Since + * it's using halt mode (not monitor mode), it runs in + * "Special Debug State" for access to registers, memory, + * coprocessors, trace data, etc. + * + * REVISIT: *assumes* we've had a SRST+TRST reset so the + * mini-icache contents have been invalidated. Safest to + * force that, so writing new contents is reliable... + */ address = xscale->handler_address; - while (binary_size > 0) + for (unsigned binary_size = xscale_debug_handler_size; + binary_size > 0; + binary_size -= buf_cnt, buffer += buf_cnt) { uint32_t cache_line[8]; - uint8_t buffer[32]; + unsigned i; - if ((retval = fileio_read(&debug_handler, 32, buffer, &buf_cnt)) != ERROR_OK) - { - - } + buf_cnt = binary_size; + if (buf_cnt > 32) + buf_cnt = 32; for (i = 0; i < buf_cnt; i += 4) { @@ -1691,23 +1629,31 @@ int xscale_deassert_reset(target_t *target) cache_line[i / 4] = le_to_h_u32(&buffer[i]); } - for (; buf_cnt < 32; buf_cnt += 4) + for (; i < 32; i += 4) { - cache_line[buf_cnt / 4] = 0xe1a08008; + cache_line[i / 4] = 0xe1a08008; } /* only load addresses other than the reset vectors */ if ((address % 0x400) != 0x0) { - xscale_load_ic(target, 1, address, cache_line); + retval = xscale_load_ic(target, address, + cache_line); + if (retval != ERROR_OK) + return retval; } address += buf_cnt; - binary_size -= buf_cnt; }; - xscale_load_ic(target, 1, 0x0, xscale->low_vectors); - xscale_load_ic(target, 1, 0xffff0000, xscale->high_vectors); + retval = xscale_load_ic(target, 0x0, + xscale->low_vectors); + if (retval != ERROR_OK) + return retval; + retval = xscale_load_ic(target, 0xffff0000, + xscale->high_vectors); + if (retval != ERROR_OK) + return retval; jtag_add_runtest(30, jtag_set_end_state(TAP_IDLE)); @@ -1733,8 +1679,6 @@ int xscale_deassert_reset(target_t *target) /* resume the target */ xscale_resume(target, 1, 0x0, 1, 0); } - - fileio_close(&debug_handler); } else { @@ -1744,23 +1688,21 @@ int xscale_deassert_reset(target_t *target) return ERROR_OK; } -int xscale_soft_reset_halt(struct target_s *target) -{ - return ERROR_OK; -} - -int xscale_read_core_reg(struct target_s *target, int num, enum armv4_5_mode mode) +static int xscale_read_core_reg(struct target_s *target, int num, + enum armv4_5_mode mode) { + LOG_ERROR("not implemented"); return ERROR_OK; } -int xscale_write_core_reg(struct target_s *target, int num, enum armv4_5_mode mode, uint32_t value) +static int xscale_write_core_reg(struct target_s *target, int num, + enum armv4_5_mode mode, uint32_t value) { - + LOG_ERROR("not implemented"); return ERROR_OK; } -int xscale_full_context(target_t *target) +static int xscale_full_context(target_t *target) { armv4_5_common_t *armv4_5 = target->arch_info; @@ -1782,7 +1724,7 @@ int xscale_full_context(target_t *target) * we can't enter User mode on an XScale (unpredictable), * but User shares registers with SYS */ - for(i = 1; i < 7; i++) + for (i = 1; i < 7; i++) { int valid = 1; @@ -1836,14 +1778,12 @@ int xscale_full_context(target_t *target) return ERROR_OK; } -int xscale_restore_context(target_t *target) +static int xscale_restore_context(target_t *target) { armv4_5_common_t *armv4_5 = target->arch_info; int i, j; - LOG_DEBUG("-"); - if (target->state != TARGET_HALTED) { LOG_WARNING("target not halted"); @@ -1854,7 +1794,7 @@ int xscale_restore_context(target_t *target) * we can't enter User mode on an XScale (unpredictable), * but User shares registers with SYS */ - for(i = 1; i < 7; i++) + for (i = 1; i < 7; i++) { int dirty = 0; @@ -1905,7 +1845,8 @@ int xscale_restore_context(target_t *target) return ERROR_OK; } -int xscale_read_memory(struct target_s *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer) +static int xscale_read_memory(struct target_s *target, uint32_t address, + uint32_t size, uint32_t count, uint8_t *buffer) { armv4_5_common_t *armv4_5 = target->arch_info; xscale_common_t *xscale = armv4_5->arch_info; @@ -1913,7 +1854,7 @@ int xscale_read_memory(struct target_s *target, uint32_t address, uint32_t size, uint32_t i; int retval; - LOG_DEBUG("address: 0x%8.8x, size: 0x%8.8x, count: 0x%8.8x", address, size, count); + LOG_DEBUG("address: 0x%8.8" PRIx32 ", size: 0x%8.8" PRIx32 ", count: 0x%8.8" PRIx32, address, size, count); if (target->state != TARGET_HALTED) { @@ -1929,20 +1870,20 @@ int xscale_read_memory(struct target_s *target, uint32_t address, uint32_t size, return ERROR_TARGET_UNALIGNED_ACCESS; /* send memory read request (command 0x1n, n: access size) */ - if ((retval=xscale_send_u32(target, 0x10 | size))!=ERROR_OK) + if ((retval = xscale_send_u32(target, 0x10 | size)) != ERROR_OK) return retval; /* send base address for read request */ - if ((retval=xscale_send_u32(target, address))!=ERROR_OK) + if ((retval = xscale_send_u32(target, address)) != ERROR_OK) return retval; /* send number of requested data words */ - if ((retval=xscale_send_u32(target, count))!=ERROR_OK) + if ((retval = xscale_send_u32(target, count)) != ERROR_OK) return retval; /* receive data from target (count times 32-bit words in host endianness) */ buf32 = malloc(4 * count); - if ((retval=xscale_receive(target, buf32, count))!=ERROR_OK) + if ((retval = xscale_receive(target, buf32, count)) != ERROR_OK) return retval; /* extract data from host-endian buffer into byte stream */ @@ -1970,12 +1911,12 @@ int xscale_read_memory(struct target_s *target, uint32_t address, uint32_t size, free(buf32); /* examine DCSR, to see if Sticky Abort (SA) got set */ - if ((retval=xscale_read_dcsr(target))!=ERROR_OK) + if ((retval = xscale_read_dcsr(target)) != ERROR_OK) return retval; if (buf_get_u32(xscale->reg_cache->reg_list[XSCALE_DCSR].value, 5, 1) == 1) { /* clear SA bit */ - if ((retval=xscale_send_u32(target, 0x60))!=ERROR_OK) + if ((retval = xscale_send_u32(target, 0x60)) != ERROR_OK) return retval; return ERROR_TARGET_DATA_ABORT; @@ -1984,13 +1925,14 @@ int xscale_read_memory(struct target_s *target, uint32_t address, uint32_t size, return ERROR_OK; } -int xscale_write_memory(struct target_s *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer) +static int xscale_write_memory(struct target_s *target, uint32_t address, + uint32_t size, uint32_t count, uint8_t *buffer) { armv4_5_common_t *armv4_5 = target->arch_info; xscale_common_t *xscale = armv4_5->arch_info; int retval; - LOG_DEBUG("address: 0x%8.8x, size: 0x%8.8x, count: 0x%8.8x", address, size, count); + LOG_DEBUG("address: 0x%8.8" PRIx32 ", size: 0x%8.8" PRIx32 ", count: 0x%8.8" PRIx32, address, size, count); if (target->state != TARGET_HALTED) { @@ -2006,15 +1948,15 @@ int xscale_write_memory(struct target_s *target, uint32_t address, uint32_t size return ERROR_TARGET_UNALIGNED_ACCESS; /* send memory write request (command 0x2n, n: access size) */ - if ((retval=xscale_send_u32(target, 0x20 | size))!=ERROR_OK) + if ((retval = xscale_send_u32(target, 0x20 | size)) != ERROR_OK) return retval; /* send base address for read request */ - if ((retval=xscale_send_u32(target, address))!=ERROR_OK) + if ((retval = xscale_send_u32(target, address)) != ERROR_OK) return retval; /* send number of requested data words to be written*/ - if ((retval=xscale_send_u32(target, count))!=ERROR_OK) + if ((retval = xscale_send_u32(target, count)) != ERROR_OK) return retval; /* extract data from host-endian buffer into byte stream */ @@ -2044,16 +1986,16 @@ int xscale_write_memory(struct target_s *target, uint32_t address, uint32_t size } } #endif - if ((retval=xscale_send(target, buffer, count, size))!=ERROR_OK) + if ((retval = xscale_send(target, buffer, count, size)) != ERROR_OK) return retval; /* examine DCSR, to see if Sticky Abort (SA) got set */ - if ((retval=xscale_read_dcsr(target))!=ERROR_OK) + if ((retval = xscale_read_dcsr(target)) != ERROR_OK) return retval; if (buf_get_u32(xscale->reg_cache->reg_list[XSCALE_DCSR].value, 5, 1) == 1) { /* clear SA bit */ - if ((retval=xscale_send_u32(target, 0x60))!=ERROR_OK) + if ((retval = xscale_send_u32(target, 0x60)) != ERROR_OK) return retval; return ERROR_TARGET_DATA_ABORT; @@ -2062,12 +2004,13 @@ int xscale_write_memory(struct target_s *target, uint32_t address, uint32_t size return ERROR_OK; } -int xscale_bulk_write_memory(target_t *target, uint32_t address, uint32_t count, uint8_t *buffer) +static int xscale_bulk_write_memory(target_t *target, uint32_t address, + uint32_t count, uint8_t *buffer) { return xscale_write_memory(target, address, 4, count, buffer); } -uint32_t xscale_get_ttb(target_t *target) +static uint32_t xscale_get_ttb(target_t *target) { armv4_5_common_t *armv4_5 = target->arch_info; xscale_common_t *xscale = armv4_5->arch_info; @@ -2079,7 +2022,8 @@ uint32_t xscale_get_ttb(target_t *target) return ttb; } -void xscale_disable_mmu_caches(target_t *target, int mmu, int d_u_cache, int i_cache) +static void xscale_disable_mmu_caches(target_t *target, int mmu, + int d_u_cache, int i_cache) { armv4_5_common_t *armv4_5 = target->arch_info; xscale_common_t *xscale = armv4_5->arch_info; @@ -2118,7 +2062,8 @@ void xscale_disable_mmu_caches(target_t *target, int mmu, int d_u_cache, int i_c xscale_send_u32(target, 0x53); } -void xscale_enable_mmu_caches(target_t *target, int mmu, int d_u_cache, int i_cache) +static void xscale_enable_mmu_caches(target_t *target, int mmu, + int d_u_cache, int i_cache) { armv4_5_common_t *armv4_5 = target->arch_info; xscale_common_t *xscale = armv4_5->arch_info; @@ -2144,7 +2089,8 @@ void xscale_enable_mmu_caches(target_t *target, int mmu, int d_u_cache, int i_ca xscale_send_u32(target, 0x53); } -int xscale_set_breakpoint(struct target_s *target, breakpoint_t *breakpoint) +static int xscale_set_breakpoint(struct target_s *target, + breakpoint_t *breakpoint) { int retval; armv4_5_common_t *armv4_5 = target->arch_info; @@ -2188,12 +2134,12 @@ int xscale_set_breakpoint(struct target_s *target, breakpoint_t *breakpoint) if (breakpoint->length == 4) { /* keep the original instruction in target endianness */ - if((retval = target_read_memory(target, breakpoint->address, 4, 1, breakpoint->orig_instr)) != ERROR_OK) + if ((retval = target_read_memory(target, breakpoint->address, 4, 1, breakpoint->orig_instr)) != ERROR_OK) { return retval; } /* write the original instruction in target endianness (arm7_9->arm_bkpt is host endian) */ - if((retval = target_write_u32(target, breakpoint->address, xscale->arm_bkpt)) != ERROR_OK) + if ((retval = target_write_u32(target, breakpoint->address, xscale->arm_bkpt)) != ERROR_OK) { return retval; } @@ -2201,12 +2147,12 @@ int xscale_set_breakpoint(struct target_s *target, breakpoint_t *breakpoint) else { /* keep the original instruction in target endianness */ - if((retval = target_read_memory(target, breakpoint->address, 2, 1, breakpoint->orig_instr)) != ERROR_OK) + if ((retval = target_read_memory(target, breakpoint->address, 2, 1, breakpoint->orig_instr)) != ERROR_OK) { return retval; } /* write the original instruction in target endianness (arm7_9->arm_bkpt is host endian) */ - if((retval = target_write_u32(target, breakpoint->address, xscale->thumb_bkpt)) != ERROR_OK) + if ((retval = target_write_u32(target, breakpoint->address, xscale->thumb_bkpt)) != ERROR_OK) { return retval; } @@ -2217,7 +2163,8 @@ int xscale_set_breakpoint(struct target_s *target, breakpoint_t *breakpoint) return ERROR_OK; } -int xscale_add_breakpoint(struct target_s *target, breakpoint_t *breakpoint) +static int xscale_add_breakpoint(struct target_s *target, + breakpoint_t *breakpoint) { armv4_5_common_t *armv4_5 = target->arch_info; xscale_common_t *xscale = armv4_5->arch_info; @@ -2248,7 +2195,8 @@ int xscale_add_breakpoint(struct target_s *target, breakpoint_t *breakpoint) return ERROR_OK; } -int xscale_unset_breakpoint(struct target_s *target, breakpoint_t *breakpoint) +static int xscale_unset_breakpoint(struct target_s *target, + breakpoint_t *breakpoint) { int retval; armv4_5_common_t *armv4_5 = target->arch_info; @@ -2285,14 +2233,14 @@ int xscale_unset_breakpoint(struct target_s *target, breakpoint_t *breakpoint) /* restore original instruction (kept in target endianness) */ if (breakpoint->length == 4) { - if((retval = target_write_memory(target, breakpoint->address, 4, 1, breakpoint->orig_instr)) != ERROR_OK) + if ((retval = target_write_memory(target, breakpoint->address, 4, 1, breakpoint->orig_instr)) != ERROR_OK) { return retval; } } else { - if((retval = target_write_memory(target, breakpoint->address, 2, 1, breakpoint->orig_instr)) != ERROR_OK) + if ((retval = target_write_memory(target, breakpoint->address, 2, 1, breakpoint->orig_instr)) != ERROR_OK) { return retval; } @@ -2303,7 +2251,7 @@ int xscale_unset_breakpoint(struct target_s *target, breakpoint_t *breakpoint) return ERROR_OK; } -int xscale_remove_breakpoint(struct target_s *target, breakpoint_t *breakpoint) +static int xscale_remove_breakpoint(struct target_s *target, breakpoint_t *breakpoint) { armv4_5_common_t *armv4_5 = target->arch_info; xscale_common_t *xscale = armv4_5->arch_info; @@ -2325,11 +2273,12 @@ int xscale_remove_breakpoint(struct target_s *target, breakpoint_t *breakpoint) return ERROR_OK; } -int xscale_set_watchpoint(struct target_s *target, watchpoint_t *watchpoint) +static int xscale_set_watchpoint(struct target_s *target, + watchpoint_t *watchpoint) { armv4_5_common_t *armv4_5 = target->arch_info; xscale_common_t *xscale = armv4_5->arch_info; - uint8_t enable=0; + uint8_t enable = 0; reg_t *dbcon = &xscale->reg_cache->reg_list[XSCALE_DBCON]; uint32_t dbcon_value = buf_get_u32(dbcon->value, 0, 32); @@ -2381,7 +2330,8 @@ int xscale_set_watchpoint(struct target_s *target, watchpoint_t *watchpoint) return ERROR_OK; } -int xscale_add_watchpoint(struct target_s *target, watchpoint_t *watchpoint) +static int xscale_add_watchpoint(struct target_s *target, + watchpoint_t *watchpoint) { armv4_5_common_t *armv4_5 = target->arch_info; xscale_common_t *xscale = armv4_5->arch_info; @@ -2407,7 +2357,8 @@ int xscale_add_watchpoint(struct target_s *target, watchpoint_t *watchpoint) return ERROR_OK; } -int xscale_unset_watchpoint(struct target_s *target, watchpoint_t *watchpoint) +static int xscale_unset_watchpoint(struct target_s *target, + watchpoint_t *watchpoint) { armv4_5_common_t *armv4_5 = target->arch_info; xscale_common_t *xscale = armv4_5->arch_info; @@ -2443,7 +2394,7 @@ int xscale_unset_watchpoint(struct target_s *target, watchpoint_t *watchpoint) return ERROR_OK; } -int xscale_remove_watchpoint(struct target_s *target, watchpoint_t *watchpoint) +static int xscale_remove_watchpoint(struct target_s *target, watchpoint_t *watchpoint) { armv4_5_common_t *armv4_5 = target->arch_info; xscale_common_t *xscale = armv4_5->arch_info; @@ -2464,32 +2415,7 @@ int xscale_remove_watchpoint(struct target_s *target, watchpoint_t *watchpoint) return ERROR_OK; } -void xscale_enable_watchpoints(struct target_s *target) -{ - watchpoint_t *watchpoint = target->watchpoints; - - while (watchpoint) - { - if (watchpoint->set == 0) - xscale_set_watchpoint(target, watchpoint); - watchpoint = watchpoint->next; - } -} - -void xscale_enable_breakpoints(struct target_s *target) -{ - breakpoint_t *breakpoint = target->breakpoints; - - /* set any pending breakpoints */ - while (breakpoint) - { - if (breakpoint->set == 0) - xscale_set_breakpoint(target, breakpoint); - breakpoint = breakpoint->next; - } -} - -int xscale_get_reg(reg_t *reg) +static int xscale_get_reg(reg_t *reg) { xscale_reg_t *arch_info = reg->arch_info; target_t *target = arch_info->target; @@ -2535,7 +2461,7 @@ int xscale_get_reg(reg_t *reg) return ERROR_OK; } -int xscale_set_reg(reg_t *reg, uint8_t* buf) +static int xscale_set_reg(reg_t *reg, uint8_t* buf) { xscale_reg_t *arch_info = reg->arch_info; target_t *target = arch_info->target; @@ -2580,17 +2506,7 @@ int xscale_set_reg(reg_t *reg, uint8_t* buf) return ERROR_OK; } -/* convenience wrapper to access XScale specific registers */ -int xscale_set_reg_u32(reg_t *reg, uint32_t value) -{ - uint8_t buf[4]; - - buf_set_u32(buf, 0, 32, value); - - return xscale_set_reg(reg, buf); -} - -int xscale_write_dcsr_sw(target_t *target, uint32_t value) +static int xscale_write_dcsr_sw(target_t *target, uint32_t value) { /* get pointers to arch-specific information */ armv4_5_common_t *armv4_5 = target->arch_info; @@ -2611,7 +2527,7 @@ int xscale_write_dcsr_sw(target_t *target, uint32_t value) return ERROR_OK; } -int xscale_read_trace(target_t *target) +static int xscale_read_trace(target_t *target) { /* get pointers to arch-specific information */ armv4_5_common_t *armv4_5 = target->arch_info; @@ -2690,7 +2606,8 @@ int xscale_read_trace(target_t *target) return ERROR_OK; } -int xscale_read_instruction(target_t *target, arm_instruction_t *instruction) +static int xscale_read_instruction(target_t *target, + arm_instruction_t *instruction) { /* get pointers to arch-specific information */ armv4_5_common_t *armv4_5 = target->arch_info; @@ -2756,7 +2673,8 @@ int xscale_read_instruction(target_t *target, arm_instruction_t *instruction) return ERROR_OK; } -int xscale_branch_address(xscale_trace_data_t *trace_data, int i, uint32_t *target) +static int xscale_branch_address(xscale_trace_data_t *trace_data, + int i, uint32_t *target) { /* if there are less than four entries prior to the indirect branch message * we can't extract the address */ @@ -2771,7 +2689,7 @@ int xscale_branch_address(xscale_trace_data_t *trace_data, int i, uint32_t *targ return 0; } -int xscale_analyze_trace(target_t *target, command_context_t *cmd_ctx) +static int xscale_analyze_trace(target_t *target, command_context_t *cmd_ctx) { /* get pointers to arch-specific information */ armv4_5_common_t *armv4_5 = target->arch_info; @@ -2960,7 +2878,7 @@ int xscale_analyze_trace(target_t *target, command_context_t *cmd_ctx) return ERROR_OK; } -void xscale_build_reg_cache(target_t *target) +static void xscale_build_reg_cache(target_t *target) { /* get pointers to arch-specific information */ armv4_5_common_t *armv4_5 = target->arch_info; @@ -3005,17 +2923,21 @@ void xscale_build_reg_cache(target_t *target) xscale->reg_cache = (*cache_p); } -int xscale_init_target(struct command_context_s *cmd_ctx, struct target_s *target) +static int xscale_init_target(struct command_context_s *cmd_ctx, + struct target_s *target) { + xscale_build_reg_cache(target); return ERROR_OK; } -int xscale_quit(void) +static int xscale_quit(void) { + jtag_add_runtest(100, TAP_RESET); return ERROR_OK; } -int xscale_init_arch_info(target_t *target, xscale_common_t *xscale, jtag_tap_t *tap, const char *variant) +static int xscale_init_arch_info(target_t *target, + xscale_common_t *xscale, jtag_tap_t *tap, const char *variant) { armv4_5_common_t *armv4_5; uint32_t high_reset_branch, low_reset_branch; @@ -3027,29 +2949,28 @@ int xscale_init_arch_info(target_t *target, xscale_common_t *xscale, jtag_tap_t xscale->arch_info = NULL; xscale->common_magic = XSCALE_COMMON_MAGIC; - /* remember the variant (PXA25x, PXA27x, IXP42x, ...) */ - xscale->variant = strdup(variant); - - /* prepare JTAG information for the new target */ - xscale->jtag_info.tap = tap; - - xscale->jtag_info.dbgrx = 0x02; - xscale->jtag_info.dbgtx = 0x10; - xscale->jtag_info.dcsr = 0x09; - xscale->jtag_info.ldic = 0x07; + /* we don't really *need* variant info ... */ + if (variant) { + int ir_length = 0; + + if (strcmp(variant, "pxa250") == 0 + || strcmp(variant, "pxa255") == 0 + || strcmp(variant, "pxa26x") == 0) + ir_length = 5; + else if (strcmp(variant, "pxa27x") == 0 + || strcmp(variant, "ixp42x") == 0 + || strcmp(variant, "ixp45x") == 0 + || strcmp(variant, "ixp46x") == 0) + ir_length = 7; + else + LOG_WARNING("%s: unrecognized variant %s", + tap->dotted_name, variant); - if ((strcmp(xscale->variant, "pxa250") == 0) || - (strcmp(xscale->variant, "pxa255") == 0) || - (strcmp(xscale->variant, "pxa26x") == 0)) - { - xscale->jtag_info.ir_length = 5; - } - else if ((strcmp(xscale->variant, "pxa27x") == 0) || - (strcmp(xscale->variant, "ixp42x") == 0) || - (strcmp(xscale->variant, "ixp45x") == 0) || - (strcmp(xscale->variant, "ixp46x") == 0)) - { - xscale->jtag_info.ir_length = 7; + if (ir_length && ir_length != tap->ir_length) { + LOG_WARNING("%s: IR length for %s is %d; fixing", + tap->dotted_name, variant, ir_length); + tap->ir_length = ir_length; + } } /* the debug handler isn't installed (and thus not running) at this time */ @@ -3123,18 +3044,26 @@ int xscale_init_arch_info(target_t *target, xscale_common_t *xscale, jtag_tap_t return ERROR_OK; } -/* target xscale */ -int xscale_target_create(struct target_s *target, Jim_Interp *interp) +static int xscale_target_create(struct target_s *target, Jim_Interp *interp) { - xscale_common_t *xscale = calloc(1,sizeof(xscale_common_t)); + xscale_common_t *xscale; - xscale_init_arch_info(target, xscale, target->tap, target->variant); - xscale_build_reg_cache(target); + if (xscale_debug_handler_size > 0x800) { + LOG_ERROR("debug_handler.bin: larger than 2kb"); + return ERROR_FAIL; + } - return ERROR_OK; + xscale = calloc(1, sizeof(*xscale)); + if (!xscale) + return ERROR_FAIL; + + return xscale_init_arch_info(target, xscale, target->tap, + target->variant); } -int xscale_handle_debug_handler_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc) +static int +xscale_handle_debug_handler_command(struct command_context_s *cmd_ctx, + char *cmd, char **args, int argc) { target_t *target = NULL; armv4_5_common_t *armv4_5; @@ -3175,7 +3104,9 @@ int xscale_handle_debug_handler_command(struct command_context_s *cmd_ctx, char return ERROR_OK; } -int xscale_handle_cache_clean_address_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc) +static int +xscale_handle_cache_clean_address_command(struct command_context_s *cmd_ctx, + char *cmd, char **args, int argc) { target_t *target = NULL; armv4_5_common_t *armv4_5; @@ -3214,7 +3145,9 @@ int xscale_handle_cache_clean_address_command(struct command_context_s *cmd_ctx, return ERROR_OK; } -int xscale_handle_cache_info_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc) +static int +xscale_handle_cache_info_command(struct command_context_s *cmd_ctx, + char *cmd, char **args, int argc) { target_t *target = get_current_target(cmd_ctx); armv4_5_common_t *armv4_5; @@ -3228,7 +3161,8 @@ int xscale_handle_cache_info_command(struct command_context_s *cmd_ctx, char *cm return armv4_5_handle_cache_info_command(cmd_ctx, &xscale->armv4_5_mmu.armv4_5_cache); } -static int xscale_virt2phys(struct target_s *target, uint32_t virtual, uint32_t *physical) +static int xscale_virt2phys(struct target_s *target, + uint32_t virtual, uint32_t *physical) { armv4_5_common_t *armv4_5; xscale_common_t *xscale; @@ -3265,7 +3199,8 @@ static int xscale_mmu(struct target_s *target, int *enabled) return ERROR_OK; } -int xscale_handle_mmu_command(command_context_t *cmd_ctx, char *cmd, char **args, int argc) +static int xscale_handle_mmu_command(command_context_t *cmd_ctx, + char *cmd, char **args, int argc) { target_t *target = get_current_target(cmd_ctx); armv4_5_common_t *armv4_5; @@ -3301,7 +3236,8 @@ int xscale_handle_mmu_command(command_context_t *cmd_ctx, char *cmd, char **args return ERROR_OK; } -int xscale_handle_idcache_command(command_context_t *cmd_ctx, char *cmd, char **args, int argc) +static int xscale_handle_idcache_command(command_context_t *cmd_ctx, + char *cmd, char **args, int argc) { target_t *target = get_current_target(cmd_ctx); armv4_5_common_t *armv4_5; @@ -3355,7 +3291,8 @@ int xscale_handle_idcache_command(command_context_t *cmd_ctx, char *cmd, char ** return ERROR_OK; } -int xscale_handle_vector_catch_command(command_context_t *cmd_ctx, char *cmd, char **args, int argc) +static int xscale_handle_vector_catch_command(command_context_t *cmd_ctx, + char *cmd, char **args, int argc) { target_t *target = get_current_target(cmd_ctx); armv4_5_common_t *armv4_5; @@ -3383,7 +3320,69 @@ int xscale_handle_vector_catch_command(command_context_t *cmd_ctx, char *cmd, ch } -int xscale_handle_trace_buffer_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc) +static int xscale_handle_vector_table_command(command_context_t *cmd_ctx, + char *cmd, char **args, int argc) +{ + target_t *target = get_current_target(cmd_ctx); + armv4_5_common_t *armv4_5; + xscale_common_t *xscale; + int err = 0; + + if (xscale_get_arch_pointers(target, &armv4_5, &xscale) != ERROR_OK) + { + return ERROR_OK; + } + + if (argc == 0) /* print current settings */ + { + int idx; + + command_print(cmd_ctx, "active user-set static vectors:"); + for (idx = 1; idx < 8; idx++) + if (xscale->static_low_vectors_set & (1 << idx)) + command_print(cmd_ctx, "low %d: 0x%" PRIx32, idx, xscale->static_low_vectors[idx]); + for (idx = 1; idx < 8; idx++) + if (xscale->static_high_vectors_set & (1 << idx)) + command_print(cmd_ctx, "high %d: 0x%" PRIx32, idx, xscale->static_high_vectors[idx]); + return ERROR_OK; + } + + if (argc != 3) + err = 1; + else + { + int idx; + uint32_t vec; + idx = strtoul(args[1], NULL, 0); + vec = strtoul(args[2], NULL, 0); + + if (idx < 1 || idx >= 8) + err = 1; + + if (!err && strcmp(args[0], "low") == 0) + { + xscale->static_low_vectors_set |= (1<static_low_vectors[idx] = vec; + } + else if (!err && (strcmp(args[0], "high") == 0)) + { + xscale->static_high_vectors_set |= (1<static_high_vectors[idx] = vec; + } + else + err = 1; + } + + if (err) + command_print(cmd_ctx, "usage: xscale vector_table "); + + return ERROR_OK; +} + + +static int +xscale_handle_trace_buffer_command(struct command_context_s *cmd_ctx, + char *cmd, char **args, int argc) { target_t *target = get_current_target(cmd_ctx); armv4_5_common_t *armv4_5; @@ -3462,7 +3461,9 @@ int xscale_handle_trace_buffer_command(struct command_context_s *cmd_ctx, char * return ERROR_OK; } -int xscale_handle_trace_image_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc) +static int +xscale_handle_trace_image_command(struct command_context_s *cmd_ctx, + char *cmd, char **args, int argc) { target_t *target; armv4_5_common_t *armv4_5; @@ -3513,7 +3514,8 @@ int xscale_handle_trace_image_command(struct command_context_s *cmd_ctx, char *c return ERROR_OK; } -int xscale_handle_dump_trace_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc) +static int xscale_handle_dump_trace_command(struct command_context_s *cmd_ctx, + char *cmd, char **args, int argc) { target_t *target = get_current_target(cmd_ctx); armv4_5_common_t *armv4_5; @@ -3571,7 +3573,9 @@ int xscale_handle_dump_trace_command(struct command_context_s *cmd_ctx, char *cm return ERROR_OK; } -int xscale_handle_analyze_trace_buffer_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc) +static int +xscale_handle_analyze_trace_buffer_command(struct command_context_s *cmd_ctx, + char *cmd, char **args, int argc) { target_t *target = get_current_target(cmd_ctx); armv4_5_common_t *armv4_5; @@ -3587,7 +3591,8 @@ int xscale_handle_analyze_trace_buffer_command(struct command_context_s *cmd_ctx return ERROR_OK; } -int xscale_handle_cp15(command_context_t *cmd_ctx, char *cmd, char **args, int argc) +static int xscale_handle_cp15(command_context_t *cmd_ctx, + char *cmd, char **args, int argc) { target_t *target = get_current_target(cmd_ctx); armv4_5_common_t *armv4_5; @@ -3605,11 +3610,11 @@ int xscale_handle_cp15(command_context_t *cmd_ctx, char *cmd, char **args, int a } uint32_t reg_no = 0; reg_t *reg = NULL; - if(argc > 0) + if (argc > 0) { reg_no = strtoul(args[0], NULL, 0); /*translate from xscale cp15 register no to openocd register*/ - switch(reg_no) + switch (reg_no) { case 0: reg_no = XSCALE_MAINID; @@ -3642,16 +3647,16 @@ int xscale_handle_cp15(command_context_t *cmd_ctx, char *cmd, char **args, int a reg = &xscale->reg_cache->reg_list[reg_no]; } - if(argc == 1) + if (argc == 1) { uint32_t value; /* read cp15 control register */ xscale_get_reg(reg); value = buf_get_u32(reg->value, 0, 32); - command_print(cmd_ctx, "%s (/%i): 0x%x", reg->name, reg->size, value); + command_print(cmd_ctx, "%s (/%i): 0x%" PRIx32 "", reg->name, (int)(reg->size), value); } - else if(argc == 2) + else if (argc == 2) { uint32_t value = strtoul(args[1], NULL, 0); @@ -3676,7 +3681,7 @@ int xscale_handle_cp15(command_context_t *cmd_ctx, char *cmd, char **args, int a return ERROR_OK; } -int xscale_register_commands(struct command_context_s *cmd_ctx) +static int xscale_register_commands(struct command_context_s *cmd_ctx) { command_t *xscale_cmd; @@ -3691,8 +3696,9 @@ int xscale_register_commands(struct command_context_s *cmd_ctx) register_command(cmd_ctx, xscale_cmd, "dcache", xscale_handle_idcache_command, COMMAND_EXEC, "['enable'|'disable'] the DCache"); register_command(cmd_ctx, xscale_cmd, "vector_catch", xscale_handle_vector_catch_command, COMMAND_EXEC, " of vectors that should be catched"); + register_command(cmd_ctx, xscale_cmd, "vector_table", xscale_handle_vector_table_command, COMMAND_EXEC, " set static code for exception handler entry"); - register_command(cmd_ctx, xscale_cmd, "trace_buffer", xscale_handle_trace_buffer_command, COMMAND_EXEC, " ['fill' [n]|'wrap']"); + register_command(cmd_ctx, xscale_cmd, "trace_buffer", xscale_handle_trace_buffer_command, COMMAND_EXEC, " ['fill' [n]|'wrap']"); register_command(cmd_ctx, xscale_cmd, "dump_trace", xscale_handle_dump_trace_command, COMMAND_EXEC, "dump content of trace buffer to "); register_command(cmd_ctx, xscale_cmd, "analyze_trace", xscale_handle_analyze_trace_buffer_command, COMMAND_EXEC, "analyze content of trace buffer"); @@ -3705,3 +3711,44 @@ int xscale_register_commands(struct command_context_s *cmd_ctx) return ERROR_OK; } + +target_type_t xscale_target = +{ + .name = "xscale", + + .poll = xscale_poll, + .arch_state = xscale_arch_state, + + .target_request_data = NULL, + + .halt = xscale_halt, + .resume = xscale_resume, + .step = xscale_step, + + .assert_reset = xscale_assert_reset, + .deassert_reset = xscale_deassert_reset, + .soft_reset_halt = NULL, + + .get_gdb_reg_list = armv4_5_get_gdb_reg_list, + + .read_memory = xscale_read_memory, + .write_memory = xscale_write_memory, + .bulk_write_memory = xscale_bulk_write_memory, + .checksum_memory = arm7_9_checksum_memory, + .blank_check_memory = arm7_9_blank_check_memory, + + .run_algorithm = armv4_5_run_algorithm, + + .add_breakpoint = xscale_add_breakpoint, + .remove_breakpoint = xscale_remove_breakpoint, + .add_watchpoint = xscale_add_watchpoint, + .remove_watchpoint = xscale_remove_watchpoint, + + .register_commands = xscale_register_commands, + .target_create = xscale_target_create, + .init_target = xscale_init_target, + .quit = xscale_quit, + + .virt2phys = xscale_virt2phys, + .mmu = xscale_mmu +};