X-Git-Url: https://review.openocd.org/gitweb?p=openocd.git;a=blobdiff_plain;f=src%2Ftarget%2Fxscale.c;h=48dbc47e49733eefd871cb8c374127bdbcd703d1;hp=33dd3564183fc21c5ed39bd14ce1bf99cd8d6bd8;hb=1aac72d24339380f6e98c50dec4c96ab30537749;hpb=ac927559c3ce5406adac34b9d4ca4ecb37a48181

diff --git a/src/target/xscale.c b/src/target/xscale.c
index 33dd356418..48dbc47e49 100644
--- a/src/target/xscale.c
+++ b/src/target/xscale.c
@@ -27,13 +27,17 @@
 #include "config.h"
 #endif
 
+#include "breakpoints.h"
 #include "xscale.h"
 #include "target_type.h"
-#include "arm7_9_common.h"
+#include "arm_jtag.h"
 #include "arm_simulator.h"
 #include "arm_disassembler.h"
-#include "time_support.h"
+#include <helper/time_support.h>
+#include "register.h"
 #include "image.h"
+#include "arm_opcodes.h"
+#include "armv4_5.h"
 
 
 /*
@@ -57,16 +61,16 @@
 
 
 /* forward declarations */
-static int xscale_resume(struct target_s *, int current,
+static int xscale_resume(struct target *, int current,
 	uint32_t address, int handle_breakpoints, int debug_execution);
-static int xscale_debug_entry(target_t *);
-static int xscale_restore_context(target_t *);
-static int xscale_get_reg(reg_t *reg);
-static int xscale_set_reg(reg_t *reg, uint8_t *buf);
-static int xscale_set_breakpoint(struct target_s *, struct breakpoint *);
-static int xscale_set_watchpoint(struct target_s *, struct watchpoint *);
-static int xscale_unset_breakpoint(struct target_s *, struct breakpoint *);
-static int xscale_read_trace(target_t *);
+static int xscale_debug_entry(struct target *);
+static int xscale_restore_banked(struct target *);
+static int xscale_get_reg(struct reg *reg);
+static int xscale_set_reg(struct reg *reg, uint8_t *buf);
+static int xscale_set_breakpoint(struct target *, struct breakpoint *);
+static int xscale_set_watchpoint(struct target *, struct watchpoint *);
+static int xscale_unset_breakpoint(struct target *, struct breakpoint *);
+static int xscale_read_trace(struct target *);
 
 
 /* This XScale "debug handler" is loaded into the processor's
@@ -132,10 +136,8 @@ static const struct xscale_reg xscale_reg_arch_info[] =
 	{-1, NULL}, /* TXRXCTRL implicit access via JTAG */
 };
 
-static int xscale_reg_arch_type = -1;
-
 /* convenience wrapper to access XScale specific registers */
-static int xscale_set_reg_u32(reg_t *reg, uint32_t value)
+static int xscale_set_reg_u32(struct reg *reg, uint32_t value)
 {
 	uint8_t buf[4];
 
@@ -146,7 +148,7 @@ static int xscale_set_reg_u32(reg_t *reg, uint32_t value)
 
 static const char xscale_not[] = "target is not an XScale";
 
-static int xscale_verify_pointer(struct command_context_s *cmd_ctx,
+static int xscale_verify_pointer(struct command_context *cmd_ctx,
 		struct xscale_common *xscale)
 {
 	if (xscale->common_magic != XSCALE_COMMON_MAGIC) {
@@ -178,7 +180,7 @@ static int xscale_jtag_set_instr(struct jtag_tap *tap, uint32_t new_instr)
 	return ERROR_OK;
 }
 
-static int xscale_read_dcsr(target_t *target)
+static int xscale_read_dcsr(struct target *target)
 {
 	struct xscale_common *xscale = target_to_xscale(target);
 	int retval;
@@ -191,7 +193,8 @@ static int xscale_read_dcsr(target_t *target)
 	uint8_t field2_check_mask = 0x1;
 
 	jtag_set_end_state(TAP_DRPAUSE);
-	xscale_jtag_set_instr(target->tap, XSCALE_SELDCSR);
+	xscale_jtag_set_instr(target->tap,
+		XSCALE_SELDCSR << xscale->xscale_variant);
 
 	buf_set_u32(&field0, 1, 1, xscale->hold_rst);
 	buf_set_u32(&field0, 2, 1, xscale->external_debug_break);
@@ -251,11 +254,12 @@ static void xscale_getbuf(jtag_callback_data_t arg)
 	*((uint32_t *)in) = buf_get_u32(in, 0, 32);
 }
 
-static int xscale_receive(target_t *target, uint32_t *buffer, int num_words)
+static int xscale_receive(struct target *target, uint32_t *buffer, int num_words)
 {
 	if (num_words == 0)
 		return ERROR_INVALID_ARGUMENTS;
 
+	struct xscale_common *xscale = target_to_xscale(target);
 	int retval = ERROR_OK;
 	tap_state_t path[3];
 	struct scan_field fields[3];
@@ -289,7 +293,8 @@ static int xscale_receive(target_t *target, uint32_t *buffer, int num_words)
 	fields[2].check_mask = &field2_check_mask;
 
 	jtag_set_end_state(TAP_IDLE);
-	xscale_jtag_set_instr(target->tap, XSCALE_DBGTX);
+	xscale_jtag_set_instr(target->tap,
+		XSCALE_DBGTX << xscale->xscale_variant);
 	jtag_add_runtest(1, jtag_get_end_state()); /* ensures that we're in the TAP_IDLE state as the above could be a no-op */
 
 	/* repeat until all words have been collected */
@@ -355,7 +360,7 @@ static int xscale_receive(target_t *target, uint32_t *buffer, int num_words)
 	return retval;
 }
 
-static int xscale_read_tx(target_t *target, int consume)
+static int xscale_read_tx(struct target *target, int consume)
 {
 	struct xscale_common *xscale = target_to_xscale(target);
 	tap_state_t path[3];
@@ -371,7 +376,8 @@ static int xscale_read_tx(target_t *target, int consume)
 
 	jtag_set_end_state(TAP_IDLE);
 
-	xscale_jtag_set_instr(target->tap, XSCALE_DBGTX);
+	xscale_jtag_set_instr(target->tap,
+		XSCALE_DBGTX << xscale->xscale_variant);
 
 	path[0] = TAP_DRSELECT;
 	path[1] = TAP_DRCAPTURE;
@@ -412,7 +418,7 @@ static int xscale_read_tx(target_t *target, int consume)
 			jtag_add_pathmove(3, path);
 		else
 		{
-			jtag_add_pathmove(sizeof(noconsume_path)/sizeof(*noconsume_path), noconsume_path);
+			jtag_add_pathmove(ARRAY_SIZE(noconsume_path), noconsume_path);
 		}
 
 		jtag_add_dr_scan(3, fields, jtag_set_end_state(TAP_IDLE));
@@ -453,7 +459,7 @@ static int xscale_read_tx(target_t *target, int consume)
 	return ERROR_OK;
 }
 
-static int xscale_write_rx(target_t *target)
+static int xscale_write_rx(struct target *target)
 {
 	struct xscale_common *xscale = target_to_xscale(target);
 	int retval;
@@ -469,7 +475,8 @@ static int xscale_write_rx(target_t *target)
 
 	jtag_set_end_state(TAP_IDLE);
 
-	xscale_jtag_set_instr(target->tap, XSCALE_DBGRX);
+	xscale_jtag_set_instr(target->tap,
+		XSCALE_DBGRX << xscale->xscale_variant);
 
 	memset(&fields, 0, sizeof fields);
 
@@ -539,8 +546,9 @@ static int xscale_write_rx(target_t *target)
 }
 
 /* send count elements of size byte to the debug handler */
-static int xscale_send(target_t *target, uint8_t *buffer, int count, int size)
+static int xscale_send(struct target *target, uint8_t *buffer, int count, int size)
 {
+	struct xscale_common *xscale = target_to_xscale(target);
 	uint32_t t[3];
 	int bits[3];
 	int retval;
@@ -548,7 +556,8 @@ static int xscale_send(target_t *target, uint8_t *buffer, int count, int size)
 
 	jtag_set_end_state(TAP_IDLE);
 
-	xscale_jtag_set_instr(target->tap, XSCALE_DBGRX);
+	xscale_jtag_set_instr(target->tap,
+		XSCALE_DBGRX << xscale->xscale_variant);
 
 	bits[0]=3;
 	t[0]=0;
@@ -583,7 +592,7 @@ static int xscale_send(target_t *target, uint8_t *buffer, int count, int size)
 			break;
 		default:
 			LOG_ERROR("BUG: size neither 4, 2 nor 1");
-			exit(-1);
+			return ERROR_INVALID_ARGUMENTS;
 		}
 		jtag_add_dr_out(target->tap,
 				3,
@@ -602,7 +611,7 @@ static int xscale_send(target_t *target, uint8_t *buffer, int count, int size)
 	return ERROR_OK;
 }
 
-static int xscale_send_u32(target_t *target, uint32_t value)
+static int xscale_send_u32(struct target *target, uint32_t value)
 {
 	struct xscale_common *xscale = target_to_xscale(target);
 
@@ -610,7 +619,7 @@ static int xscale_send_u32(target_t *target, uint32_t value)
 	return xscale_write_rx(target);
 }
 
-static int xscale_write_dcsr(target_t *target, int hold_rst, int ext_dbg_brk)
+static int xscale_write_dcsr(struct target *target, int hold_rst, int ext_dbg_brk)
 {
 	struct xscale_common *xscale = target_to_xscale(target);
 	int retval;
@@ -629,7 +638,8 @@ static int xscale_write_dcsr(target_t *target, int hold_rst, int ext_dbg_brk)
 		xscale->external_debug_break = ext_dbg_brk;
 
 	jtag_set_end_state(TAP_IDLE);
-	xscale_jtag_set_instr(target->tap, XSCALE_SELDCSR);
+	xscale_jtag_set_instr(target->tap,
+		XSCALE_SELDCSR << xscale->xscale_variant);
 
 	buf_set_u32(&field0, 1, 1, xscale->hold_rst);
 	buf_set_u32(&field0, 2, 1, xscale->external_debug_break);
@@ -681,8 +691,9 @@ static unsigned int parity (unsigned int v)
 	return (0x6996 >> v) & 1;
 }
 
-static int xscale_load_ic(target_t *target, uint32_t va, uint32_t buffer[8])
+static int xscale_load_ic(struct target *target, uint32_t va, uint32_t buffer[8])
 {
+	struct xscale_common *xscale = target_to_xscale(target);
 	uint8_t packet[4];
 	uint8_t cmd;
 	int word;
@@ -692,7 +703,8 @@ static int xscale_load_ic(target_t *target, uint32_t va, uint32_t buffer[8])
 
 	/* LDIC into IR */
 	jtag_set_end_state(TAP_IDLE);
-	xscale_jtag_set_instr(target->tap, XSCALE_LDIC);
+	xscale_jtag_set_instr(target->tap,
+		XSCALE_LDIC << xscale->xscale_variant);
 
 	/* CMD is b011 to load a cacheline into the Mini ICache.
 	 * Loading into the main ICache is deprecated, and unused.
@@ -736,14 +748,16 @@ static int xscale_load_ic(target_t *target, uint32_t va, uint32_t buffer[8])
 	return jtag_execute_queue();
 }
 
-static int xscale_invalidate_ic_line(target_t *target, uint32_t va)
+static int xscale_invalidate_ic_line(struct target *target, uint32_t va)
 {
+	struct xscale_common *xscale = target_to_xscale(target);
 	uint8_t packet[4];
 	uint8_t cmd;
 	struct scan_field fields[2];
 
 	jtag_set_end_state(TAP_IDLE);
-	xscale_jtag_set_instr(target->tap, XSCALE_LDIC);
+	xscale_jtag_set_instr(target->tap,
+		XSCALE_LDIC << xscale->xscale_variant);
 
 	/* CMD for invalidate IC line b000, bits [6:4] b000 */
 	buf_set_u32(&cmd, 0, 6, 0x0);
@@ -766,7 +780,7 @@ static int xscale_invalidate_ic_line(target_t *target, uint32_t va)
 	return ERROR_OK;
 }
 
-static int xscale_update_vectors(target_t *target)
+static int xscale_update_vectors(struct target *target)
 {
 	struct xscale_common *xscale = target_to_xscale(target);
 	int i;
@@ -830,10 +844,10 @@ static int xscale_update_vectors(target_t *target)
 	return ERROR_OK;
 }
 
-static int xscale_arch_state(struct target_s *target)
+static int xscale_arch_state(struct target *target)
 {
 	struct xscale_common *xscale = target_to_xscale(target);
-	struct armv4_5_common_s *armv4_5 = &xscale->armv4_5_common;
+	struct arm *armv4_5 = &xscale->armv4_5_common;
 
 	static const char *state[] =
 	{
@@ -845,21 +859,14 @@ static int xscale_arch_state(struct target_s *target)
 		"", "\n(processor reset)", "\n(trace buffer full)"
 	};
 
-	if (armv4_5->common_magic != ARMV4_5_COMMON_MAGIC)
+	if (armv4_5->common_magic != ARM_COMMON_MAGIC)
 	{
 		LOG_ERROR("BUG: called for a non-ARMv4/5 target");
-		exit(-1);
+		return ERROR_INVALID_ARGUMENTS;
 	}
 
-	LOG_USER("target halted in %s state due to %s, current mode: %s\n"
-			"cpsr: 0x%8.8" PRIx32 " pc: 0x%8.8" PRIx32 "\n"
-			"MMU: %s, D-Cache: %s, I-Cache: %s"
-			"%s",
-			 armv4_5_state_strings[armv4_5->core_state],
-			 Jim_Nvp_value2name_simple(nvp_target_debug_reason, target->debug_reason)->name ,
-			 armv4_5_mode_strings[armv4_5_mode_to_number(armv4_5->core_mode)],
-			 buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32),
-			 buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32),
+	arm_arch_state(target);
+	LOG_USER("MMU: %s, D-Cache: %s, I-Cache: %s%s",
 			 state[xscale->armv4_5_mmu.mmu_enabled],
 			 state[xscale->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled],
 			 state[xscale->armv4_5_mmu.armv4_5_cache.i_cache_enabled],
@@ -868,7 +875,7 @@ static int xscale_arch_state(struct target_s *target)
 	return ERROR_OK;
 }
 
-static int xscale_poll(target_t *target)
+static int xscale_poll(struct target *target)
 {
 	int retval = ERROR_OK;
 
@@ -908,10 +915,10 @@ static int xscale_poll(target_t *target)
 	return retval;
 }
 
-static int xscale_debug_entry(target_t *target)
+static int xscale_debug_entry(struct target *target)
 {
 	struct xscale_common *xscale = target_to_xscale(target);
-	struct armv4_5_common_s *armv4_5 = &xscale->armv4_5_common;
+	struct arm *armv4_5 = &xscale->armv4_5_common;
 	uint32_t pc;
 	uint32_t buffer[10];
 	int i;
@@ -934,9 +941,9 @@ static int xscale_debug_entry(target_t *target)
 	LOG_DEBUG("r0: 0x%8.8" PRIx32 "", buffer[0]);
 
 	/* move pc from buffer to register cache */
-	buf_set_u32(armv4_5->core_cache->reg_list[15].value, 0, 32, buffer[1]);
-	armv4_5->core_cache->reg_list[15].dirty = 1;
-	armv4_5->core_cache->reg_list[15].valid = 1;
+	buf_set_u32(armv4_5->pc->value, 0, 32, buffer[1]);
+	armv4_5->pc->dirty = 1;
+	armv4_5->pc->valid = 1;
 	LOG_DEBUG("pc: 0x%8.8" PRIx32 "", buffer[1]);
 
 	/* move data from buffer to register cache */
@@ -948,36 +955,24 @@ static int xscale_debug_entry(target_t *target)
 		LOG_DEBUG("r%i: 0x%8.8" PRIx32 "", i, buffer[i + 1]);
 	}
 
-	buf_set_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32, buffer[9]);
-	armv4_5->core_cache->reg_list[ARMV4_5_CPSR].dirty = 1;
-	armv4_5->core_cache->reg_list[ARMV4_5_CPSR].valid = 1;
+	arm_set_cpsr(armv4_5, buffer[9]);
 	LOG_DEBUG("cpsr: 0x%8.8" PRIx32 "", buffer[9]);
 
-	armv4_5->core_mode = buffer[9] & 0x1f;
-	if (armv4_5_mode_to_number(armv4_5->core_mode) == -1)
+	if (!is_arm_mode(armv4_5->core_mode))
 	{
 		target->state = TARGET_UNKNOWN;
 		LOG_ERROR("cpsr contains invalid mode value - communication failure");
 		return ERROR_TARGET_FAILURE;
 	}
-	LOG_DEBUG("target entered debug state in %s mode", armv4_5_mode_strings[armv4_5_mode_to_number(armv4_5->core_mode)]);
-
-	if (buffer[9] & 0x20)
-		armv4_5->core_state = ARMV4_5_STATE_THUMB;
-	else
-		armv4_5->core_state = ARMV4_5_STATE_ARM;
-
-
-	if (armv4_5_mode_to_number(armv4_5->core_mode)==-1)
-		return ERROR_FAIL;
+	LOG_DEBUG("target entered debug state in %s mode",
+			 arm_mode_name(armv4_5->core_mode));
 
 	/* get banked registers, r8 to r14, and spsr if not in USR/SYS mode */
-	if ((armv4_5->core_mode != ARMV4_5_MODE_USR) && (armv4_5->core_mode != ARMV4_5_MODE_SYS))
-	{
+	if (armv4_5->spsr) {
 		xscale_receive(target, buffer, 8);
-		buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 16).value, 0, 32, buffer[7]);
-		ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 16).dirty = 0;
-		ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 16).valid = 1;
+		buf_set_u32(armv4_5->spsr->value, 0, 32, buffer[7]);
+		armv4_5->spsr->dirty = false;
+		armv4_5->spsr->valid = true;
 	}
 	else
 	{
@@ -985,12 +980,14 @@ static int xscale_debug_entry(target_t *target)
 		xscale_receive(target, buffer, 7);
 	}
 
-	/* move data from buffer to register cache */
+	/* move data from buffer to right banked register in cache */
 	for (i = 8; i <= 14; i++)
 	{
-		buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).value, 0, 32, buffer[i - 8]);
-		ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).dirty = 0;
-		ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).valid = 1;
+		struct reg *r = arm_reg_current(armv4_5, i);
+
+		buf_set_u32(r->value, 0, 32, buffer[i - 8]);
+		r->dirty = false;
+		r->valid = true;
 	}
 
 	/* examine debug reason */
@@ -998,7 +995,7 @@ static int xscale_debug_entry(target_t *target)
 	moe = buf_get_u32(xscale->reg_cache->reg_list[XSCALE_DCSR].value, 2, 3);
 
 	/* stored PC (for calculating fixup) */
-	pc = buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32);
+	pc = buf_get_u32(armv4_5->pc->value, 0, 32);
 
 	switch (moe)
 	{
@@ -1045,7 +1042,7 @@ static int xscale_debug_entry(target_t *target)
 	}
 
 	/* apply PC fixup */
-	buf_set_u32(armv4_5->core_cache->reg_list[15].value, 0, 32, pc);
+	buf_set_u32(armv4_5->pc->value, 0, 32, pc);
 
 	/* on the first debug entry, identify cache type */
 	if (xscale->armv4_5_mmu.armv4_5_cache.ctype == -1)
@@ -1088,7 +1085,7 @@ static int xscale_debug_entry(target_t *target)
 	return ERROR_OK;
 }
 
-static int xscale_halt(target_t *target)
+static int xscale_halt(struct target *target)
 {
 	struct xscale_common *xscale = target_to_xscale(target);
 
@@ -1122,10 +1119,10 @@ static int xscale_halt(target_t *target)
 	return ERROR_OK;
 }
 
-static int xscale_enable_single_step(struct target_s *target, uint32_t next_pc)
+static int xscale_enable_single_step(struct target *target, uint32_t next_pc)
 {
 	struct xscale_common *xscale = target_to_xscale(target);
-	reg_t *ibcr0 = &xscale->reg_cache->reg_list[XSCALE_IBCR0];
+	struct reg *ibcr0 = &xscale->reg_cache->reg_list[XSCALE_IBCR0];
 	int retval;
 
 	if (xscale->ibcr0_used)
@@ -1149,10 +1146,10 @@ static int xscale_enable_single_step(struct target_s *target, uint32_t next_pc)
 	return ERROR_OK;
 }
 
-static int xscale_disable_single_step(struct target_s *target)
+static int xscale_disable_single_step(struct target *target)
 {
 	struct xscale_common *xscale = target_to_xscale(target);
-	reg_t *ibcr0 = &xscale->reg_cache->reg_list[XSCALE_IBCR0];
+	struct reg *ibcr0 = &xscale->reg_cache->reg_list[XSCALE_IBCR0];
 	int retval;
 
 	if ((retval = xscale_set_reg_u32(ibcr0, 0x0)) != ERROR_OK)
@@ -1161,7 +1158,7 @@ static int xscale_disable_single_step(struct target_s *target)
 	return ERROR_OK;
 }
 
-static void xscale_enable_watchpoints(struct target_s *target)
+static void xscale_enable_watchpoints(struct target *target)
 {
 	struct watchpoint *watchpoint = target->watchpoints;
 
@@ -1173,7 +1170,7 @@ static void xscale_enable_watchpoints(struct target_s *target)
 	}
 }
 
-static void xscale_enable_breakpoints(struct target_s *target)
+static void xscale_enable_breakpoints(struct target *target)
 {
 	struct breakpoint *breakpoint = target->breakpoints;
 
@@ -1186,11 +1183,11 @@ static void xscale_enable_breakpoints(struct target_s *target)
 	}
 }
 
-static int xscale_resume(struct target_s *target, int current,
+static int xscale_resume(struct target *target, int current,
 		uint32_t address, int handle_breakpoints, int debug_execution)
 {
 	struct xscale_common *xscale = target_to_xscale(target);
-	struct armv4_5_common_s *armv4_5 = &xscale->armv4_5_common;
+	struct arm *armv4_5 = &xscale->armv4_5_common;
 	struct breakpoint *breakpoint = target->breakpoints;
 	uint32_t current_pc;
 	int retval;
@@ -1215,21 +1212,23 @@ static int xscale_resume(struct target_s *target, int current,
 
 	/* current = 1: continue on current pc, otherwise continue at <address> */
 	if (!current)
-		buf_set_u32(armv4_5->core_cache->reg_list[15].value, 0, 32, address);
+		buf_set_u32(armv4_5->pc->value, 0, 32, address);
 
-	current_pc = buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32);
+	current_pc = buf_get_u32(armv4_5->pc->value, 0, 32);
 
 	/* if we're at the reset vector, we have to simulate the branch */
 	if (current_pc == 0x0)
 	{
 		arm_simulate_step(target, NULL);
-		current_pc = buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32);
+		current_pc = buf_get_u32(armv4_5->pc->value, 0, 32);
 	}
 
 	/* the front-end may request us not to handle breakpoints */
 	if (handle_breakpoints)
 	{
-		if ((breakpoint = breakpoint_find(target, buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32))))
+		breakpoint = breakpoint_find(target,
+				buf_get_u32(armv4_5->pc->value, 0, 32));
+		if (breakpoint != NULL)
 		{
 			uint32_t next_pc;
 
@@ -1249,7 +1248,7 @@ static int xscale_resume(struct target_s *target, int current,
 			xscale_enable_single_step(target, next_pc);
 
 			/* restore banked registers */
-			xscale_restore_context(target);
+			retval = xscale_restore_banked(target);
 
 			/* send resume request (command 0x30 or 0x31)
 			 * clean the trace buffer if it is to be enabled (0x62) */
@@ -1262,8 +1261,10 @@ static int xscale_resume(struct target_s *target, int current,
 				xscale_send_u32(target, 0x30);
 
 			/* send CPSR */
-			xscale_send_u32(target, buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32));
-			LOG_DEBUG("writing cpsr with value 0x%8.8" PRIx32 "", buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32));
+			xscale_send_u32(target,
+				buf_get_u32(armv4_5->cpsr->value, 0, 32));
+			LOG_DEBUG("writing cpsr with value 0x%8.8" PRIx32,
+				buf_get_u32(armv4_5->cpsr->value, 0, 32));
 
 			for (i = 7; i >= 0; i--)
 			{
@@ -1273,8 +1274,10 @@ static int xscale_resume(struct target_s *target, int current,
 			}
 
 			/* send PC */
-			xscale_send_u32(target, buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32));
-			LOG_DEBUG("writing PC with value 0x%8.8" PRIx32 "", buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32));
+			xscale_send_u32(target,
+					buf_get_u32(armv4_5->pc->value, 0, 32));
+			LOG_DEBUG("writing PC with value 0x%8.8" PRIx32,
+					buf_get_u32(armv4_5->pc->value, 0, 32));
 
 			/* wait for and process debug entry */
 			xscale_debug_entry(target);
@@ -1292,7 +1295,7 @@ static int xscale_resume(struct target_s *target, int current,
 	xscale_enable_watchpoints(target);
 
 	/* restore banked registers */
-	xscale_restore_context(target);
+	retval = xscale_restore_banked(target);
 
 	/* send resume request (command 0x30 or 0x31)
 	 * clean the trace buffer if it is to be enabled (0x62) */
@@ -1305,8 +1308,9 @@ static int xscale_resume(struct target_s *target, int current,
 		xscale_send_u32(target, 0x30);
 
 	/* send CPSR */
-	xscale_send_u32(target, buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32));
-	LOG_DEBUG("writing cpsr with value 0x%8.8" PRIx32 "", buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32));
+	xscale_send_u32(target, buf_get_u32(armv4_5->cpsr->value, 0, 32));
+	LOG_DEBUG("writing cpsr with value 0x%8.8" PRIx32,
+			buf_get_u32(armv4_5->cpsr->value, 0, 32));
 
 	for (i = 7; i >= 0; i--)
 	{
@@ -1316,15 +1320,16 @@ static int xscale_resume(struct target_s *target, int current,
 	}
 
 	/* send PC */
-	xscale_send_u32(target, buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32));
-	LOG_DEBUG("writing PC with value 0x%8.8" PRIx32 "", buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32));
+	xscale_send_u32(target, buf_get_u32(armv4_5->pc->value, 0, 32));
+	LOG_DEBUG("wrote PC with value 0x%8.8" PRIx32,
+			buf_get_u32(armv4_5->pc->value, 0, 32));
 
 	target->debug_reason = DBG_REASON_NOTHALTED;
 
 	if (!debug_execution)
 	{
 		/* registers are now invalid */
-		armv4_5_invalidate_core_regs(target);
+		register_cache_invalidate(armv4_5->core_cache);
 		target->state = TARGET_RUNNING;
 		target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
 	}
@@ -1339,11 +1344,11 @@ static int xscale_resume(struct target_s *target, int current,
 	return ERROR_OK;
 }
 
-static int xscale_step_inner(struct target_s *target, int current,
+static int xscale_step_inner(struct target *target, int current,
 		uint32_t address, int handle_breakpoints)
 {
 	struct xscale_common *xscale = target_to_xscale(target);
-	struct armv4_5_common_s *armv4_5 = &xscale->armv4_5_common;
+	struct arm *armv4_5 = &xscale->armv4_5_common;
 	uint32_t next_pc;
 	int retval;
 	int i;
@@ -1354,7 +1359,7 @@ static int xscale_step_inner(struct target_s *target, int current,
 	if ((retval = arm_simulate_step(target, &next_pc)) != ERROR_OK)
 	{
 		uint32_t current_opcode, current_pc;
-		current_pc = buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32);
+		current_pc = buf_get_u32(armv4_5->pc->value, 0, 32);
 
 		target_read_u32(target, current_pc, &current_opcode);
 		LOG_ERROR("BUG: couldn't calculate PC of next instruction, current opcode was 0x%8.8" PRIx32 "", current_opcode);
@@ -1366,7 +1371,7 @@ static int xscale_step_inner(struct target_s *target, int current,
 		return retval;
 
 	/* restore banked registers */
-	if ((retval = xscale_restore_context(target)) != ERROR_OK)
+	if ((retval = xscale_restore_banked(target)) != ERROR_OK)
 		return retval;
 
 	/* send resume request (command 0x30 or 0x31)
@@ -1383,9 +1388,12 @@ static int xscale_step_inner(struct target_s *target, int current,
 			return retval;
 
 	/* send CPSR */
-	if ((retval = xscale_send_u32(target, buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32))) != ERROR_OK)
+	retval = xscale_send_u32(target,
+			buf_get_u32(armv4_5->cpsr->value, 0, 32));
+	if (retval != ERROR_OK)
 		return retval;
-	LOG_DEBUG("writing cpsr with value 0x%8.8" PRIx32 "", buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32));
+	LOG_DEBUG("writing cpsr with value 0x%8.8" PRIx32,
+			buf_get_u32(armv4_5->cpsr->value, 0, 32));
 
 	for (i = 7; i >= 0; i--)
 	{
@@ -1396,15 +1404,17 @@ static int xscale_step_inner(struct target_s *target, int current,
 	}
 
 	/* send PC */
-	if ((retval = xscale_send_u32(target, buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32))) != ERROR_OK)
+	retval = xscale_send_u32(target,
+			buf_get_u32(armv4_5->pc->value, 0, 32));
+	if (retval != ERROR_OK)
 		return retval;
-	LOG_DEBUG("writing PC with value 0x%8.8" PRIx32, buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32));
+	LOG_DEBUG("wrote PC with value 0x%8.8" PRIx32,
+			buf_get_u32(armv4_5->pc->value, 0, 32));
 
 	target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
 
 	/* registers are now invalid */
-	if ((retval = armv4_5_invalidate_core_regs(target)) != ERROR_OK)
-		return retval;
+	register_cache_invalidate(armv4_5->core_cache);
 
 	/* wait for and process debug entry */
 	if ((retval = xscale_debug_entry(target)) != ERROR_OK)
@@ -1419,11 +1429,11 @@ static int xscale_step_inner(struct target_s *target, int current,
 	return ERROR_OK;
 }
 
-static int xscale_step(struct target_s *target, int current,
+static int xscale_step(struct target *target, int current,
 		uint32_t address, int handle_breakpoints)
 {
-	struct armv4_5_common_s *armv4_5 = target_to_armv4_5(target);
-	struct breakpoint *breakpoint = target->breakpoints;
+	struct arm *armv4_5 = target_to_arm(target);
+	struct breakpoint *breakpoint = NULL;
 
 	uint32_t current_pc;
 	int retval;
@@ -1436,16 +1446,16 @@ static int xscale_step(struct target_s *target, int current,
 
 	/* current = 1: continue on current pc, otherwise continue at <address> */
 	if (!current)
-		buf_set_u32(armv4_5->core_cache->reg_list[15].value, 0, 32, address);
+		buf_set_u32(armv4_5->pc->value, 0, 32, address);
 
-	current_pc = buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32);
+	current_pc = buf_get_u32(armv4_5->pc->value, 0, 32);
 
 	/* if we're at the reset vector, we have to simulate the step */
 	if (current_pc == 0x0)
 	{
 		if ((retval = arm_simulate_step(target, NULL)) != ERROR_OK)
 			return retval;
-		current_pc = buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32);
+		current_pc = buf_get_u32(armv4_5->pc->value, 0, 32);
 
 		target->debug_reason = DBG_REASON_SINGLESTEP;
 		target_call_event_callbacks(target, TARGET_EVENT_HALTED);
@@ -1455,11 +1465,13 @@ static int xscale_step(struct target_s *target, int current,
 
 	/* the front-end may request us not to handle breakpoints */
 	if (handle_breakpoints)
-		if ((breakpoint = breakpoint_find(target, buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32))))
-		{
-			if ((retval = xscale_unset_breakpoint(target, breakpoint)) != ERROR_OK)
-				return retval;
-		}
+		breakpoint = breakpoint_find(target,
+				buf_get_u32(armv4_5->pc->value, 0, 32));
+	if (breakpoint != NULL) {
+		retval = xscale_unset_breakpoint(target, breakpoint);
+		if (retval != ERROR_OK)
+			return retval;
+	}
 
 	retval = xscale_step_inner(target, current, address, handle_breakpoints);
 
@@ -1474,7 +1486,7 @@ static int xscale_step(struct target_s *target, int current,
 
 }
 
-static int xscale_assert_reset(target_t *target)
+static int xscale_assert_reset(struct target *target)
 {
 	struct xscale_common *xscale = target_to_xscale(target);
 
@@ -1485,7 +1497,8 @@ static int xscale_assert_reset(target_t *target)
 	 * end up in T-L-R, which would reset JTAG
 	 */
 	jtag_set_end_state(TAP_IDLE);
-	xscale_jtag_set_instr(target->tap, XSCALE_SELDCSR);
+	xscale_jtag_set_instr(target->tap,
+		XSCALE_SELDCSR << xscale->xscale_variant);
 
 	/* set Hold reset, Halt mode and Trap Reset */
 	buf_set_u32(xscale->reg_cache->reg_list[XSCALE_DCSR].value, 30, 1, 0x1);
@@ -1493,7 +1506,7 @@ static int xscale_assert_reset(target_t *target)
 	xscale_write_dcsr(target, 1, 0);
 
 	/* select BYPASS, because having DCSR selected caused problems on the PXA27x */
-	xscale_jtag_set_instr(target->tap, 0x7f);
+	xscale_jtag_set_instr(target->tap, ~0);
 	jtag_execute_queue();
 
 	/* assert reset */
@@ -1515,7 +1528,7 @@ static int xscale_assert_reset(target_t *target)
 	return ERROR_OK;
 }
 
-static int xscale_deassert_reset(target_t *target)
+static int xscale_deassert_reset(struct target *target)
 {
 	struct xscale_common *xscale = target_to_xscale(target);
 	struct breakpoint *breakpoint = target->breakpoints;
@@ -1540,7 +1553,7 @@ static int xscale_deassert_reset(target_t *target)
 		breakpoint = breakpoint->next;
 	}
 
-	armv4_5_invalidate_core_regs(target);
+	register_cache_invalidate(xscale->armv4_5_common.core_cache);
 
 	/* FIXME mark hardware watchpoints got unset too.  Also,
 	 * at least some of the XScale registers are invalid...
@@ -1649,23 +1662,25 @@ static int xscale_deassert_reset(target_t *target)
 	return ERROR_OK;
 }
 
-static int xscale_read_core_reg(struct target_s *target, int num,
-		enum armv4_5_mode mode)
+static int xscale_read_core_reg(struct target *target, struct reg *r,
+		int num, enum arm_mode mode)
 {
+	/** \todo add debug handler support for core register reads */
 	LOG_ERROR("not implemented");
 	return ERROR_OK;
 }
 
-static int xscale_write_core_reg(struct target_s *target, int num,
-		enum armv4_5_mode mode, uint32_t value)
+static int xscale_write_core_reg(struct target *target, struct reg *r,
+		int num, enum arm_mode mode, uint32_t value)
 {
+	/** \todo add debug handler support for core register writes */
 	LOG_ERROR("not implemented");
 	return ERROR_OK;
 }
 
-static int xscale_full_context(target_t *target)
+static int xscale_full_context(struct target *target)
 {
-	struct armv4_5_common_s *armv4_5 = target_to_armv4_5(target);
+	struct arm *armv4_5 = target_to_arm(target);
 
 	uint32_t *buffer;
 
@@ -1687,50 +1702,56 @@ static int xscale_full_context(target_t *target)
 	 */
 	for (i = 1; i < 7; i++)
 	{
-		int valid = 1;
+		enum arm_mode mode = armv4_5_number_to_mode(i);
+		bool valid = true;
+		struct reg *r;
+
+		if (mode == ARM_MODE_USR)
+			continue;
 
 		/* check if there are invalid registers in the current mode
 		 */
-		for (j = 0; j <= 16; j++)
+		for (j = 0; valid && j <= 16; j++)
 		{
-			if (ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), j).valid == 0)
-				valid = 0;
+			if (!ARMV4_5_CORE_REG_MODE(armv4_5->core_cache,
+					mode, j).valid)
+				valid = false;
 		}
+		if (valid)
+			continue;
 
-		if (!valid)
-		{
-			uint32_t tmp_cpsr;
-
-			/* request banked registers */
-			xscale_send_u32(target, 0x0);
+		/* request banked registers */
+		xscale_send_u32(target, 0x0);
 
-			tmp_cpsr = 0x0;
-			tmp_cpsr |= armv4_5_number_to_mode(i);
-			tmp_cpsr |= 0xc0; /* I/F bits */
+		/* send CPSR for desired bank mode */
+		xscale_send_u32(target, mode | 0xc0 /* I/F bits */);
 
-			/* send CPSR for desired mode */
-			xscale_send_u32(target, tmp_cpsr);
+		/* get banked registers:  r8 to r14; and SPSR
+		 * except in USR/SYS mode
+		 */
+		if (mode != ARM_MODE_SYS) {
+			/* SPSR */
+			r = &ARMV4_5_CORE_REG_MODE(armv4_5->core_cache,
+					mode, 16);
+
+			xscale_receive(target, buffer, 8);
+
+			buf_set_u32(r->value, 0, 32, buffer[7]);
+			r->dirty = false;
+			r->valid = true;
+		} else {
+			xscale_receive(target, buffer, 7);
+		}
 
-			/* get banked registers, r8 to r14, and spsr if not in USR/SYS mode */
-			if ((armv4_5_number_to_mode(i) != ARMV4_5_MODE_USR) && (armv4_5_number_to_mode(i) != ARMV4_5_MODE_SYS))
-			{
-				xscale_receive(target, buffer, 8);
-				buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 16).value, 0, 32, buffer[7]);
-				ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), 16).dirty = 0;
-				ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), 16).valid = 1;
-			}
-			else
-			{
-				xscale_receive(target, buffer, 7);
-			}
+		/* move data from buffer to register cache */
+		for (j = 8; j <= 14; j++)
+		{
+			r = &ARMV4_5_CORE_REG_MODE(armv4_5->core_cache,
+					mode, j);
 
-			/* move data from buffer to register cache */
-			for (j = 8; j <= 14; j++)
-			{
-				buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), j).value, 0, 32, buffer[j - 8]);
-				ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), j).dirty = 0;
-				ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), j).valid = 1;
-			}
+			buf_set_u32(r->value, 0, 32, buffer[j - 8]);
+			r->dirty = false;
+			r->valid = true;
 		}
 	}
 
@@ -1739,9 +1760,9 @@ static int xscale_full_context(target_t *target)
 	return ERROR_OK;
 }
 
-static int xscale_restore_context(target_t *target)
+static int xscale_restore_banked(struct target *target)
 {
-	struct armv4_5_common_s *armv4_5 = target_to_armv4_5(target);
+	struct arm *armv4_5 = target_to_arm(target);
 
 	int i, j;
 
@@ -1752,61 +1773,67 @@ static int xscale_restore_context(target_t *target)
 	}
 
 	/* iterate through processor modes (FIQ, IRQ, SVC, ABT, UND and SYS)
-	* we can't enter User mode on an XScale (unpredictable),
-	* but User shares registers with SYS
-	*/
+	 * and check if any banked registers need to be written.  Ignore
+	 * USR mode (number 0) in favor of SYS; we can't enter User mode on
+	 * an XScale (unpredictable), but they share all registers.
+	 */
 	for (i = 1; i < 7; i++)
 	{
-		int dirty = 0;
+		enum arm_mode mode = armv4_5_number_to_mode(i);
+		struct reg *r;
 
-		/* check if there are invalid registers in the current mode
-		*/
+		if (mode == ARM_MODE_USR)
+			continue;
+
+		/* check if there are dirty registers in this mode */
 		for (j = 8; j <= 14; j++)
 		{
-			if (ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), j).dirty == 1)
-				dirty = 1;
+			if (ARMV4_5_CORE_REG_MODE(armv4_5->core_cache,
+					mode, j).dirty)
+				goto dirty;
 		}
 
 		/* if not USR/SYS, check if the SPSR needs to be written */
-		if ((armv4_5_number_to_mode(i) != ARMV4_5_MODE_USR) && (armv4_5_number_to_mode(i) != ARMV4_5_MODE_SYS))
+		if (mode != ARM_MODE_SYS)
 		{
-			if (ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), 16).dirty == 1)
-				dirty = 1;
+			if (ARMV4_5_CORE_REG_MODE(armv4_5->core_cache,
+					mode, 16).dirty)
+				goto dirty;
 		}
 
-		if (dirty)
-		{
-			uint32_t tmp_cpsr;
-
-			/* send banked registers */
-			xscale_send_u32(target, 0x1);
+		/* there's nothing to flush for this mode */
+		continue;
 
-			tmp_cpsr = 0x0;
-			tmp_cpsr |= armv4_5_number_to_mode(i);
-			tmp_cpsr |= 0xc0; /* I/F bits */
+dirty:
+		/* command 0x1:  "send banked registers" */
+		xscale_send_u32(target, 0x1);
 
-			/* send CPSR for desired mode */
-			xscale_send_u32(target, tmp_cpsr);
+		/* send CPSR for desired mode */
+		xscale_send_u32(target, mode | 0xc0 /* I/F bits */);
 
-			/* send banked registers, r8 to r14, and spsr if not in USR/SYS mode */
-			for (j = 8; j <= 14; j++)
-			{
-				xscale_send_u32(target, buf_get_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, j).value, 0, 32));
-				ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), j).dirty = 0;
-			}
+		/* send r8 to r14/lr ... only FIQ needs more than r13..r14,
+		 * but this protocol doesn't understand that nuance.
+		 */
+		for (j = 8; j <= 14; j++) {
+			r = &ARMV4_5_CORE_REG_MODE(armv4_5->core_cache,
+					mode, j);
+			xscale_send_u32(target, buf_get_u32(r->value, 0, 32));
+			r->dirty = false;
+		}
 
-			if ((armv4_5_number_to_mode(i) != ARMV4_5_MODE_USR) && (armv4_5_number_to_mode(i) != ARMV4_5_MODE_SYS))
-			{
-				xscale_send_u32(target, buf_get_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 16).value, 0, 32));
-				ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), 16).dirty = 0;
-			}
+		/* send spsr if not in USR/SYS mode */
+		if (mode != ARM_MODE_SYS) {
+			r = &ARMV4_5_CORE_REG_MODE(armv4_5->core_cache,
+					mode, 16);
+			xscale_send_u32(target, buf_get_u32(r->value, 0, 32));
+			r->dirty = false;
 		}
 	}
 
 	return ERROR_OK;
 }
 
-static int xscale_read_memory(struct target_s *target, uint32_t address,
+static int xscale_read_memory(struct target *target, uint32_t address,
 		uint32_t size, uint32_t count, uint8_t *buffer)
 {
 	struct xscale_common *xscale = target_to_xscale(target);
@@ -1863,8 +1890,8 @@ static int xscale_read_memory(struct target_s *target, uint32_t address,
 				*buffer++ = buf32[i] & 0xff;
 				break;
 			default:
-				LOG_ERROR("should never get here");
-				exit(-1);
+				LOG_ERROR("invalid read size");
+				return ERROR_INVALID_ARGUMENTS;
 		}
 	}
 
@@ -1885,7 +1912,22 @@ static int xscale_read_memory(struct target_s *target, uint32_t address,
 	return ERROR_OK;
 }
 
-static int xscale_write_memory(struct target_s *target, uint32_t address,
+static int xscale_read_phys_memory(struct target *target, uint32_t address,
+		uint32_t size, uint32_t count, uint8_t *buffer)
+{
+	struct xscale_common *xscale = target_to_xscale(target);
+
+	/* with MMU inactive, there are only physical addresses */
+	if (!xscale->armv4_5_mmu.mmu_enabled)
+		return xscale_read_memory(target, address, size, count, buffer);
+
+	/** \todo: provide a non-stub implementation of this routine. */
+	LOG_ERROR("%s: %s is not implemented.  Disable MMU?",
+			target_name(target), __func__);
+	return ERROR_FAIL;
+}
+
+static int xscale_write_memory(struct target *target, uint32_t address,
 		uint32_t size, uint32_t count, uint8_t *buffer)
 {
 	struct xscale_common *xscale = target_to_xscale(target);
@@ -1963,13 +2005,28 @@ static int xscale_write_memory(struct target_s *target, uint32_t address,
 	return ERROR_OK;
 }
 
-static int xscale_bulk_write_memory(target_t *target, uint32_t address,
+static int xscale_write_phys_memory(struct target *target, uint32_t address,
+		uint32_t size, uint32_t count, uint8_t *buffer)
+{
+	struct xscale_common *xscale = target_to_xscale(target);
+
+	/* with MMU inactive, there are only physical addresses */
+	if (!xscale->armv4_5_mmu.mmu_enabled)
+		return xscale_read_memory(target, address, size, count, buffer);
+
+	/** \todo: provide a non-stub implementation of this routine. */
+	LOG_ERROR("%s: %s is not implemented.  Disable MMU?",
+			target_name(target), __func__);
+	return ERROR_FAIL;
+}
+
+static int xscale_bulk_write_memory(struct target *target, uint32_t address,
 		uint32_t count, uint8_t *buffer)
 {
 	return xscale_write_memory(target, address, 4, count, buffer);
 }
 
-static uint32_t xscale_get_ttb(target_t *target)
+static uint32_t xscale_get_ttb(struct target *target)
 {
 	struct xscale_common *xscale = target_to_xscale(target);
 	uint32_t ttb;
@@ -1980,7 +2037,7 @@ static uint32_t xscale_get_ttb(target_t *target)
 	return ttb;
 }
 
-static void xscale_disable_mmu_caches(target_t *target, int mmu,
+static void xscale_disable_mmu_caches(struct target *target, int mmu,
 		int d_u_cache, int i_cache)
 {
 	struct xscale_common *xscale = target_to_xscale(target);
@@ -2019,7 +2076,7 @@ static void xscale_disable_mmu_caches(target_t *target, int mmu,
 	xscale_send_u32(target, 0x53);
 }
 
-static void xscale_enable_mmu_caches(target_t *target, int mmu,
+static void xscale_enable_mmu_caches(struct target *target, int mmu,
 		int d_u_cache, int i_cache)
 {
 	struct xscale_common *xscale = target_to_xscale(target);
@@ -2045,7 +2102,7 @@ static void xscale_enable_mmu_caches(target_t *target, int mmu,
 	xscale_send_u32(target, 0x53);
 }
 
-static int xscale_set_breakpoint(struct target_s *target,
+static int xscale_set_breakpoint(struct target *target,
 		struct breakpoint *breakpoint)
 {
 	int retval;
@@ -2118,17 +2175,11 @@ static int xscale_set_breakpoint(struct target_s *target,
 	return ERROR_OK;
 }
 
-static int xscale_add_breakpoint(struct target_s *target,
+static int xscale_add_breakpoint(struct target *target,
 		struct breakpoint *breakpoint)
 {
 	struct xscale_common *xscale = target_to_xscale(target);
 
-	if (target->state != TARGET_HALTED)
-	{
-		LOG_WARNING("target not halted");
-		return ERROR_TARGET_NOT_HALTED;
-	}
-
 	if ((breakpoint->type == BKPT_HARD) && (xscale->ibcr_available < 1))
 	{
 		LOG_INFO("no breakpoint unit available for hardware breakpoint");
@@ -2149,7 +2200,7 @@ static int xscale_add_breakpoint(struct target_s *target,
 	return ERROR_OK;
 }
 
-static int xscale_unset_breakpoint(struct target_s *target,
+static int xscale_unset_breakpoint(struct target *target,
 		struct breakpoint *breakpoint)
 {
 	int retval;
@@ -2204,7 +2255,7 @@ static int xscale_unset_breakpoint(struct target_s *target,
 	return ERROR_OK;
 }
 
-static int xscale_remove_breakpoint(struct target_s *target, struct breakpoint *breakpoint)
+static int xscale_remove_breakpoint(struct target *target, struct breakpoint *breakpoint)
 {
 	struct xscale_common *xscale = target_to_xscale(target);
 
@@ -2225,12 +2276,12 @@ static int xscale_remove_breakpoint(struct target_s *target, struct breakpoint *
 	return ERROR_OK;
 }
 
-static int xscale_set_watchpoint(struct target_s *target,
+static int xscale_set_watchpoint(struct target *target,
 		struct watchpoint *watchpoint)
 {
 	struct xscale_common *xscale = target_to_xscale(target);
 	uint8_t enable = 0;
-	reg_t *dbcon = &xscale->reg_cache->reg_list[XSCALE_DBCON];
+	struct reg *dbcon = &xscale->reg_cache->reg_list[XSCALE_DBCON];
 	uint32_t dbcon_value = buf_get_u32(dbcon->value, 0, 32);
 
 	if (target->state != TARGET_HALTED)
@@ -2281,17 +2332,11 @@ static int xscale_set_watchpoint(struct target_s *target,
 	return ERROR_OK;
 }
 
-static int xscale_add_watchpoint(struct target_s *target,
+static int xscale_add_watchpoint(struct target *target,
 		struct watchpoint *watchpoint)
 {
 	struct xscale_common *xscale = target_to_xscale(target);
 
-	if (target->state != TARGET_HALTED)
-	{
-		LOG_WARNING("target not halted");
-		return ERROR_TARGET_NOT_HALTED;
-	}
-
 	if (xscale->dbr_available < 1)
 	{
 		return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
@@ -2307,11 +2352,11 @@ static int xscale_add_watchpoint(struct target_s *target,
 	return ERROR_OK;
 }
 
-static int xscale_unset_watchpoint(struct target_s *target,
+static int xscale_unset_watchpoint(struct target *target,
 		struct watchpoint *watchpoint)
 {
 	struct xscale_common *xscale = target_to_xscale(target);
-	reg_t *dbcon = &xscale->reg_cache->reg_list[XSCALE_DBCON];
+	struct reg *dbcon = &xscale->reg_cache->reg_list[XSCALE_DBCON];
 	uint32_t dbcon_value = buf_get_u32(dbcon->value, 0, 32);
 
 	if (target->state != TARGET_HALTED)
@@ -2343,7 +2388,7 @@ static int xscale_unset_watchpoint(struct target_s *target,
 	return ERROR_OK;
 }
 
-static int xscale_remove_watchpoint(struct target_s *target, struct watchpoint *watchpoint)
+static int xscale_remove_watchpoint(struct target *target, struct watchpoint *watchpoint)
 {
 	struct xscale_common *xscale = target_to_xscale(target);
 
@@ -2363,10 +2408,10 @@ static int xscale_remove_watchpoint(struct target_s *target, struct watchpoint *
 	return ERROR_OK;
 }
 
-static int xscale_get_reg(reg_t *reg)
+static int xscale_get_reg(struct reg *reg)
 {
 	struct xscale_reg *arch_info = reg->arch_info;
-	target_t *target = arch_info->target;
+	struct target *target = arch_info->target;
 	struct xscale_common *xscale = target_to_xscale(target);
 
 	/* DCSR, TX and RX are accessible via JTAG */
@@ -2408,10 +2453,10 @@ static int xscale_get_reg(reg_t *reg)
 	return ERROR_OK;
 }
 
-static int xscale_set_reg(reg_t *reg, uint8_t* buf)
+static int xscale_set_reg(struct reg *reg, uint8_t* buf)
 {
 	struct xscale_reg *arch_info = reg->arch_info;
-	target_t *target = arch_info->target;
+	struct target *target = arch_info->target;
 	struct xscale_common *xscale = target_to_xscale(target);
 	uint32_t value = buf_get_u32(buf, 0, 32);
 
@@ -2452,10 +2497,10 @@ static int xscale_set_reg(reg_t *reg, uint8_t* buf)
 	return ERROR_OK;
 }
 
-static int xscale_write_dcsr_sw(target_t *target, uint32_t value)
+static int xscale_write_dcsr_sw(struct target *target, uint32_t value)
 {
 	struct xscale_common *xscale = target_to_xscale(target);
-	reg_t *dcsr = &xscale->reg_cache->reg_list[XSCALE_DCSR];
+	struct reg *dcsr = &xscale->reg_cache->reg_list[XSCALE_DCSR];
 	struct xscale_reg *dcsr_arch_info = dcsr->arch_info;
 
 	/* send CP write request (command 0x41) */
@@ -2471,10 +2516,10 @@ static int xscale_write_dcsr_sw(target_t *target, uint32_t value)
 	return ERROR_OK;
 }
 
-static int xscale_read_trace(target_t *target)
+static int xscale_read_trace(struct target *target)
 {
 	struct xscale_common *xscale = target_to_xscale(target);
-	struct armv4_5_common_s *armv4_5 = &xscale->armv4_5_common;
+	struct arm *armv4_5 = &xscale->armv4_5_common;
 	struct xscale_trace_data **trace_data_p;
 
 	/* 258 words from debug handler
@@ -2533,7 +2578,8 @@ static int xscale_read_trace(target_t *target)
 	(*trace_data_p)->next = NULL;
 	(*trace_data_p)->chkpt0 = trace_buffer[256];
 	(*trace_data_p)->chkpt1 = trace_buffer[257];
-	(*trace_data_p)->last_instruction = buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32);
+	(*trace_data_p)->last_instruction =
+			buf_get_u32(armv4_5->pc->value, 0, 32);
 	(*trace_data_p)->entries = malloc(sizeof(struct xscale_trace_entry) * (256 - j));
 	(*trace_data_p)->depth = 256 - j;
 
@@ -2549,13 +2595,13 @@ static int xscale_read_trace(target_t *target)
 	return ERROR_OK;
 }
 
-static int xscale_read_instruction(target_t *target,
+static int xscale_read_instruction(struct target *target,
 		struct arm_instruction *instruction)
 {
 	struct xscale_common *xscale = target_to_xscale(target);
 	int i;
 	int section = -1;
-	uint32_t size_read;
+	size_t size_read;
 	uint32_t opcode;
 	int retval;
 
@@ -2579,7 +2625,7 @@ static int xscale_read_instruction(target_t *target,
 		return ERROR_TRACE_INSTRUCTION_UNAVAILABLE;
 	}
 
-	if (xscale->trace.core_state == ARMV4_5_STATE_ARM)
+	if (xscale->trace.core_state == ARM_STATE_ARM)
 	{
 		uint8_t buf[4];
 		if ((retval = image_read_section(xscale->trace.image, section,
@@ -2592,7 +2638,7 @@ static int xscale_read_instruction(target_t *target,
 		opcode = target_buffer_get_u32(target, buf);
 		arm_evaluate_opcode(opcode, xscale->trace.current_pc, instruction);
 	}
-	else if (xscale->trace.core_state == ARMV4_5_STATE_THUMB)
+	else if (xscale->trace.core_state == ARM_STATE_THUMB)
 	{
 		uint8_t buf[2];
 		if ((retval = image_read_section(xscale->trace.image, section,
@@ -2630,7 +2676,7 @@ static int xscale_branch_address(struct xscale_trace_data *trace_data,
 	return 0;
 }
 
-static int xscale_analyze_trace(target_t *target, command_context_t *cmd_ctx)
+static int xscale_analyze_trace(struct target *target, struct command_context *cmd_ctx)
 {
 	struct xscale_common *xscale = target_to_xscale(target);
 	int next_pc_ok = 0;
@@ -2644,7 +2690,7 @@ static int xscale_analyze_trace(target_t *target, command_context_t *cmd_ctx)
 		int rollover;
 		int branch;
 		int exception;
-		xscale->trace.core_state = ARMV4_5_STATE_ARM;
+		xscale->trace.core_state = ARM_STATE_ARM;
 
 		chkpt = 0;
 		rollover = 0;
@@ -2778,7 +2824,7 @@ static int xscale_analyze_trace(target_t *target, command_context_t *cmd_ctx)
 					}
 					else
 					{
-						xscale->trace.current_pc += (xscale->trace.core_state == ARMV4_5_STATE_ARM) ? 4 : 2;
+						xscale->trace.current_pc += (xscale->trace.core_state == ARM_STATE_ARM) ? 4 : 2;
 					}
 					command_print(cmd_ctx, "%s", instruction.text);
 				}
@@ -2793,7 +2839,7 @@ static int xscale_analyze_trace(target_t *target, command_context_t *cmd_ctx)
 			}
 		}
 
-		for (; xscale->trace.current_pc < trace_data->last_instruction; xscale->trace.current_pc += (xscale->trace.core_state == ARMV4_5_STATE_ARM) ? 4 : 2)
+		for (; xscale->trace.current_pc < trace_data->last_instruction; xscale->trace.current_pc += (xscale->trace.core_state == ARM_STATE_ARM) ? 4 : 2)
 		{
 			struct arm_instruction instruction;
 			if ((retval = xscale_read_instruction(target, &instruction)) != ERROR_OK)
@@ -2817,21 +2863,21 @@ static int xscale_analyze_trace(target_t *target, command_context_t *cmd_ctx)
 	return ERROR_OK;
 }
 
-static void xscale_build_reg_cache(target_t *target)
+static const struct reg_arch_type xscale_reg_type = {
+	.get = xscale_get_reg,
+	.set = xscale_set_reg,
+};
+
+static void xscale_build_reg_cache(struct target *target)
 {
 	struct xscale_common *xscale = target_to_xscale(target);
-	struct armv4_5_common_s *armv4_5 = &xscale->armv4_5_common;
+	struct arm *armv4_5 = &xscale->armv4_5_common;
 	struct reg_cache **cache_p = register_get_last_cache_p(&target->reg_cache);
 	struct xscale_reg *arch_info = malloc(sizeof(xscale_reg_arch_info));
 	int i;
-	int num_regs = sizeof(xscale_reg_arch_info) / sizeof(struct xscale_reg);
+	int num_regs = ARRAY_SIZE(xscale_reg_arch_info);
 
-	(*cache_p) = armv4_5_build_reg_cache(target, armv4_5);
-	armv4_5->core_cache = (*cache_p);
-
-	/* register a register arch-type for XScale dbg registers only once */
-	if (xscale_reg_arch_type == -1)
-		xscale_reg_arch_type = register_reg_arch_type(xscale_get_reg, xscale_set_reg);
+	(*cache_p) = arm_build_reg_cache(target, armv4_5);
 
 	(*cache_p)->next = malloc(sizeof(struct reg_cache));
 	cache_p = &(*cache_p)->next;
@@ -2839,7 +2885,7 @@ static void xscale_build_reg_cache(target_t *target)
 	/* fill in values for the xscale reg cache */
 	(*cache_p)->name = "XScale registers";
 	(*cache_p)->next = NULL;
-	(*cache_p)->reg_list = malloc(num_regs * sizeof(reg_t));
+	(*cache_p)->reg_list = malloc(num_regs * sizeof(struct reg));
 	(*cache_p)->num_regs = num_regs;
 
 	for (i = 0; i < num_regs; i++)
@@ -2849,10 +2895,8 @@ static void xscale_build_reg_cache(target_t *target)
 		(*cache_p)->reg_list[i].dirty = 0;
 		(*cache_p)->reg_list[i].valid = 0;
 		(*cache_p)->reg_list[i].size = 32;
-		(*cache_p)->reg_list[i].bitfield_desc = NULL;
-		(*cache_p)->reg_list[i].num_bitfields = 0;
 		(*cache_p)->reg_list[i].arch_info = &arch_info[i];
-		(*cache_p)->reg_list[i].arch_type = xscale_reg_arch_type;
+		(*cache_p)->reg_list[i].type = &xscale_reg_type;
 		arch_info[i] = xscale_reg_arch_info[i];
 		arch_info[i].target = target;
 	}
@@ -2860,14 +2904,14 @@ static void xscale_build_reg_cache(target_t *target)
 	xscale->reg_cache = (*cache_p);
 }
 
-static int xscale_init_target(struct command_context_s *cmd_ctx,
-		struct target_s *target)
+static int xscale_init_target(struct command_context *cmd_ctx,
+		struct target *target)
 {
 	xscale_build_reg_cache(target);
 	return ERROR_OK;
 }
 
-static int xscale_init_arch_info(target_t *target,
+static int xscale_init_arch_info(struct target *target,
 		struct xscale_common *xscale, struct jtag_tap *tap, const char *variant)
 {
 	struct arm *armv4_5;
@@ -2876,10 +2920,10 @@ static int xscale_init_arch_info(target_t *target,
 
 	armv4_5 = &xscale->armv4_5_common;
 
-	/* store architecture specfic data (none so far) */
+	/* store architecture specfic data */
 	xscale->common_magic = XSCALE_COMMON_MAGIC;
 
-	/* we don't really *need* variant info ... */
+	/* we don't really *need* a variant param ... */
 	if (variant) {
 		int ir_length = 0;
 
@@ -2892,6 +2936,8 @@ static int xscale_init_arch_info(target_t *target,
 				|| strcmp(variant, "ixp45x") == 0
 				|| strcmp(variant, "ixp46x") == 0)
 			ir_length = 7;
+		else if (strcmp(variant, "pxa3xx") == 0)
+			ir_length = 11;
 		else
 			LOG_WARNING("%s: unrecognized variant %s",
 				tap->dotted_name, variant);
@@ -2903,6 +2949,12 @@ static int xscale_init_arch_info(target_t *target,
 		}
 	}
 
+	/* PXA3xx shifts the JTAG instructions */
+	if (tap->ir_length == 11)
+		xscale->xscale_variant = XSCALE_PXA3XX;
+	else
+		xscale->xscale_variant = XSCALE_IXP4XX_PXA2XX;
+
 	/* the debug handler isn't installed (and thus not running) at this time */
 	xscale->handler_address = 0xfe000800;
 
@@ -2941,6 +2993,9 @@ static int xscale_init_arch_info(target_t *target,
 	xscale->dbr0_used = 0;
 	xscale->dbr1_used = 0;
 
+	LOG_INFO("%s: hardware has 2 breakpoints and 2 watchpoints",
+			target_name(target));
+
 	xscale->arm_bkpt = ARMV5_BKPT(0x0);
 	xscale->thumb_bkpt = ARMV5_T_BKPT(0x0) & 0xffff;
 
@@ -2958,7 +3013,7 @@ static int xscale_init_arch_info(target_t *target,
 	armv4_5->write_core_reg = xscale_write_core_reg;
 	armv4_5->full_context = xscale_full_context;
 
-	armv4_5_init_arch_info(target, armv4_5);
+	arm_init_arch_info(target, armv4_5);
 
 	xscale->armv4_5_mmu.armv4_5_cache.ctype = -1;
 	xscale->armv4_5_mmu.get_ttb = xscale_get_ttb;
@@ -2972,7 +3027,7 @@ static int xscale_init_arch_info(target_t *target,
 	return ERROR_OK;
 }
 
-static int xscale_target_create(struct target_s *target, Jim_Interp *interp)
+static int xscale_target_create(struct target *target, Jim_Interp *interp)
 {
 	struct xscale_common *xscale;
 
@@ -2991,29 +3046,29 @@ static int xscale_target_create(struct target_s *target, Jim_Interp *interp)
 
 COMMAND_HANDLER(xscale_handle_debug_handler_command)
 {
-	target_t *target = NULL;
+	struct target *target = NULL;
 	struct xscale_common *xscale;
 	int retval;
 	uint32_t handler_address;
 
-	if (argc < 2)
+	if (CMD_ARGC < 2)
 	{
 		LOG_ERROR("'xscale debug_handler <target#> <address>' command takes two required operands");
 		return ERROR_OK;
 	}
 
-	if ((target = get_target(args[0])) == NULL)
+	if ((target = get_target(CMD_ARGV[0])) == NULL)
 	{
-		LOG_ERROR("target '%s' not defined", args[0]);
+		LOG_ERROR("target '%s' not defined", CMD_ARGV[0]);
 		return ERROR_FAIL;
 	}
 
 	xscale = target_to_xscale(target);
-	retval = xscale_verify_pointer(cmd_ctx, xscale);
+	retval = xscale_verify_pointer(CMD_CTX, xscale);
 	if (retval != ERROR_OK)
 		return retval;
 
-	COMMAND_PARSE_NUMBER(u32, args[1], handler_address);
+	COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], handler_address);
 
 	if (((handler_address >= 0x800) && (handler_address <= 0x1fef800)) ||
 		((handler_address >= 0xfe000800) && (handler_address <= 0xfffff800)))
@@ -3031,28 +3086,28 @@ COMMAND_HANDLER(xscale_handle_debug_handler_command)
 
 COMMAND_HANDLER(xscale_handle_cache_clean_address_command)
 {
-	target_t *target = NULL;
+	struct target *target = NULL;
 	struct xscale_common *xscale;
 	int retval;
 	uint32_t cache_clean_address;
 
-	if (argc < 2)
+	if (CMD_ARGC < 2)
 	{
 		return ERROR_COMMAND_SYNTAX_ERROR;
 	}
 
-	target = get_target(args[0]);
+	target = get_target(CMD_ARGV[0]);
 	if (target == NULL)
 	{
-		LOG_ERROR("target '%s' not defined", args[0]);
+		LOG_ERROR("target '%s' not defined", CMD_ARGV[0]);
 		return ERROR_FAIL;
 	}
 	xscale = target_to_xscale(target);
-	retval = xscale_verify_pointer(cmd_ctx, xscale);
+	retval = xscale_verify_pointer(CMD_CTX, xscale);
 	if (retval != ERROR_OK)
 		return retval;
 
-	COMMAND_PARSE_NUMBER(u32, args[1], cache_clean_address);
+	COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], cache_clean_address);
 
 	if (cache_clean_address & 0xffff)
 	{
@@ -3068,18 +3123,18 @@ COMMAND_HANDLER(xscale_handle_cache_clean_address_command)
 
 COMMAND_HANDLER(xscale_handle_cache_info_command)
 {
-	target_t *target = get_current_target(cmd_ctx);
+	struct target *target = get_current_target(CMD_CTX);
 	struct xscale_common *xscale = target_to_xscale(target);
 	int retval;
 
-	retval = xscale_verify_pointer(cmd_ctx, xscale);
+	retval = xscale_verify_pointer(CMD_CTX, xscale);
 	if (retval != ERROR_OK)
 		return retval;
 
-	return armv4_5_handle_cache_info_command(cmd_ctx, &xscale->armv4_5_mmu.armv4_5_cache);
+	return armv4_5_handle_cache_info_command(CMD_CTX, &xscale->armv4_5_mmu.armv4_5_cache);
 }
 
-static int xscale_virt2phys(struct target_s *target,
+static int xscale_virt2phys(struct target *target,
 		uint32_t virtual, uint32_t *physical)
 {
 	struct xscale_common *xscale = target_to_xscale(target);
@@ -3102,7 +3157,7 @@ static int xscale_virt2phys(struct target_s *target,
 	return ERROR_OK;
 }
 
-static int xscale_mmu(struct target_s *target, int *enabled)
+static int xscale_mmu(struct target *target, int *enabled)
 {
 	struct xscale_common *xscale = target_to_xscale(target);
 
@@ -3117,114 +3172,99 @@ static int xscale_mmu(struct target_s *target, int *enabled)
 
 COMMAND_HANDLER(xscale_handle_mmu_command)
 {
-	target_t *target = get_current_target(cmd_ctx);
+	struct target *target = get_current_target(CMD_CTX);
 	struct xscale_common *xscale = target_to_xscale(target);
 	int retval;
 
-	retval = xscale_verify_pointer(cmd_ctx, xscale);
+	retval = xscale_verify_pointer(CMD_CTX, xscale);
 	if (retval != ERROR_OK)
 		return retval;
 
 	if (target->state != TARGET_HALTED)
 	{
-		command_print(cmd_ctx, "target must be stopped for \"%s\" command", CMD_NAME);
+		command_print(CMD_CTX, "target must be stopped for \"%s\" command", CMD_NAME);
 		return ERROR_OK;
 	}
 
-	if (argc >= 1)
+	if (CMD_ARGC >= 1)
 	{
-		if (strcmp("enable", args[0]) == 0)
-		{
+		bool enable;
+		COMMAND_PARSE_ENABLE(CMD_ARGV[0], enable);
+		if (enable)
 			xscale_enable_mmu_caches(target, 1, 0, 0);
-			xscale->armv4_5_mmu.mmu_enabled = 1;
-		}
-		else if (strcmp("disable", args[0]) == 0)
-		{
+		else
 			xscale_disable_mmu_caches(target, 1, 0, 0);
-			xscale->armv4_5_mmu.mmu_enabled = 0;
-		}
+		xscale->armv4_5_mmu.mmu_enabled = enable;
 	}
 
-	command_print(cmd_ctx, "mmu %s", (xscale->armv4_5_mmu.mmu_enabled) ? "enabled" : "disabled");
+	command_print(CMD_CTX, "mmu %s", (xscale->armv4_5_mmu.mmu_enabled) ? "enabled" : "disabled");
 
 	return ERROR_OK;
 }
 
 COMMAND_HANDLER(xscale_handle_idcache_command)
 {
-	target_t *target = get_current_target(cmd_ctx);
+	struct target *target = get_current_target(CMD_CTX);
 	struct xscale_common *xscale = target_to_xscale(target);
-	int icache = 0, dcache = 0;
-	int retval;
 
-	retval = xscale_verify_pointer(cmd_ctx, xscale);
+	int retval = xscale_verify_pointer(CMD_CTX, xscale);
 	if (retval != ERROR_OK)
 		return retval;
 
 	if (target->state != TARGET_HALTED)
 	{
-		command_print(cmd_ctx, "target must be stopped for \"%s\" command", CMD_NAME);
+		command_print(CMD_CTX, "target must be stopped for \"%s\" command", CMD_NAME);
 		return ERROR_OK;
 	}
 
-	if (strcmp(CMD_NAME, "icache") == 0)
-		icache = 1;
-	else if (strcmp(CMD_NAME, "dcache") == 0)
-		dcache = 1;
+	bool icache;
+	COMMAND_PARSE_BOOL(CMD_NAME, icache, "icache", "dcache");
 
-	if (argc >= 1)
+	if (CMD_ARGC >= 1)
 	{
-		if (strcmp("enable", args[0]) == 0)
-		{
-			xscale_enable_mmu_caches(target, 0, dcache, icache);
-
-			if (icache)
-				xscale->armv4_5_mmu.armv4_5_cache.i_cache_enabled = 1;
-			else if (dcache)
-				xscale->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled = 1;
-		}
-		else if (strcmp("disable", args[0]) == 0)
-		{
-			xscale_disable_mmu_caches(target, 0, dcache, icache);
-
-			if (icache)
-				xscale->armv4_5_mmu.armv4_5_cache.i_cache_enabled = 0;
-			else if (dcache)
-				xscale->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled = 0;
-		}
+		bool enable;
+		COMMAND_PARSE_ENABLE(CMD_ARGV[0], enable);
+		if (enable)
+			xscale_enable_mmu_caches(target, 1, 0, 0);
+		else
+			xscale_disable_mmu_caches(target, 1, 0, 0);
+		if (icache)
+			xscale->armv4_5_mmu.armv4_5_cache.i_cache_enabled = enable;
+		else
+			xscale->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled = enable;
 	}
 
-	if (icache)
-		command_print(cmd_ctx, "icache %s", (xscale->armv4_5_mmu.armv4_5_cache.i_cache_enabled) ? "enabled" : "disabled");
-
-	if (dcache)
-		command_print(cmd_ctx, "dcache %s", (xscale->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled) ? "enabled" : "disabled");
+	bool enabled = icache ?
+					xscale->armv4_5_mmu.armv4_5_cache.i_cache_enabled :
+					xscale->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled;
+	const char *msg = enabled ? "enabled" : "disabled";
+	command_print(CMD_CTX, "%s %s", CMD_NAME, msg);
 
 	return ERROR_OK;
 }
 
 COMMAND_HANDLER(xscale_handle_vector_catch_command)
 {
-	target_t *target = get_current_target(cmd_ctx);
+	struct target *target = get_current_target(CMD_CTX);
 	struct xscale_common *xscale = target_to_xscale(target);
 	int retval;
 
-	retval = xscale_verify_pointer(cmd_ctx, xscale);
+	retval = xscale_verify_pointer(CMD_CTX, xscale);
 	if (retval != ERROR_OK)
 		return retval;
 
-	if (argc < 1)
+	if (CMD_ARGC < 1)
 	{
-		command_print(cmd_ctx, "usage: xscale vector_catch [mask]");
+		command_print(CMD_CTX, "usage: xscale vector_catch [mask]");
 	}
 	else
 	{
-		COMMAND_PARSE_NUMBER(u8, args[0], xscale->vector_catch);
+		COMMAND_PARSE_NUMBER(u8, CMD_ARGV[0], xscale->vector_catch);
 		buf_set_u32(xscale->reg_cache->reg_list[XSCALE_DCSR].value, 16, 8, xscale->vector_catch);
 		xscale_write_dcsr(target, -1, -1);
 	}
 
-	command_print(cmd_ctx, "vector catch mask: 0x%2.2x", xscale->vector_catch);
+	command_print(CMD_CTX, "vector catch mask: 0x%2.2x", xscale->vector_catch);
 
 	return ERROR_OK;
 }
@@ -3232,47 +3272,47 @@ COMMAND_HANDLER(xscale_handle_vector_catch_command)
 
 COMMAND_HANDLER(xscale_handle_vector_table_command)
 {
-	target_t *target = get_current_target(cmd_ctx);
+	struct target *target = get_current_target(CMD_CTX);
 	struct xscale_common *xscale = target_to_xscale(target);
 	int err = 0;
 	int retval;
 
-	retval = xscale_verify_pointer(cmd_ctx, xscale);
+	retval = xscale_verify_pointer(CMD_CTX, xscale);
 	if (retval != ERROR_OK)
 		return retval;
 
-	if (argc == 0) /* print current settings */
+	if (CMD_ARGC == 0) /* print current settings */
 	{
 		int idx;
 
-		command_print(cmd_ctx, "active user-set static vectors:");
+		command_print(CMD_CTX, "active user-set static vectors:");
 		for (idx = 1; idx < 8; idx++)
 			if (xscale->static_low_vectors_set & (1 << idx))
-				command_print(cmd_ctx, "low  %d: 0x%" PRIx32, idx, xscale->static_low_vectors[idx]);
+				command_print(CMD_CTX, "low  %d: 0x%" PRIx32, idx, xscale->static_low_vectors[idx]);
 		for (idx = 1; idx < 8; idx++)
 			if (xscale->static_high_vectors_set & (1 << idx))
-				command_print(cmd_ctx, "high %d: 0x%" PRIx32, idx, xscale->static_high_vectors[idx]);
+				command_print(CMD_CTX, "high %d: 0x%" PRIx32, idx, xscale->static_high_vectors[idx]);
 		return ERROR_OK;
 	}
 
-	if (argc != 3)
+	if (CMD_ARGC != 3)
 		err = 1;
 	else
 	{
 		int idx;
-		COMMAND_PARSE_NUMBER(int, args[1], idx);
+		COMMAND_PARSE_NUMBER(int, CMD_ARGV[1], idx);
 		uint32_t vec;
-		COMMAND_PARSE_NUMBER(u32, args[2], vec);
+		COMMAND_PARSE_NUMBER(u32, CMD_ARGV[2], vec);
 
 		if (idx < 1 || idx >= 8)
 			err = 1;
 
-		if (!err && strcmp(args[0], "low") == 0)
+		if (!err && strcmp(CMD_ARGV[0], "low") == 0)
 		{
 			xscale->static_low_vectors_set |= (1<<idx);
 			xscale->static_low_vectors[idx] = vec;
 		}
-		else if (!err && (strcmp(args[0], "high") == 0))
+		else if (!err && (strcmp(CMD_ARGV[0], "high") == 0))
 		{
 			xscale->static_high_vectors_set |= (1<<idx);
 			xscale->static_high_vectors[idx] = vec;
@@ -3282,7 +3322,7 @@ COMMAND_HANDLER(xscale_handle_vector_table_command)
 	}
 
 	if (err)
-		command_print(cmd_ctx, "usage: xscale vector_table <high|low> <index> <code>");
+		command_print(CMD_CTX, "usage: xscale vector_table <high|low> <index> <code>");
 
 	return ERROR_OK;
 }
@@ -3290,23 +3330,23 @@ COMMAND_HANDLER(xscale_handle_vector_table_command)
 
 COMMAND_HANDLER(xscale_handle_trace_buffer_command)
 {
-	target_t *target = get_current_target(cmd_ctx);
+	struct target *target = get_current_target(CMD_CTX);
 	struct xscale_common *xscale = target_to_xscale(target);
-	struct armv4_5_common_s *armv4_5 = &xscale->armv4_5_common;
+	struct arm *armv4_5 = &xscale->armv4_5_common;
 	uint32_t dcsr_value;
 	int retval;
 
-	retval = xscale_verify_pointer(cmd_ctx, xscale);
+	retval = xscale_verify_pointer(CMD_CTX, xscale);
 	if (retval != ERROR_OK)
 		return retval;
 
 	if (target->state != TARGET_HALTED)
 	{
-		command_print(cmd_ctx, "target must be stopped for \"%s\" command", CMD_NAME);
+		command_print(CMD_CTX, "target must be stopped for \"%s\" command", CMD_NAME);
 		return ERROR_OK;
 	}
 
-	if ((argc >= 1) && (strcmp("enable", args[0]) == 0))
+	if ((CMD_ARGC >= 1) && (strcmp("enable", CMD_ARGV[0]) == 0))
 	{
 		struct xscale_trace_data *td, *next_td;
 		xscale->trace.buffer_enabled = 1;
@@ -3324,19 +3364,19 @@ COMMAND_HANDLER(xscale_handle_trace_buffer_command)
 		}
 		xscale->trace.data = NULL;
 	}
-	else if ((argc >= 1) && (strcmp("disable", args[0]) == 0))
+	else if ((CMD_ARGC >= 1) && (strcmp("disable", CMD_ARGV[0]) == 0))
 	{
 		xscale->trace.buffer_enabled = 0;
 	}
 
-	if ((argc >= 2) && (strcmp("fill", args[1]) == 0))
+	if ((CMD_ARGC >= 2) && (strcmp("fill", CMD_ARGV[1]) == 0))
 	{
 		uint32_t fill = 1;
-		if (argc >= 3)
-			COMMAND_PARSE_NUMBER(u32, args[2], fill);
+		if (CMD_ARGC >= 3)
+			COMMAND_PARSE_NUMBER(u32, CMD_ARGV[2], fill);
 		xscale->trace.buffer_fill = fill;
 	}
-	else if ((argc >= 2) && (strcmp("wrap", args[1]) == 0))
+	else if ((CMD_ARGC >= 2) && (strcmp("wrap", CMD_ARGV[1]) == 0))
 	{
 		xscale->trace.buffer_fill = -1;
 	}
@@ -3346,7 +3386,8 @@ COMMAND_HANDLER(xscale_handle_trace_buffer_command)
 		/* if we enable the trace buffer in fill-once
 		 * mode we know the address of the first instruction */
 		xscale->trace.pc_ok = 1;
-		xscale->trace.current_pc = buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32);
+		xscale->trace.current_pc =
+				buf_get_u32(armv4_5->pc->value, 0, 32);
 	}
 	else
 	{
@@ -3354,7 +3395,7 @@ COMMAND_HANDLER(xscale_handle_trace_buffer_command)
 		xscale->trace.pc_ok = 0;
 	}
 
-	command_print(cmd_ctx, "trace buffer %s (%s)",
+	command_print(CMD_CTX, "trace buffer %s (%s)",
 		(xscale->trace.buffer_enabled) ? "enabled" : "disabled",
 		(xscale->trace.buffer_fill > 0) ? "fill" : "wrap");
 
@@ -3369,17 +3410,17 @@ COMMAND_HANDLER(xscale_handle_trace_buffer_command)
 
 COMMAND_HANDLER(xscale_handle_trace_image_command)
 {
-	target_t *target = get_current_target(cmd_ctx);
+	struct target *target = get_current_target(CMD_CTX);
 	struct xscale_common *xscale = target_to_xscale(target);
 	int retval;
 
-	if (argc < 1)
+	if (CMD_ARGC < 1)
 	{
-		command_print(cmd_ctx, "usage: xscale trace_image <file> [base address] [type]");
+		command_print(CMD_CTX, "usage: xscale trace_image <file> [base address] [type]");
 		return ERROR_OK;
 	}
 
-	retval = xscale_verify_pointer(cmd_ctx, xscale);
+	retval = xscale_verify_pointer(CMD_CTX, xscale);
 	if (retval != ERROR_OK)
 		return retval;
 
@@ -3387,7 +3428,7 @@ COMMAND_HANDLER(xscale_handle_trace_image_command)
 	{
 		image_close(xscale->trace.image);
 		free(xscale->trace.image);
-		command_print(cmd_ctx, "previously loaded image found and closed");
+		command_print(CMD_CTX, "previously loaded image found and closed");
 	}
 
 	xscale->trace.image = malloc(sizeof(struct image));
@@ -3395,17 +3436,17 @@ COMMAND_HANDLER(xscale_handle_trace_image_command)
 	xscale->trace.image->start_address_set = 0;
 
 	/* a base address isn't always necessary, default to 0x0 (i.e. don't relocate) */
-	if (argc >= 2)
+	if (CMD_ARGC >= 2)
 	{
 		xscale->trace.image->base_address_set = 1;
-		COMMAND_PARSE_NUMBER(int, args[1], xscale->trace.image->base_address);
+		COMMAND_PARSE_NUMBER(int, CMD_ARGV[1], xscale->trace.image->base_address);
 	}
 	else
 	{
 		xscale->trace.image->base_address_set = 0;
 	}
 
-	if (image_open(xscale->trace.image, args[0], (argc >= 3) ? args[2] : NULL) != ERROR_OK)
+	if (image_open(xscale->trace.image, CMD_ARGV[0], (CMD_ARGC >= 3) ? CMD_ARGV[2] : NULL) != ERROR_OK)
 	{
 		free(xscale->trace.image);
 		xscale->trace.image = NULL;
@@ -3417,25 +3458,25 @@ COMMAND_HANDLER(xscale_handle_trace_image_command)
 
 COMMAND_HANDLER(xscale_handle_dump_trace_command)
 {
-	target_t *target = get_current_target(cmd_ctx);
+	struct target *target = get_current_target(CMD_CTX);
 	struct xscale_common *xscale = target_to_xscale(target);
 	struct xscale_trace_data *trace_data;
 	struct fileio file;
 	int retval;
 
-	retval = xscale_verify_pointer(cmd_ctx, xscale);
+	retval = xscale_verify_pointer(CMD_CTX, xscale);
 	if (retval != ERROR_OK)
 		return retval;
 
 	if (target->state != TARGET_HALTED)
 	{
-		command_print(cmd_ctx, "target must be stopped for \"%s\" command", CMD_NAME);
+		command_print(CMD_CTX, "target must be stopped for \"%s\" command", CMD_NAME);
 		return ERROR_OK;
 	}
 
-	if (argc < 1)
+	if (CMD_ARGC < 1)
 	{
-		command_print(cmd_ctx, "usage: xscale dump_trace <file>");
+		command_print(CMD_CTX, "usage: xscale dump_trace <file>");
 		return ERROR_OK;
 	}
 
@@ -3443,11 +3484,11 @@ COMMAND_HANDLER(xscale_handle_dump_trace_command)
 
 	if (!trace_data)
 	{
-		command_print(cmd_ctx, "no trace data collected");
+		command_print(CMD_CTX, "no trace data collected");
 		return ERROR_OK;
 	}
 
-	if (fileio_open(&file, args[0], FILEIO_WRITE, FILEIO_BINARY) != ERROR_OK)
+	if (fileio_open(&file, CMD_ARGV[0], FILEIO_WRITE, FILEIO_BINARY) != ERROR_OK)
 	{
 		return ERROR_OK;
 	}
@@ -3474,39 +3515,39 @@ COMMAND_HANDLER(xscale_handle_dump_trace_command)
 
 COMMAND_HANDLER(xscale_handle_analyze_trace_buffer_command)
 {
-	target_t *target = get_current_target(cmd_ctx);
+	struct target *target = get_current_target(CMD_CTX);
 	struct xscale_common *xscale = target_to_xscale(target);
 	int retval;
 
-	retval = xscale_verify_pointer(cmd_ctx, xscale);
+	retval = xscale_verify_pointer(CMD_CTX, xscale);
 	if (retval != ERROR_OK)
 		return retval;
 
-	xscale_analyze_trace(target, cmd_ctx);
+	xscale_analyze_trace(target, CMD_CTX);
 
 	return ERROR_OK;
 }
 
 COMMAND_HANDLER(xscale_handle_cp15)
 {
-	target_t *target = get_current_target(cmd_ctx);
+	struct target *target = get_current_target(CMD_CTX);
 	struct xscale_common *xscale = target_to_xscale(target);
 	int retval;
 
-	retval = xscale_verify_pointer(cmd_ctx, xscale);
+	retval = xscale_verify_pointer(CMD_CTX, xscale);
 	if (retval != ERROR_OK)
 		return retval;
 
 	if (target->state != TARGET_HALTED)
 	{
-		command_print(cmd_ctx, "target must be stopped for \"%s\" command", CMD_NAME);
+		command_print(CMD_CTX, "target must be stopped for \"%s\" command", CMD_NAME);
 		return ERROR_OK;
 	}
 	uint32_t reg_no = 0;
-	reg_t *reg = NULL;
-	if (argc > 0)
+	struct reg *reg = NULL;
+	if (CMD_ARGC > 0)
 	{
-		COMMAND_PARSE_NUMBER(u32, args[0], reg_no);
+		COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], reg_no);
 		/*translate from xscale cp15 register no to openocd register*/
 		switch (reg_no)
 		{
@@ -3535,25 +3576,25 @@ COMMAND_HANDLER(xscale_handle_cp15)
 			reg_no = XSCALE_CPACCESS;
 			break;
 		default:
-			command_print(cmd_ctx, "invalid register number");
+			command_print(CMD_CTX, "invalid register number");
 			return ERROR_INVALID_ARGUMENTS;
 		}
 		reg = &xscale->reg_cache->reg_list[reg_no];
 
 	}
-	if (argc == 1)
+	if (CMD_ARGC == 1)
 	{
 		uint32_t value;
 
 		/* read cp15 control register */
 		xscale_get_reg(reg);
 		value = buf_get_u32(reg->value, 0, 32);
-		command_print(cmd_ctx, "%s (/%i): 0x%" PRIx32 "", reg->name, (int)(reg->size), value);
+		command_print(CMD_CTX, "%s (/%i): 0x%" PRIx32 "", reg->name, (int)(reg->size), value);
 	}
-	else if (argc == 2)
+	else if (CMD_ARGC == 2)
 	{
 		uint32_t value;
-		COMMAND_PARSE_NUMBER(u32, args[1], value);
+		COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], value);
 
 		/* send CP write request (command 0x41) */
 		xscale_send_u32(target, 0x41);
@@ -3569,42 +3610,128 @@ COMMAND_HANDLER(xscale_handle_cp15)
 	}
 	else
 	{
-		command_print(cmd_ctx, "usage: cp15 [register]<, [value]>");
+		command_print(CMD_CTX, "usage: cp15 [register]<, [value]>");
 	}
 
 	return ERROR_OK;
 }
 
-static int xscale_register_commands(struct command_context_s *cmd_ctx)
-{
-	command_t *xscale_cmd;
-
-	xscale_cmd = register_command(cmd_ctx, NULL, "xscale", NULL, COMMAND_ANY, "xscale specific commands");
-
-	register_command(cmd_ctx, xscale_cmd, "debug_handler", xscale_handle_debug_handler_command, COMMAND_ANY, "'xscale debug_handler <target#> <address>' command takes two required operands");
-	register_command(cmd_ctx, xscale_cmd, "cache_clean_address", xscale_handle_cache_clean_address_command, COMMAND_ANY, NULL);
-
-	register_command(cmd_ctx, xscale_cmd, "cache_info", xscale_handle_cache_info_command, COMMAND_EXEC, NULL);
-	register_command(cmd_ctx, xscale_cmd, "mmu", xscale_handle_mmu_command, COMMAND_EXEC, "['enable'|'disable'] the MMU");
-	register_command(cmd_ctx, xscale_cmd, "icache", xscale_handle_idcache_command, COMMAND_EXEC, "['enable'|'disable'] the ICache");
-	register_command(cmd_ctx, xscale_cmd, "dcache", xscale_handle_idcache_command, COMMAND_EXEC, "['enable'|'disable'] the DCache");
-
-	register_command(cmd_ctx, xscale_cmd, "vector_catch", xscale_handle_vector_catch_command, COMMAND_EXEC, "<mask> of vectors that should be catched");
-	register_command(cmd_ctx, xscale_cmd, "vector_table", xscale_handle_vector_table_command, COMMAND_EXEC, "<high|low> <index> <code> set static code for exception handler entry");
-
-	register_command(cmd_ctx, xscale_cmd, "trace_buffer", xscale_handle_trace_buffer_command, COMMAND_EXEC, "<enable | disable> ['fill' [n]|'wrap']");
-
-	register_command(cmd_ctx, xscale_cmd, "dump_trace", xscale_handle_dump_trace_command, COMMAND_EXEC, "dump content of trace buffer to <file>");
-	register_command(cmd_ctx, xscale_cmd, "analyze_trace", xscale_handle_analyze_trace_buffer_command, COMMAND_EXEC, "analyze content of trace buffer");
-	register_command(cmd_ctx, xscale_cmd, "trace_image", xscale_handle_trace_image_command,
-		COMMAND_EXEC, "load image from <file> [base address]");
-
-	register_command(cmd_ctx, xscale_cmd, "cp15", xscale_handle_cp15, COMMAND_EXEC, "access coproc 15 <register> [value]");
-
-	armv4_5_register_commands(cmd_ctx);
-
-	return ERROR_OK;
-}
+static const struct command_registration xscale_exec_command_handlers[] = {
+	{
+		.name = "cache_info",
+		.handler = xscale_handle_cache_info_command,
+		.mode = COMMAND_EXEC,
+		.help = "display information about CPU caches",
+	},
+	{
+		.name = "mmu",
+		.handler = xscale_handle_mmu_command,
+		.mode = COMMAND_EXEC,
+		.help = "enable or disable the MMU",
+		.usage = "['enable'|'disable']",
+	},
+	{
+		.name = "icache",
+		.handler = xscale_handle_idcache_command,
+		.mode = COMMAND_EXEC,
+		.help = "display ICache state, optionally enabling or "
+			"disabling it",
+		.usage = "['enable'|'disable']",
+	},
+	{
+		.name = "dcache",
+		.handler = xscale_handle_idcache_command,
+		.mode = COMMAND_EXEC,
+		.help = "display DCache state, optionally enabling or "
+			"disabling it",
+		.usage = "['enable'|'disable']",
+	},
+	{
+		.name = "vector_catch",
+		.handler = xscale_handle_vector_catch_command,
+		.mode = COMMAND_EXEC,
+		.help = "set or display 8-bit mask of vectors "
+			"that should trigger debug entry",
+		.usage = "[mask]",
+	},
+	{
+		.name = "vector_table",
+		.handler = xscale_handle_vector_table_command,
+		.mode = COMMAND_EXEC,
+		.help = "set vector table entry in mini-ICache, "
+			"or display current tables",
+		.usage = "[('high'|'low') index code]",
+	},
+	{
+		.name = "trace_buffer",
+		.handler = xscale_handle_trace_buffer_command,
+		.mode = COMMAND_EXEC,
+		.help = "display trace buffer status, enable or disable "
+			"tracing, and optionally reconfigure trace mode",
+		.usage = "['enable'|'disable' ['fill' number|'wrap']]",
+	},
+	{
+		.name = "dump_trace",
+		.handler = xscale_handle_dump_trace_command,
+		.mode = COMMAND_EXEC,
+		.help = "dump content of trace buffer to file",
+		.usage = "filename",
+	},
+	{
+		.name = "analyze_trace",
+		.handler = xscale_handle_analyze_trace_buffer_command,
+		.mode = COMMAND_EXEC,
+		.help = "analyze content of trace buffer",
+		.usage = "",
+	},
+	{
+		.name = "trace_image",
+		.handler = xscale_handle_trace_image_command,
+		.mode = COMMAND_EXEC,
+		.help = "load image from file to address (default 0)",
+		.usage = "filename [offset [filetype]]",
+	},
+	{
+		.name = "cp15",
+		.handler = xscale_handle_cp15,
+		.mode = COMMAND_EXEC,
+		.help = "Read or write coprocessor 15 register.",
+		.usage = "register [value]",
+	},
+	COMMAND_REGISTRATION_DONE
+};
+static const struct command_registration xscale_any_command_handlers[] = {
+	{
+		.name = "debug_handler",
+		.handler = xscale_handle_debug_handler_command,
+		.mode = COMMAND_ANY,
+		.help = "Change address used for debug handler.",
+		.usage = "target address",
+	},
+	{
+		.name = "cache_clean_address",
+		.handler = xscale_handle_cache_clean_address_command,
+		.mode = COMMAND_ANY,
+		.help = "Change address used for cleaning data cache.",
+		.usage = "address",
+	},
+	{
+		.chain = xscale_exec_command_handlers,
+	},
+	COMMAND_REGISTRATION_DONE
+};
+static const struct command_registration xscale_command_handlers[] = {
+	{
+		.chain = arm_command_handlers,
+	},
+	{
+		.name = "xscale",
+		.mode = COMMAND_ANY,
+		.help = "xscale command group",
+		.chain = xscale_any_command_handlers,
+	},
+	COMMAND_REGISTRATION_DONE
+};
 
 struct target_type xscale_target =
 {
@@ -3623,13 +3750,17 @@ struct target_type xscale_target =
 	.deassert_reset = xscale_deassert_reset,
 	.soft_reset_halt = NULL,
 
-	.get_gdb_reg_list = armv4_5_get_gdb_reg_list,
+	/* REVISIT on some cores, allow exporting iwmmxt registers ... */
+	.get_gdb_reg_list = arm_get_gdb_reg_list,
 
 	.read_memory = xscale_read_memory,
+	.read_phys_memory = xscale_read_phys_memory,
 	.write_memory = xscale_write_memory,
+	.write_phys_memory = xscale_write_phys_memory,
 	.bulk_write_memory = xscale_bulk_write_memory,
-	.checksum_memory = arm7_9_checksum_memory,
-	.blank_check_memory = arm7_9_blank_check_memory,
+
+	.checksum_memory = arm_checksum_memory,
+	.blank_check_memory = arm_blank_check_memory,
 
 	.run_algorithm = armv4_5_run_algorithm,
 
@@ -3638,7 +3769,7 @@ struct target_type xscale_target =
 	.add_watchpoint = xscale_add_watchpoint,
 	.remove_watchpoint = xscale_remove_watchpoint,
 
-	.register_commands = xscale_register_commands,
+	.commands = xscale_command_handlers,
 	.target_create = xscale_target_create,
 	.init_target = xscale_init_target,