X-Git-Url: https://review.openocd.org/gitweb?p=openocd.git;a=blobdiff_plain;f=src%2Ftarget%2Fxscale.c;h=4598872d163cd602330844c91c1cf49a12ca3159;hp=40126c92837cf746382be1ac4551eef5c1e21956;hb=ab33bdd46c3bb3acdb3f1b1f09a0e1a9393ef798;hpb=7a1ac49ac921964f48e0bbd9e1bf0d151d99b17e diff --git a/src/target/xscale.c b/src/target/xscale.c index 40126c9283..4598872d16 100644 --- a/src/target/xscale.c +++ b/src/target/xscale.c @@ -35,90 +35,52 @@ #include "time_support.h" #include "image.h" -/* cli handling */ -int xscale_register_commands(struct command_context_s *cmd_ctx); -/* forward declarations */ -int xscale_target_create(struct target_s *target, Jim_Interp *interp); -int xscale_init_target(struct command_context_s *cmd_ctx, struct target_s *target); -int xscale_quit(void); - -int xscale_arch_state(struct target_s *target); -int xscale_poll(target_t *target); -int xscale_halt(target_t *target); -int xscale_resume(struct target_s *target, int current, uint32_t address, int handle_breakpoints, int debug_execution); -int xscale_step(struct target_s *target, int current, uint32_t address, int handle_breakpoints); -int xscale_debug_entry(target_t *target); -int xscale_restore_context(target_t *target); - -int xscale_assert_reset(target_t *target); -int xscale_deassert_reset(target_t *target); -int xscale_soft_reset_halt(struct target_s *target); - -int xscale_set_reg_u32(reg_t *reg, uint32_t value); - -int xscale_read_core_reg(struct target_s *target, int num, enum armv4_5_mode mode); -int xscale_write_core_reg(struct target_s *target, int num, enum armv4_5_mode mode, uint32_t value); - -int xscale_read_memory(struct target_s *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer); -int xscale_write_memory(struct target_s *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer); -int xscale_bulk_write_memory(target_t *target, uint32_t address, uint32_t count, uint8_t *buffer); - -int xscale_add_breakpoint(struct target_s *target, breakpoint_t *breakpoint); -int xscale_remove_breakpoint(struct target_s *target, breakpoint_t *breakpoint); -int xscale_set_breakpoint(struct target_s *target, breakpoint_t *breakpoint); -int xscale_unset_breakpoint(struct target_s *target, breakpoint_t *breakpoint); -int xscale_add_watchpoint(struct target_s *target, watchpoint_t *watchpoint); -int xscale_remove_watchpoint(struct target_s *target, watchpoint_t *watchpoint); -void xscale_enable_watchpoints(struct target_s *target); -void xscale_enable_breakpoints(struct target_s *target); -static int xscale_virt2phys(struct target_s *target, uint32_t virtual, uint32_t *physical); -static int xscale_mmu(struct target_s *target, int *enabled); - -int xscale_read_trace(target_t *target); - -target_type_t xscale_target = -{ - .name = "xscale", - - .poll = xscale_poll, - .arch_state = xscale_arch_state, - - .target_request_data = NULL, - - .halt = xscale_halt, - .resume = xscale_resume, - .step = xscale_step, - - .assert_reset = xscale_assert_reset, - .deassert_reset = xscale_deassert_reset, - .soft_reset_halt = xscale_soft_reset_halt, - - .get_gdb_reg_list = armv4_5_get_gdb_reg_list, - - .read_memory = xscale_read_memory, - .write_memory = xscale_write_memory, - .bulk_write_memory = xscale_bulk_write_memory, - .checksum_memory = arm7_9_checksum_memory, - .blank_check_memory = arm7_9_blank_check_memory, - - .run_algorithm = armv4_5_run_algorithm, +/* + * Important XScale documents available as of October 2009 include: + * + * Intel XScale® Core Developer’s Manual, January 2004 + * Order Number: 273473-002 + * This has a chapter detailing debug facilities, and punts some + * details to chip-specific microarchitecture documents. + * + * Hot-Debug for Intel XScale® Core Debug White Paper, May 2005 + * Document Number: 273539-005 + * Less detailed than the developer's manual, but summarizes those + * missing details (for most XScales) and gives LOTS of notes about + * debugger/handler interaction issues. Presents a simpler reset + * and load-handler sequence than the arch doc. (Note, OpenOCD + * doesn't currently support "Hot-Debug" as defined there.) + * + * Chip-specific microarchitecture documents may also be useful. + */ - .add_breakpoint = xscale_add_breakpoint, - .remove_breakpoint = xscale_remove_breakpoint, - .add_watchpoint = xscale_add_watchpoint, - .remove_watchpoint = xscale_remove_watchpoint, - .register_commands = xscale_register_commands, - .target_create = xscale_target_create, - .init_target = xscale_init_target, - .quit = xscale_quit, - - .virt2phys = xscale_virt2phys, - .mmu = xscale_mmu -}; - -char* xscale_reg_list[] = +/* forward declarations */ +static int xscale_resume(struct target_s *, int current, + uint32_t address, int handle_breakpoints, int debug_execution); +static int xscale_debug_entry(target_t *); +static int xscale_restore_context(target_t *); +static int xscale_get_reg(reg_t *reg); +static int xscale_set_reg(reg_t *reg, uint8_t *buf); +static int xscale_set_breakpoint(struct target_s *, breakpoint_t *); +static int xscale_set_watchpoint(struct target_s *, watchpoint_t *); +static int xscale_unset_breakpoint(struct target_s *, breakpoint_t *); +static int xscale_read_trace(target_t *); + + +/* This XScale "debug handler" is loaded into the processor's + * mini-ICache, which is 2K of code writable only via JTAG. + * + * FIXME the OpenOCD "bin2char" utility currently doesn't handle + * binary files cleanly. It's string oriented, and terminates them + * with a NUL character. Better would be to generate the constants + * and let other code decide names, scoping, and other housekeeping. + */ +static /* unsigned const char xscale_debug_handler[] = ... */ +#include "xscale_debug.h" + +static char *const xscale_reg_list[] = { "XSCALE_MAINID", /* 0 */ "XSCALE_CACHETYPE", @@ -144,7 +106,7 @@ char* xscale_reg_list[] = "XSCALE_TXRXCTRL", }; -xscale_reg_t xscale_reg_arch_info[] = +static const xscale_reg_t xscale_reg_arch_info[] = { {XSCALE_MAINID, NULL}, {XSCALE_CACHETYPE, NULL}, @@ -170,12 +132,21 @@ xscale_reg_t xscale_reg_arch_info[] = {-1, NULL}, /* TXRXCTRL implicit access via JTAG */ }; -int xscale_reg_arch_type = -1; +static int xscale_reg_arch_type = -1; + +/* convenience wrapper to access XScale specific registers */ +static int xscale_set_reg_u32(reg_t *reg, uint32_t value) +{ + uint8_t buf[4]; + + buf_set_u32(buf, 0, 32, value); -int xscale_get_reg(reg_t *reg); -int xscale_set_reg(reg_t *reg, uint8_t *buf); + return xscale_set_reg(reg, buf); +} -int xscale_get_arch_pointers(target_t *target, armv4_5_common_t **armv4_5_p, xscale_common_t **xscale_p) + +static int xscale_get_arch_pointers(target_t *target, + armv4_5_common_t **armv4_5_p, xscale_common_t **xscale_p) { armv4_5_common_t *armv4_5 = target->arch_info; xscale_common_t *xscale = armv4_5->arch_info; @@ -198,7 +169,7 @@ int xscale_get_arch_pointers(target_t *target, armv4_5_common_t **armv4_5_p, xsc return ERROR_OK; } -int xscale_jtag_set_instr(jtag_tap_t *tap, uint32_t new_instr) +static int xscale_jtag_set_instr(jtag_tap_t *tap, uint32_t new_instr) { if (tap == NULL) return ERROR_FAIL; @@ -206,33 +177,25 @@ int xscale_jtag_set_instr(jtag_tap_t *tap, uint32_t new_instr) if (buf_get_u32(tap->cur_instr, 0, tap->ir_length) != new_instr) { scan_field_t field; + uint8_t scratch[4]; + memset(&field, 0, sizeof field); field.tap = tap; field.num_bits = tap->ir_length; - field.out_value = calloc(CEIL(field.num_bits, 8), 1); + field.out_value = scratch; buf_set_u32(field.out_value, 0, field.num_bits, new_instr); - uint8_t tmp[4]; - field.in_value = tmp; - jtag_add_ir_scan(1, &field, jtag_get_end_state()); - - /* FIX!!!! isn't this check superfluous? verify_ircapture handles this? */ - jtag_check_value_mask(&field, tap->expected, tap->expected_mask); - - free(field.out_value); } return ERROR_OK; } -int xscale_read_dcsr(target_t *target) +static int xscale_read_dcsr(target_t *target) { armv4_5_common_t *armv4_5 = target->arch_info; xscale_common_t *xscale = armv4_5->arch_info; - int retval; - scan_field_t fields[3]; uint8_t field0 = 0x0; uint8_t field0_check_value = 0x2; @@ -242,24 +205,24 @@ int xscale_read_dcsr(target_t *target) uint8_t field2_check_mask = 0x1; jtag_set_end_state(TAP_DRPAUSE); - xscale_jtag_set_instr(xscale->jtag_info.tap, xscale->jtag_info.dcsr); + xscale_jtag_set_instr(target->tap, XSCALE_SELDCSR); buf_set_u32(&field0, 1, 1, xscale->hold_rst); buf_set_u32(&field0, 2, 1, xscale->external_debug_break); - fields[0].tap = xscale->jtag_info.tap; + memset(&fields, 0, sizeof fields); + + fields[0].tap = target->tap; fields[0].num_bits = 3; fields[0].out_value = &field0; uint8_t tmp; fields[0].in_value = &tmp; - fields[1].tap = xscale->jtag_info.tap; + fields[1].tap = target->tap; fields[1].num_bits = 32; - fields[1].out_value = NULL; fields[1].in_value = xscale->reg_cache->reg_list[XSCALE_DCSR].value; - - fields[2].tap = xscale->jtag_info.tap; + fields[2].tap = target->tap; fields[2].num_bits = 1; fields[2].out_value = &field2; uint8_t tmp2; @@ -298,22 +261,18 @@ int xscale_read_dcsr(target_t *target) static void xscale_getbuf(jtag_callback_data_t arg) { - uint8_t *in = (uint8_t *)arg; + uint8_t *in = (uint8_t *)arg; *((uint32_t *)in) = buf_get_u32(in, 0, 32); } -int xscale_receive(target_t *target, uint32_t *buffer, int num_words) +static int xscale_receive(target_t *target, uint32_t *buffer, int num_words) { if (num_words == 0) return ERROR_INVALID_ARGUMENTS; int retval = ERROR_OK; - armv4_5_common_t *armv4_5 = target->arch_info; - xscale_common_t *xscale = armv4_5->arch_info; - tap_state_t path[3]; scan_field_t fields[3]; - uint8_t *field0 = malloc(num_words * 1); uint8_t field0_check_value = 0x2; uint8_t field0_check_mask = 0x6; @@ -322,35 +281,29 @@ int xscale_receive(target_t *target, uint32_t *buffer, int num_words) uint8_t field2_check_mask = 0x1; int words_done = 0; int words_scheduled = 0; - int i; path[0] = TAP_DRSELECT; path[1] = TAP_DRCAPTURE; path[2] = TAP_DRSHIFT; - fields[0].tap = xscale->jtag_info.tap; + memset(&fields, 0, sizeof fields); + + fields[0].tap = target->tap; fields[0].num_bits = 3; - fields[0].out_value = NULL; - fields[0].in_value = NULL; fields[0].check_value = &field0_check_value; fields[0].check_mask = &field0_check_mask; - fields[1].tap = xscale->jtag_info.tap; + fields[1].tap = target->tap; fields[1].num_bits = 32; - fields[1].out_value = NULL; - fields[1].check_value = NULL; - fields[1].check_mask = NULL; - fields[2].tap = xscale->jtag_info.tap; + fields[2].tap = target->tap; fields[2].num_bits = 1; - fields[2].out_value = NULL; - fields[2].in_value = NULL; fields[2].check_value = &field2_check_value; fields[2].check_mask = &field2_check_mask; jtag_set_end_state(TAP_IDLE); - xscale_jtag_set_instr(xscale->jtag_info.tap, xscale->jtag_info.dbgtx); + xscale_jtag_set_instr(target->tap, XSCALE_DBGTX); jtag_add_runtest(1, jtag_get_end_state()); /* ensures that we're in the TAP_IDLE state as the above could be a no-op */ /* repeat until all words have been collected */ @@ -416,16 +369,14 @@ int xscale_receive(target_t *target, uint32_t *buffer, int num_words) return retval; } -int xscale_read_tx(target_t *target, int consume) +static int xscale_read_tx(target_t *target, int consume) { armv4_5_common_t *armv4_5 = target->arch_info; xscale_common_t *xscale = armv4_5->arch_info; tap_state_t path[3]; tap_state_t noconsume_path[6]; - int retval; struct timeval timeout, now; - scan_field_t fields[3]; uint8_t field0_in = 0x0; uint8_t field0_check_value = 0x2; @@ -435,7 +386,7 @@ int xscale_read_tx(target_t *target, int consume) jtag_set_end_state(TAP_IDLE); - xscale_jtag_set_instr(xscale->jtag_info.tap, xscale->jtag_info.dbgtx); + xscale_jtag_set_instr(target->tap, XSCALE_DBGTX); path[0] = TAP_DRSELECT; path[1] = TAP_DRCAPTURE; @@ -448,20 +399,18 @@ int xscale_read_tx(target_t *target, int consume) noconsume_path[4] = TAP_DREXIT2; noconsume_path[5] = TAP_DRSHIFT; - fields[0].tap = xscale->jtag_info.tap; + memset(&fields, 0, sizeof fields); + + fields[0].tap = target->tap; fields[0].num_bits = 3; - fields[0].out_value = NULL; fields[0].in_value = &field0_in; - fields[1].tap = xscale->jtag_info.tap; + fields[1].tap = target->tap; fields[1].num_bits = 32; - fields[1].out_value = NULL; fields[1].in_value = xscale->reg_cache->reg_list[XSCALE_TX].value; - - fields[2].tap = xscale->jtag_info.tap; + fields[2].tap = target->tap; fields[2].num_bits = 1; - fields[2].out_value = NULL; uint8_t tmp; fields[2].in_value = &tmp; @@ -519,14 +468,12 @@ int xscale_read_tx(target_t *target, int consume) return ERROR_OK; } -int xscale_write_rx(target_t *target) +static int xscale_write_rx(target_t *target) { armv4_5_common_t *armv4_5 = target->arch_info; xscale_common_t *xscale = armv4_5->arch_info; - int retval; struct timeval timeout, now; - scan_field_t fields[3]; uint8_t field0_out = 0x0; uint8_t field0_in = 0x0; @@ -538,20 +485,20 @@ int xscale_write_rx(target_t *target) jtag_set_end_state(TAP_IDLE); - xscale_jtag_set_instr(xscale->jtag_info.tap, xscale->jtag_info.dbgrx); + xscale_jtag_set_instr(target->tap, XSCALE_DBGRX); + + memset(&fields, 0, sizeof fields); - fields[0].tap = xscale->jtag_info.tap; + fields[0].tap = target->tap; fields[0].num_bits = 3; fields[0].out_value = &field0_out; fields[0].in_value = &field0_in; - fields[1].tap = xscale->jtag_info.tap; + fields[1].tap = target->tap; fields[1].num_bits = 32; fields[1].out_value = xscale->reg_cache->reg_list[XSCALE_RX].value; - fields[1].in_value = NULL; - - fields[2].tap = xscale->jtag_info.tap; + fields[2].tap = target->tap; fields[2].num_bits = 1; fields[2].out_value = &field2; uint8_t tmp; @@ -608,20 +555,16 @@ int xscale_write_rx(target_t *target) } /* send count elements of size byte to the debug handler */ -int xscale_send(target_t *target, uint8_t *buffer, int count, int size) +static int xscale_send(target_t *target, uint8_t *buffer, int count, int size) { - armv4_5_common_t *armv4_5 = target->arch_info; - xscale_common_t *xscale = armv4_5->arch_info; uint32_t t[3]; int bits[3]; - int retval; - int done_count = 0; jtag_set_end_state(TAP_IDLE); - xscale_jtag_set_instr(xscale->jtag_info.tap, xscale->jtag_info.dbgrx); + xscale_jtag_set_instr(target->tap, XSCALE_DBGRX); bits[0]=3; t[0]=0; @@ -658,7 +601,7 @@ int xscale_send(target_t *target, uint8_t *buffer, int count, int size) LOG_ERROR("BUG: size neither 4, 2 nor 1"); exit(-1); } - jtag_add_dr_out(xscale->jtag_info.tap, + jtag_add_dr_out(target->tap, 3, bits, t, @@ -675,7 +618,7 @@ int xscale_send(target_t *target, uint8_t *buffer, int count, int size) return ERROR_OK; } -int xscale_send_u32(target_t *target, uint32_t value) +static int xscale_send_u32(target_t *target, uint32_t value) { armv4_5_common_t *armv4_5 = target->arch_info; xscale_common_t *xscale = armv4_5->arch_info; @@ -684,13 +627,11 @@ int xscale_send_u32(target_t *target, uint32_t value) return xscale_write_rx(target); } -int xscale_write_dcsr(target_t *target, int hold_rst, int ext_dbg_brk) +static int xscale_write_dcsr(target_t *target, int hold_rst, int ext_dbg_brk) { armv4_5_common_t *armv4_5 = target->arch_info; xscale_common_t *xscale = armv4_5->arch_info; - int retval; - scan_field_t fields[3]; uint8_t field0 = 0x0; uint8_t field0_check_value = 0x2; @@ -706,24 +647,24 @@ int xscale_write_dcsr(target_t *target, int hold_rst, int ext_dbg_brk) xscale->external_debug_break = ext_dbg_brk; jtag_set_end_state(TAP_IDLE); - xscale_jtag_set_instr(xscale->jtag_info.tap, xscale->jtag_info.dcsr); + xscale_jtag_set_instr(target->tap, XSCALE_SELDCSR); buf_set_u32(&field0, 1, 1, xscale->hold_rst); buf_set_u32(&field0, 2, 1, xscale->external_debug_break); - fields[0].tap = xscale->jtag_info.tap; + memset(&fields, 0, sizeof fields); + + fields[0].tap = target->tap; fields[0].num_bits = 3; fields[0].out_value = &field0; uint8_t tmp; fields[0].in_value = &tmp; - fields[1].tap = xscale->jtag_info.tap; + fields[1].tap = target->tap; fields[1].num_bits = 32; fields[1].out_value = xscale->reg_cache->reg_list[XSCALE_DCSR].value; - fields[1].in_value = NULL; - - fields[2].tap = xscale->jtag_info.tap; + fields[2].tap = target->tap; fields[2].num_bits = 1; fields[2].out_value = &field2; uint8_t tmp2; @@ -747,65 +688,52 @@ int xscale_write_dcsr(target_t *target, int hold_rst, int ext_dbg_brk) } /* parity of the number of bits 0 if even; 1 if odd. for 32 bit words */ -unsigned int parity (unsigned int v) +static unsigned int parity (unsigned int v) { - unsigned int ov = v; + // unsigned int ov = v; v ^= v >> 16; v ^= v >> 8; v ^= v >> 4; v &= 0xf; - LOG_DEBUG("parity of 0x%x is %i", ov, (0x6996 >> v) & 1); + // LOG_DEBUG("parity of 0x%x is %i", ov, (0x6996 >> v) & 1); return (0x6996 >> v) & 1; } -int xscale_load_ic(target_t *target, int mini, uint32_t va, uint32_t buffer[8]) +static int xscale_load_ic(target_t *target, uint32_t va, uint32_t buffer[8]) { - armv4_5_common_t *armv4_5 = target->arch_info; - xscale_common_t *xscale = armv4_5->arch_info; uint8_t packet[4]; uint8_t cmd; int word; - scan_field_t fields[2]; LOG_DEBUG("loading miniIC at 0x%8.8" PRIx32 "", va); + /* LDIC into IR */ jtag_set_end_state(TAP_IDLE); - xscale_jtag_set_instr(xscale->jtag_info.tap, xscale->jtag_info.ldic); /* LDIC */ - - /* CMD is b010 for Main IC and b011 for Mini IC */ - if (mini) - buf_set_u32(&cmd, 0, 3, 0x3); - else - buf_set_u32(&cmd, 0, 3, 0x2); + xscale_jtag_set_instr(target->tap, XSCALE_LDIC); - buf_set_u32(&cmd, 3, 3, 0x0); + /* CMD is b011 to load a cacheline into the Mini ICache. + * Loading into the main ICache is deprecated, and unused. + * It's followed by three zero bits, and 27 address bits. + */ + buf_set_u32(&cmd, 0, 6, 0x3); /* virtual address of desired cache line */ buf_set_u32(packet, 0, 27, va >> 5); - fields[0].tap = xscale->jtag_info.tap; + memset(&fields, 0, sizeof fields); + + fields[0].tap = target->tap; fields[0].num_bits = 6; fields[0].out_value = &cmd; - fields[0].in_value = NULL; - - - - - - fields[1].tap = xscale->jtag_info.tap; + fields[1].tap = target->tap; fields[1].num_bits = 27; fields[1].out_value = packet; - fields[1].in_value = NULL; - - - - - jtag_add_dr_scan(2, fields, jtag_get_end_state()); + /* rest of packet is a cacheline: 8 instructions, with parity */ fields[0].num_bits = 32; fields[0].out_value = packet; @@ -823,22 +751,17 @@ int xscale_load_ic(target_t *target, int mini, uint32_t va, uint32_t buffer[8]) jtag_add_dr_scan(2, fields, jtag_get_end_state()); } - jtag_execute_queue(); - - return ERROR_OK; + return jtag_execute_queue(); } -int xscale_invalidate_ic_line(target_t *target, uint32_t va) +static int xscale_invalidate_ic_line(target_t *target, uint32_t va) { - armv4_5_common_t *armv4_5 = target->arch_info; - xscale_common_t *xscale = armv4_5->arch_info; uint8_t packet[4]; uint8_t cmd; - scan_field_t fields[2]; jtag_set_end_state(TAP_IDLE); - xscale_jtag_set_instr(xscale->jtag_info.tap, xscale->jtag_info.ldic); /* LDIC */ + xscale_jtag_set_instr(target->tap, XSCALE_LDIC); /* CMD for invalidate IC line b000, bits [6:4] b000 */ buf_set_u32(&cmd, 0, 6, 0x0); @@ -846,32 +769,22 @@ int xscale_invalidate_ic_line(target_t *target, uint32_t va) /* virtual address of desired cache line */ buf_set_u32(packet, 0, 27, va >> 5); - fields[0].tap = xscale->jtag_info.tap; + memset(&fields, 0, sizeof fields); + + fields[0].tap = target->tap; fields[0].num_bits = 6; fields[0].out_value = &cmd; - fields[0].in_value = NULL; - - - - - - fields[1].tap = xscale->jtag_info.tap; + fields[1].tap = target->tap; fields[1].num_bits = 27; fields[1].out_value = packet; - fields[1].in_value = NULL; - - - - - jtag_add_dr_scan(2, fields, jtag_get_end_state()); return ERROR_OK; } -int xscale_update_vectors(target_t *target) +static int xscale_update_vectors(target_t *target) { armv4_5_common_t *armv4_5 = target->arch_info; xscale_common_t *xscale = armv4_5->arch_info; @@ -930,23 +843,23 @@ int xscale_update_vectors(target_t *target) xscale_invalidate_ic_line(target, 0x0); xscale_invalidate_ic_line(target, 0xffff0000); - xscale_load_ic(target, 1, 0x0, xscale->low_vectors); - xscale_load_ic(target, 1, 0xffff0000, xscale->high_vectors); + xscale_load_ic(target, 0x0, xscale->low_vectors); + xscale_load_ic(target, 0xffff0000, xscale->high_vectors); return ERROR_OK; } -int xscale_arch_state(struct target_s *target) +static int xscale_arch_state(struct target_s *target) { armv4_5_common_t *armv4_5 = target->arch_info; xscale_common_t *xscale = armv4_5->arch_info; - char *state[] = + static const char *state[] = { "disabled", "enabled" }; - char *arch_dbg_reason[] = + static const char *arch_dbg_reason[] = { "", "\n(processor reset)", "\n(trace buffer full)" }; @@ -974,11 +887,9 @@ int xscale_arch_state(struct target_s *target) return ERROR_OK; } -int xscale_poll(target_t *target) +static int xscale_poll(target_t *target) { int retval = ERROR_OK; - armv4_5_common_t *armv4_5 = target->arch_info; - xscale_common_t *xscale = armv4_5->arch_info; if ((target->state == TARGET_RUNNING) || (target->state == TARGET_DEBUG_RUNNING)) { @@ -987,8 +898,6 @@ int xscale_poll(target_t *target) { /* there's data to read from the tx register, we entered debug state */ - xscale->handler_running = 1; - target->state = TARGET_HALTED; /* process debug entry, fetching current mode regs */ @@ -1018,7 +927,7 @@ int xscale_poll(target_t *target) return retval; } -int xscale_debug_entry(target_t *target) +static int xscale_debug_entry(target_t *target) { armv4_5_common_t *armv4_5 = target->arch_info; xscale_common_t *xscale = armv4_5->arch_info; @@ -1040,8 +949,8 @@ int xscale_debug_entry(target_t *target) /* move r0 from buffer to register cache */ buf_set_u32(armv4_5->core_cache->reg_list[0].value, 0, 32, buffer[0]); - armv4_5->core_cache->reg_list[15].dirty = 1; - armv4_5->core_cache->reg_list[15].valid = 1; + armv4_5->core_cache->reg_list[0].dirty = 1; + armv4_5->core_cache->reg_list[0].valid = 1; LOG_DEBUG("r0: 0x%8.8" PRIx32 "", buffer[0]); /* move pc from buffer to register cache */ @@ -1148,7 +1057,7 @@ int xscale_debug_entry(target_t *target) xscale->arch_debug_reason = XSCALE_DBG_REASON_TB_FULL; pc -= 4; break; - case 0x7: /* Reserved */ + case 0x7: /* Reserved (may flag Hot-Debug support) */ default: LOG_ERROR("Method of Entry is 'Reserved'"); exit(-1); @@ -1199,7 +1108,7 @@ int xscale_debug_entry(target_t *target) return ERROR_OK; } -int xscale_halt(target_t *target) +static int xscale_halt(target_t *target) { armv4_5_common_t *armv4_5 = target->arch_info; xscale_common_t *xscale = armv4_5->arch_info; @@ -1234,7 +1143,7 @@ int xscale_halt(target_t *target) return ERROR_OK; } -int xscale_enable_single_step(struct target_s *target, uint32_t next_pc) +static int xscale_enable_single_step(struct target_s *target, uint32_t next_pc) { armv4_5_common_t *armv4_5 = target->arch_info; xscale_common_t *xscale= armv4_5->arch_info; @@ -1262,7 +1171,7 @@ int xscale_enable_single_step(struct target_s *target, uint32_t next_pc) return ERROR_OK; } -int xscale_disable_single_step(struct target_s *target) +static int xscale_disable_single_step(struct target_s *target) { armv4_5_common_t *armv4_5 = target->arch_info; xscale_common_t *xscale= armv4_5->arch_info; @@ -1275,7 +1184,33 @@ int xscale_disable_single_step(struct target_s *target) return ERROR_OK; } -int xscale_resume(struct target_s *target, int current, uint32_t address, int handle_breakpoints, int debug_execution) +static void xscale_enable_watchpoints(struct target_s *target) +{ + watchpoint_t *watchpoint = target->watchpoints; + + while (watchpoint) + { + if (watchpoint->set == 0) + xscale_set_watchpoint(target, watchpoint); + watchpoint = watchpoint->next; + } +} + +static void xscale_enable_breakpoints(struct target_s *target) +{ + breakpoint_t *breakpoint = target->breakpoints; + + /* set any pending breakpoints */ + while (breakpoint) + { + if (breakpoint->set == 0) + xscale_set_breakpoint(target, breakpoint); + breakpoint = breakpoint->next; + } +} + +static int xscale_resume(struct target_s *target, int current, + uint32_t address, int handle_breakpoints, int debug_execution) { armv4_5_common_t *armv4_5 = target->arch_info; xscale_common_t *xscale= armv4_5->arch_info; @@ -1426,12 +1361,11 @@ int xscale_resume(struct target_s *target, int current, uint32_t address, int ha LOG_DEBUG("target resumed"); - xscale->handler_running = 1; - return ERROR_OK; } -static int xscale_step_inner(struct target_s *target, int current, uint32_t address, int handle_breakpoints) +static int xscale_step_inner(struct target_s *target, int current, + uint32_t address, int handle_breakpoints) { armv4_5_common_t *armv4_5 = target->arch_info; xscale_common_t *xscale = armv4_5->arch_info; @@ -1511,7 +1445,8 @@ static int xscale_step_inner(struct target_s *target, int current, uint32_t addr return ERROR_OK; } -int xscale_step(struct target_s *target, int current, uint32_t address, int handle_breakpoints) +static int xscale_step(struct target_s *target, int current, + uint32_t address, int handle_breakpoints) { armv4_5_common_t *armv4_5 = target->arch_info; breakpoint_t *breakpoint = target->breakpoints; @@ -1565,7 +1500,7 @@ int xscale_step(struct target_s *target, int current, uint32_t address, int hand } -int xscale_assert_reset(target_t *target) +static int xscale_assert_reset(target_t *target) { armv4_5_common_t *armv4_5 = target->arch_info; xscale_common_t *xscale = armv4_5->arch_info; @@ -1577,7 +1512,7 @@ int xscale_assert_reset(target_t *target) * end up in T-L-R, which would reset JTAG */ jtag_set_end_state(TAP_IDLE); - xscale_jtag_set_instr(xscale->jtag_info.tap, xscale->jtag_info.dcsr); + xscale_jtag_set_instr(target->tap, XSCALE_SELDCSR); /* set Hold reset, Halt mode and Trap Reset */ buf_set_u32(xscale->reg_cache->reg_list[XSCALE_DCSR].value, 30, 1, 0x1); @@ -1585,7 +1520,7 @@ int xscale_assert_reset(target_t *target) xscale_write_dcsr(target, 1, 0); /* select BYPASS, because having DCSR selected caused problems on the PXA27x */ - xscale_jtag_set_instr(xscale->jtag_info.tap, 0x7f); + xscale_jtag_set_instr(target->tap, 0x7f); jtag_execute_queue(); /* assert reset */ @@ -1607,19 +1542,10 @@ int xscale_assert_reset(target_t *target) return ERROR_OK; } -int xscale_deassert_reset(target_t *target) +static int xscale_deassert_reset(target_t *target) { armv4_5_common_t *armv4_5 = target->arch_info; xscale_common_t *xscale = armv4_5->arch_info; - - fileio_t debug_handler; - uint32_t address; - uint32_t binary_size; - - uint32_t buf_cnt; - uint32_t i; - int retval; - breakpoint_t *breakpoint = target->breakpoints; LOG_DEBUG("-"); @@ -1642,8 +1568,23 @@ int xscale_deassert_reset(target_t *target) breakpoint = breakpoint->next; } - if (!xscale->handler_installed) + armv4_5_invalidate_core_regs(target); + + /* FIXME mark hardware watchpoints got unset too. Also, + * at least some of the XScale registers are invalid... + */ + + /* + * REVISIT: *assumes* we had a SRST+TRST reset so the mini-icache + * contents got invalidated. Safer to force that, so writing new + * contents can't ever fail.. + */ { + uint32_t address; + unsigned buf_cnt; + const uint8_t *buffer = xscale_debug_handler; + int retval; + /* release SRST */ jtag_add_reset(0, 0); @@ -1658,36 +1599,22 @@ int xscale_deassert_reset(target_t *target) buf_set_u32(xscale->reg_cache->reg_list[XSCALE_DCSR].value, 16, 1, 0x1); xscale_write_dcsr(target, 1, 0); - /* Load debug handler */ - if (fileio_open(&debug_handler, "xscale/debug_handler.bin", FILEIO_READ, FILEIO_BINARY) != ERROR_OK) - { - return ERROR_OK; - } - - if ((binary_size = debug_handler.size) % 4) - { - LOG_ERROR("debug_handler.bin: size not a multiple of 4"); - exit(-1); - } - - if (binary_size > 0x800) - { - LOG_ERROR("debug_handler.bin: larger than 2kb"); - exit(-1); - } - - binary_size = CEIL(binary_size, 32) * 32; - + /* Load the debug handler into the mini-icache. Since + * it's using halt mode (not monitor mode), it runs in + * "Special Debug State" for access to registers, memory, + * coprocessors, trace data, etc. + */ address = xscale->handler_address; - while (binary_size > 0) + for (unsigned binary_size = sizeof xscale_debug_handler - 1; + binary_size > 0; + binary_size -= buf_cnt, buffer += buf_cnt) { uint32_t cache_line[8]; - uint8_t buffer[32]; - - if ((retval = fileio_read(&debug_handler, 32, buffer, &buf_cnt)) != ERROR_OK) - { + unsigned i; - } + buf_cnt = binary_size; + if (buf_cnt > 32) + buf_cnt = 32; for (i = 0; i < buf_cnt; i += 4) { @@ -1695,23 +1622,31 @@ int xscale_deassert_reset(target_t *target) cache_line[i / 4] = le_to_h_u32(&buffer[i]); } - for (; buf_cnt < 32; buf_cnt += 4) + for (; i < 32; i += 4) { - cache_line[buf_cnt / 4] = 0xe1a08008; + cache_line[i / 4] = 0xe1a08008; } /* only load addresses other than the reset vectors */ if ((address % 0x400) != 0x0) { - xscale_load_ic(target, 1, address, cache_line); + retval = xscale_load_ic(target, address, + cache_line); + if (retval != ERROR_OK) + return retval; } address += buf_cnt; - binary_size -= buf_cnt; }; - xscale_load_ic(target, 1, 0x0, xscale->low_vectors); - xscale_load_ic(target, 1, 0xffff0000, xscale->high_vectors); + retval = xscale_load_ic(target, 0x0, + xscale->low_vectors); + if (retval != ERROR_OK) + return retval; + retval = xscale_load_ic(target, 0xffff0000, + xscale->high_vectors); + if (retval != ERROR_OK) + return retval; jtag_add_runtest(30, jtag_set_end_state(TAP_IDLE)); @@ -1737,34 +1672,26 @@ int xscale_deassert_reset(target_t *target) /* resume the target */ xscale_resume(target, 1, 0x0, 1, 0); } - - fileio_close(&debug_handler); - } - else - { - jtag_add_reset(0, 0); } return ERROR_OK; } -int xscale_soft_reset_halt(struct target_s *target) -{ - return ERROR_OK; -} - -int xscale_read_core_reg(struct target_s *target, int num, enum armv4_5_mode mode) +static int xscale_read_core_reg(struct target_s *target, int num, + enum armv4_5_mode mode) { + LOG_ERROR("not implemented"); return ERROR_OK; } -int xscale_write_core_reg(struct target_s *target, int num, enum armv4_5_mode mode, uint32_t value) +static int xscale_write_core_reg(struct target_s *target, int num, + enum armv4_5_mode mode, uint32_t value) { - + LOG_ERROR("not implemented"); return ERROR_OK; } -int xscale_full_context(target_t *target) +static int xscale_full_context(target_t *target) { armv4_5_common_t *armv4_5 = target->arch_info; @@ -1840,14 +1767,12 @@ int xscale_full_context(target_t *target) return ERROR_OK; } -int xscale_restore_context(target_t *target) +static int xscale_restore_context(target_t *target) { armv4_5_common_t *armv4_5 = target->arch_info; int i, j; - LOG_DEBUG("-"); - if (target->state != TARGET_HALTED) { LOG_WARNING("target not halted"); @@ -1909,7 +1834,8 @@ int xscale_restore_context(target_t *target) return ERROR_OK; } -int xscale_read_memory(struct target_s *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer) +static int xscale_read_memory(struct target_s *target, uint32_t address, + uint32_t size, uint32_t count, uint8_t *buffer) { armv4_5_common_t *armv4_5 = target->arch_info; xscale_common_t *xscale = armv4_5->arch_info; @@ -1988,7 +1914,8 @@ int xscale_read_memory(struct target_s *target, uint32_t address, uint32_t size, return ERROR_OK; } -int xscale_write_memory(struct target_s *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer) +static int xscale_write_memory(struct target_s *target, uint32_t address, + uint32_t size, uint32_t count, uint8_t *buffer) { armv4_5_common_t *armv4_5 = target->arch_info; xscale_common_t *xscale = armv4_5->arch_info; @@ -2066,12 +1993,13 @@ int xscale_write_memory(struct target_s *target, uint32_t address, uint32_t size return ERROR_OK; } -int xscale_bulk_write_memory(target_t *target, uint32_t address, uint32_t count, uint8_t *buffer) +static int xscale_bulk_write_memory(target_t *target, uint32_t address, + uint32_t count, uint8_t *buffer) { return xscale_write_memory(target, address, 4, count, buffer); } -uint32_t xscale_get_ttb(target_t *target) +static uint32_t xscale_get_ttb(target_t *target) { armv4_5_common_t *armv4_5 = target->arch_info; xscale_common_t *xscale = armv4_5->arch_info; @@ -2083,7 +2011,8 @@ uint32_t xscale_get_ttb(target_t *target) return ttb; } -void xscale_disable_mmu_caches(target_t *target, int mmu, int d_u_cache, int i_cache) +static void xscale_disable_mmu_caches(target_t *target, int mmu, + int d_u_cache, int i_cache) { armv4_5_common_t *armv4_5 = target->arch_info; xscale_common_t *xscale = armv4_5->arch_info; @@ -2122,7 +2051,8 @@ void xscale_disable_mmu_caches(target_t *target, int mmu, int d_u_cache, int i_c xscale_send_u32(target, 0x53); } -void xscale_enable_mmu_caches(target_t *target, int mmu, int d_u_cache, int i_cache) +static void xscale_enable_mmu_caches(target_t *target, int mmu, + int d_u_cache, int i_cache) { armv4_5_common_t *armv4_5 = target->arch_info; xscale_common_t *xscale = armv4_5->arch_info; @@ -2148,7 +2078,8 @@ void xscale_enable_mmu_caches(target_t *target, int mmu, int d_u_cache, int i_ca xscale_send_u32(target, 0x53); } -int xscale_set_breakpoint(struct target_s *target, breakpoint_t *breakpoint) +static int xscale_set_breakpoint(struct target_s *target, + breakpoint_t *breakpoint) { int retval; armv4_5_common_t *armv4_5 = target->arch_info; @@ -2221,7 +2152,8 @@ int xscale_set_breakpoint(struct target_s *target, breakpoint_t *breakpoint) return ERROR_OK; } -int xscale_add_breakpoint(struct target_s *target, breakpoint_t *breakpoint) +static int xscale_add_breakpoint(struct target_s *target, + breakpoint_t *breakpoint) { armv4_5_common_t *armv4_5 = target->arch_info; xscale_common_t *xscale = armv4_5->arch_info; @@ -2252,7 +2184,8 @@ int xscale_add_breakpoint(struct target_s *target, breakpoint_t *breakpoint) return ERROR_OK; } -int xscale_unset_breakpoint(struct target_s *target, breakpoint_t *breakpoint) +static int xscale_unset_breakpoint(struct target_s *target, + breakpoint_t *breakpoint) { int retval; armv4_5_common_t *armv4_5 = target->arch_info; @@ -2307,7 +2240,7 @@ int xscale_unset_breakpoint(struct target_s *target, breakpoint_t *breakpoint) return ERROR_OK; } -int xscale_remove_breakpoint(struct target_s *target, breakpoint_t *breakpoint) +static int xscale_remove_breakpoint(struct target_s *target, breakpoint_t *breakpoint) { armv4_5_common_t *armv4_5 = target->arch_info; xscale_common_t *xscale = armv4_5->arch_info; @@ -2329,7 +2262,8 @@ int xscale_remove_breakpoint(struct target_s *target, breakpoint_t *breakpoint) return ERROR_OK; } -int xscale_set_watchpoint(struct target_s *target, watchpoint_t *watchpoint) +static int xscale_set_watchpoint(struct target_s *target, + watchpoint_t *watchpoint) { armv4_5_common_t *armv4_5 = target->arch_info; xscale_common_t *xscale = armv4_5->arch_info; @@ -2385,7 +2319,8 @@ int xscale_set_watchpoint(struct target_s *target, watchpoint_t *watchpoint) return ERROR_OK; } -int xscale_add_watchpoint(struct target_s *target, watchpoint_t *watchpoint) +static int xscale_add_watchpoint(struct target_s *target, + watchpoint_t *watchpoint) { armv4_5_common_t *armv4_5 = target->arch_info; xscale_common_t *xscale = armv4_5->arch_info; @@ -2411,7 +2346,8 @@ int xscale_add_watchpoint(struct target_s *target, watchpoint_t *watchpoint) return ERROR_OK; } -int xscale_unset_watchpoint(struct target_s *target, watchpoint_t *watchpoint) +static int xscale_unset_watchpoint(struct target_s *target, + watchpoint_t *watchpoint) { armv4_5_common_t *armv4_5 = target->arch_info; xscale_common_t *xscale = armv4_5->arch_info; @@ -2447,7 +2383,7 @@ int xscale_unset_watchpoint(struct target_s *target, watchpoint_t *watchpoint) return ERROR_OK; } -int xscale_remove_watchpoint(struct target_s *target, watchpoint_t *watchpoint) +static int xscale_remove_watchpoint(struct target_s *target, watchpoint_t *watchpoint) { armv4_5_common_t *armv4_5 = target->arch_info; xscale_common_t *xscale = armv4_5->arch_info; @@ -2468,32 +2404,7 @@ int xscale_remove_watchpoint(struct target_s *target, watchpoint_t *watchpoint) return ERROR_OK; } -void xscale_enable_watchpoints(struct target_s *target) -{ - watchpoint_t *watchpoint = target->watchpoints; - - while (watchpoint) - { - if (watchpoint->set == 0) - xscale_set_watchpoint(target, watchpoint); - watchpoint = watchpoint->next; - } -} - -void xscale_enable_breakpoints(struct target_s *target) -{ - breakpoint_t *breakpoint = target->breakpoints; - - /* set any pending breakpoints */ - while (breakpoint) - { - if (breakpoint->set == 0) - xscale_set_breakpoint(target, breakpoint); - breakpoint = breakpoint->next; - } -} - -int xscale_get_reg(reg_t *reg) +static int xscale_get_reg(reg_t *reg) { xscale_reg_t *arch_info = reg->arch_info; target_t *target = arch_info->target; @@ -2539,7 +2450,7 @@ int xscale_get_reg(reg_t *reg) return ERROR_OK; } -int xscale_set_reg(reg_t *reg, uint8_t* buf) +static int xscale_set_reg(reg_t *reg, uint8_t* buf) { xscale_reg_t *arch_info = reg->arch_info; target_t *target = arch_info->target; @@ -2584,17 +2495,7 @@ int xscale_set_reg(reg_t *reg, uint8_t* buf) return ERROR_OK; } -/* convenience wrapper to access XScale specific registers */ -int xscale_set_reg_u32(reg_t *reg, uint32_t value) -{ - uint8_t buf[4]; - - buf_set_u32(buf, 0, 32, value); - - return xscale_set_reg(reg, buf); -} - -int xscale_write_dcsr_sw(target_t *target, uint32_t value) +static int xscale_write_dcsr_sw(target_t *target, uint32_t value) { /* get pointers to arch-specific information */ armv4_5_common_t *armv4_5 = target->arch_info; @@ -2615,7 +2516,7 @@ int xscale_write_dcsr_sw(target_t *target, uint32_t value) return ERROR_OK; } -int xscale_read_trace(target_t *target) +static int xscale_read_trace(target_t *target) { /* get pointers to arch-specific information */ armv4_5_common_t *armv4_5 = target->arch_info; @@ -2694,7 +2595,8 @@ int xscale_read_trace(target_t *target) return ERROR_OK; } -int xscale_read_instruction(target_t *target, arm_instruction_t *instruction) +static int xscale_read_instruction(target_t *target, + arm_instruction_t *instruction) { /* get pointers to arch-specific information */ armv4_5_common_t *armv4_5 = target->arch_info; @@ -2760,7 +2662,8 @@ int xscale_read_instruction(target_t *target, arm_instruction_t *instruction) return ERROR_OK; } -int xscale_branch_address(xscale_trace_data_t *trace_data, int i, uint32_t *target) +static int xscale_branch_address(xscale_trace_data_t *trace_data, + int i, uint32_t *target) { /* if there are less than four entries prior to the indirect branch message * we can't extract the address */ @@ -2775,7 +2678,7 @@ int xscale_branch_address(xscale_trace_data_t *trace_data, int i, uint32_t *targ return 0; } -int xscale_analyze_trace(target_t *target, command_context_t *cmd_ctx) +static int xscale_analyze_trace(target_t *target, command_context_t *cmd_ctx) { /* get pointers to arch-specific information */ armv4_5_common_t *armv4_5 = target->arch_info; @@ -2964,7 +2867,7 @@ int xscale_analyze_trace(target_t *target, command_context_t *cmd_ctx) return ERROR_OK; } -void xscale_build_reg_cache(target_t *target) +static void xscale_build_reg_cache(target_t *target) { /* get pointers to arch-specific information */ armv4_5_common_t *armv4_5 = target->arch_info; @@ -3009,17 +2912,15 @@ void xscale_build_reg_cache(target_t *target) xscale->reg_cache = (*cache_p); } -int xscale_init_target(struct command_context_s *cmd_ctx, struct target_s *target) -{ - return ERROR_OK; -} - -int xscale_quit(void) +static int xscale_init_target(struct command_context_s *cmd_ctx, + struct target_s *target) { + xscale_build_reg_cache(target); return ERROR_OK; } -int xscale_init_arch_info(target_t *target, xscale_common_t *xscale, jtag_tap_t *tap, const char *variant) +static int xscale_init_arch_info(target_t *target, + xscale_common_t *xscale, jtag_tap_t *tap, const char *variant) { armv4_5_common_t *armv4_5; uint32_t high_reset_branch, low_reset_branch; @@ -3031,34 +2932,31 @@ int xscale_init_arch_info(target_t *target, xscale_common_t *xscale, jtag_tap_t xscale->arch_info = NULL; xscale->common_magic = XSCALE_COMMON_MAGIC; - /* remember the variant (PXA25x, PXA27x, IXP42x, ...) */ - xscale->variant = strdup(variant); - - /* prepare JTAG information for the new target */ - xscale->jtag_info.tap = tap; - - xscale->jtag_info.dbgrx = 0x02; - xscale->jtag_info.dbgtx = 0x10; - xscale->jtag_info.dcsr = 0x09; - xscale->jtag_info.ldic = 0x07; + /* we don't really *need* variant info ... */ + if (variant) { + int ir_length = 0; + + if (strcmp(variant, "pxa250") == 0 + || strcmp(variant, "pxa255") == 0 + || strcmp(variant, "pxa26x") == 0) + ir_length = 5; + else if (strcmp(variant, "pxa27x") == 0 + || strcmp(variant, "ixp42x") == 0 + || strcmp(variant, "ixp45x") == 0 + || strcmp(variant, "ixp46x") == 0) + ir_length = 7; + else + LOG_WARNING("%s: unrecognized variant %s", + tap->dotted_name, variant); - if ((strcmp(xscale->variant, "pxa250") == 0) || - (strcmp(xscale->variant, "pxa255") == 0) || - (strcmp(xscale->variant, "pxa26x") == 0)) - { - xscale->jtag_info.ir_length = 5; - } - else if ((strcmp(xscale->variant, "pxa27x") == 0) || - (strcmp(xscale->variant, "ixp42x") == 0) || - (strcmp(xscale->variant, "ixp45x") == 0) || - (strcmp(xscale->variant, "ixp46x") == 0)) - { - xscale->jtag_info.ir_length = 7; + if (ir_length && ir_length != tap->ir_length) { + LOG_WARNING("%s: IR length for %s is %d; fixing", + tap->dotted_name, variant, ir_length); + tap->ir_length = ir_length; + } } /* the debug handler isn't installed (and thus not running) at this time */ - xscale->handler_installed = 0; - xscale->handler_running = 0; xscale->handler_address = 0xfe000800; /* clear the vectors we keep locally for reference */ @@ -3127,18 +3025,26 @@ int xscale_init_arch_info(target_t *target, xscale_common_t *xscale, jtag_tap_t return ERROR_OK; } -/* target xscale */ -int xscale_target_create(struct target_s *target, Jim_Interp *interp) +static int xscale_target_create(struct target_s *target, Jim_Interp *interp) { - xscale_common_t *xscale = calloc(1,sizeof(xscale_common_t)); + xscale_common_t *xscale; - xscale_init_arch_info(target, xscale, target->tap, target->variant); - xscale_build_reg_cache(target); + if (sizeof xscale_debug_handler - 1 > 0x800) { + LOG_ERROR("debug_handler.bin: larger than 2kb"); + return ERROR_FAIL; + } - return ERROR_OK; + xscale = calloc(1, sizeof(*xscale)); + if (!xscale) + return ERROR_FAIL; + + return xscale_init_arch_info(target, xscale, target->tap, + target->variant); } -int xscale_handle_debug_handler_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc) +static int +xscale_handle_debug_handler_command(struct command_context_s *cmd_ctx, + char *cmd, char **args, int argc) { target_t *target = NULL; armv4_5_common_t *armv4_5; @@ -3163,7 +3069,7 @@ int xscale_handle_debug_handler_command(struct command_context_s *cmd_ctx, char return ERROR_FAIL; } - handler_address = strtoul(args[1], NULL, 0); + COMMAND_PARSE_NUMBER(u32, args[1], handler_address); if (((handler_address >= 0x800) && (handler_address <= 0x1fef800)) || ((handler_address >= 0xfe000800) && (handler_address <= 0xfffff800))) @@ -3179,7 +3085,9 @@ int xscale_handle_debug_handler_command(struct command_context_s *cmd_ctx, char return ERROR_OK; } -int xscale_handle_cache_clean_address_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc) +static int +xscale_handle_cache_clean_address_command(struct command_context_s *cmd_ctx, + char *cmd, char **args, int argc) { target_t *target = NULL; armv4_5_common_t *armv4_5; @@ -3204,7 +3112,7 @@ int xscale_handle_cache_clean_address_command(struct command_context_s *cmd_ctx, return ERROR_FAIL; } - cache_clean_address = strtoul(args[1], NULL, 0); + COMMAND_PARSE_NUMBER(u32, args[1], cache_clean_address); if (cache_clean_address & 0xffff) { @@ -3218,7 +3126,9 @@ int xscale_handle_cache_clean_address_command(struct command_context_s *cmd_ctx, return ERROR_OK; } -int xscale_handle_cache_info_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc) +static int +xscale_handle_cache_info_command(struct command_context_s *cmd_ctx, + char *cmd, char **args, int argc) { target_t *target = get_current_target(cmd_ctx); armv4_5_common_t *armv4_5; @@ -3232,7 +3142,8 @@ int xscale_handle_cache_info_command(struct command_context_s *cmd_ctx, char *cm return armv4_5_handle_cache_info_command(cmd_ctx, &xscale->armv4_5_mmu.armv4_5_cache); } -static int xscale_virt2phys(struct target_s *target, uint32_t virtual, uint32_t *physical) +static int xscale_virt2phys(struct target_s *target, + uint32_t virtual, uint32_t *physical) { armv4_5_common_t *armv4_5; xscale_common_t *xscale; @@ -3269,7 +3180,8 @@ static int xscale_mmu(struct target_s *target, int *enabled) return ERROR_OK; } -int xscale_handle_mmu_command(command_context_t *cmd_ctx, char *cmd, char **args, int argc) +static int xscale_handle_mmu_command(command_context_t *cmd_ctx, + char *cmd, char **args, int argc) { target_t *target = get_current_target(cmd_ctx); armv4_5_common_t *armv4_5; @@ -3305,7 +3217,8 @@ int xscale_handle_mmu_command(command_context_t *cmd_ctx, char *cmd, char **args return ERROR_OK; } -int xscale_handle_idcache_command(command_context_t *cmd_ctx, char *cmd, char **args, int argc) +static int xscale_handle_idcache_command(command_context_t *cmd_ctx, + char *cmd, char **args, int argc) { target_t *target = get_current_target(cmd_ctx); armv4_5_common_t *armv4_5; @@ -3359,7 +3272,8 @@ int xscale_handle_idcache_command(command_context_t *cmd_ctx, char *cmd, char ** return ERROR_OK; } -int xscale_handle_vector_catch_command(command_context_t *cmd_ctx, char *cmd, char **args, int argc) +static int xscale_handle_vector_catch_command(command_context_t *cmd_ctx, + char *cmd, char **args, int argc) { target_t *target = get_current_target(cmd_ctx); armv4_5_common_t *armv4_5; @@ -3376,7 +3290,7 @@ int xscale_handle_vector_catch_command(command_context_t *cmd_ctx, char *cmd, ch } else { - xscale->vector_catch = strtoul(args[0], NULL, 0); + COMMAND_PARSE_NUMBER(u32, args[0], xscale->vector_catch); buf_set_u32(xscale->reg_cache->reg_list[XSCALE_DCSR].value, 16, 8, xscale->vector_catch); xscale_write_dcsr(target, -1, -1); } @@ -3387,7 +3301,8 @@ int xscale_handle_vector_catch_command(command_context_t *cmd_ctx, char *cmd, ch } -int xscale_handle_vector_table_command(command_context_t *cmd_ctx, char *cmd, char **args, int argc) +static int xscale_handle_vector_table_command(command_context_t *cmd_ctx, + char *cmd, char **args, int argc) { target_t *target = get_current_target(cmd_ctx); armv4_5_common_t *armv4_5; @@ -3418,9 +3333,9 @@ int xscale_handle_vector_table_command(command_context_t *cmd_ctx, char *cmd, ch else { int idx; + COMMAND_PARSE_NUMBER(int, args[1], idx); uint32_t vec; - idx = strtoul(args[1], NULL, 0); - vec = strtoul(args[2], NULL, 0); + COMMAND_PARSE_NUMBER(u32, args[2], vec); if (idx < 1 || idx >= 8) err = 1; @@ -3446,7 +3361,9 @@ int xscale_handle_vector_table_command(command_context_t *cmd_ctx, char *cmd, ch } -int xscale_handle_trace_buffer_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc) +static int +xscale_handle_trace_buffer_command(struct command_context_s *cmd_ctx, + char *cmd, char **args, int argc) { target_t *target = get_current_target(cmd_ctx); armv4_5_common_t *armv4_5; @@ -3489,10 +3406,10 @@ int xscale_handle_trace_buffer_command(struct command_context_s *cmd_ctx, char * if ((argc >= 2) && (strcmp("fill", args[1]) == 0)) { + uint32_t fill = 1; if (argc >= 3) - xscale->trace.buffer_fill = strtoul(args[2], NULL, 0); - else - xscale->trace.buffer_fill = 1; + COMMAND_PARSE_NUMBER(u32, args[2], fill); + xscale->trace.buffer_fill = fill; } else if ((argc >= 2) && (strcmp("wrap", args[1]) == 0)) { @@ -3525,7 +3442,9 @@ int xscale_handle_trace_buffer_command(struct command_context_s *cmd_ctx, char * return ERROR_OK; } -int xscale_handle_trace_image_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc) +static int +xscale_handle_trace_image_command(struct command_context_s *cmd_ctx, + char *cmd, char **args, int argc) { target_t *target; armv4_5_common_t *armv4_5; @@ -3559,7 +3478,7 @@ int xscale_handle_trace_image_command(struct command_context_s *cmd_ctx, char *c if (argc >= 2) { xscale->trace.image->base_address_set = 1; - xscale->trace.image->base_address = strtoul(args[1], NULL, 0); + COMMAND_PARSE_NUMBER(u32, args[1], xscale->trace.image->base_address); } else { @@ -3576,7 +3495,8 @@ int xscale_handle_trace_image_command(struct command_context_s *cmd_ctx, char *c return ERROR_OK; } -int xscale_handle_dump_trace_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc) +static int xscale_handle_dump_trace_command(struct command_context_s *cmd_ctx, + char *cmd, char **args, int argc) { target_t *target = get_current_target(cmd_ctx); armv4_5_common_t *armv4_5; @@ -3634,7 +3554,9 @@ int xscale_handle_dump_trace_command(struct command_context_s *cmd_ctx, char *cm return ERROR_OK; } -int xscale_handle_analyze_trace_buffer_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc) +static int +xscale_handle_analyze_trace_buffer_command(struct command_context_s *cmd_ctx, + char *cmd, char **args, int argc) { target_t *target = get_current_target(cmd_ctx); armv4_5_common_t *armv4_5; @@ -3650,7 +3572,8 @@ int xscale_handle_analyze_trace_buffer_command(struct command_context_s *cmd_ctx return ERROR_OK; } -int xscale_handle_cp15(command_context_t *cmd_ctx, char *cmd, char **args, int argc) +static int xscale_handle_cp15(command_context_t *cmd_ctx, + char *cmd, char **args, int argc) { target_t *target = get_current_target(cmd_ctx); armv4_5_common_t *armv4_5; @@ -3670,7 +3593,7 @@ int xscale_handle_cp15(command_context_t *cmd_ctx, char *cmd, char **args, int a reg_t *reg = NULL; if (argc > 0) { - reg_no = strtoul(args[0], NULL, 0); + COMMAND_PARSE_NUMBER(u32, args[0], reg_no); /*translate from xscale cp15 register no to openocd register*/ switch (reg_no) { @@ -3716,8 +3639,8 @@ int xscale_handle_cp15(command_context_t *cmd_ctx, char *cmd, char **args, int a } else if (argc == 2) { - - uint32_t value = strtoul(args[1], NULL, 0); + uint32_t value; + COMMAND_PARSE_NUMBER(u32, args[1], value); /* send CP write request (command 0x41) */ xscale_send_u32(target, 0x41); @@ -3739,7 +3662,7 @@ int xscale_handle_cp15(command_context_t *cmd_ctx, char *cmd, char **args, int a return ERROR_OK; } -int xscale_register_commands(struct command_context_s *cmd_ctx) +static int xscale_register_commands(struct command_context_s *cmd_ctx) { command_t *xscale_cmd; @@ -3769,3 +3692,43 @@ int xscale_register_commands(struct command_context_s *cmd_ctx) return ERROR_OK; } + +target_type_t xscale_target = +{ + .name = "xscale", + + .poll = xscale_poll, + .arch_state = xscale_arch_state, + + .target_request_data = NULL, + + .halt = xscale_halt, + .resume = xscale_resume, + .step = xscale_step, + + .assert_reset = xscale_assert_reset, + .deassert_reset = xscale_deassert_reset, + .soft_reset_halt = NULL, + + .get_gdb_reg_list = armv4_5_get_gdb_reg_list, + + .read_memory = xscale_read_memory, + .write_memory = xscale_write_memory, + .bulk_write_memory = xscale_bulk_write_memory, + .checksum_memory = arm7_9_checksum_memory, + .blank_check_memory = arm7_9_blank_check_memory, + + .run_algorithm = armv4_5_run_algorithm, + + .add_breakpoint = xscale_add_breakpoint, + .remove_breakpoint = xscale_remove_breakpoint, + .add_watchpoint = xscale_add_watchpoint, + .remove_watchpoint = xscale_remove_watchpoint, + + .register_commands = xscale_register_commands, + .target_create = xscale_target_create, + .init_target = xscale_init_target, + + .virt2phys = xscale_virt2phys, + .mmu = xscale_mmu +};