X-Git-Url: https://review.openocd.org/gitweb?p=openocd.git;a=blobdiff_plain;f=src%2Ftarget%2Fxscale.c;h=36d41fd5e8d2bcaf3242a175a36059db08ff99af;hp=4e62c8a16ac006efa25a87277811d4407728d9f8;hb=503bb08f9993c59a4b3206600555a42fd18459b6;hpb=8bc200e1fe1e0997989aa0bf4d9f57cda0b3c9c3 diff --git a/src/target/xscale.c b/src/target/xscale.c index 4e62c8a16a..36d41fd5e8 100644 --- a/src/target/xscale.c +++ b/src/target/xscale.c @@ -2,6 +2,9 @@ * Copyright (C) 2006, 2007 by Dominic Rath * * Dominic.Rath@gmx.de * * * + * Copyright (C) 2007,2008 Øyvind Harboe * + * oyvind.harboe@zylin.com * + * * * This program is free software; you can redistribute it and/or modify * * it under the terms of the GNU General Public License as published by * * the Free Software Foundation; either version 2 of the License, or * @@ -25,6 +28,7 @@ #include "xscale.h" +#include "arm7_9_common.h" #include "register.h" #include "target.h" #include "armv4_5.h" @@ -49,9 +53,9 @@ int xscale_register_commands(struct command_context_s *cmd_ctx); /* forward declarations */ -int xscale_target_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct target_s *target); +int xscale_target_create(struct target_s *target, Jim_Interp *interp); int xscale_init_target(struct command_context_s *cmd_ctx, struct target_s *target); -int xscale_quit(); +int xscale_quit(void); int xscale_arch_state(struct target_s *target); int xscale_poll(target_t *target); @@ -64,7 +68,6 @@ int xscale_restore_context(target_t *target); int xscale_assert_reset(target_t *target); int xscale_deassert_reset(target_t *target); int xscale_soft_reset_halt(struct target_s *target); -int xscale_prepare_reset_halt(struct target_s *target); int xscale_set_reg_u32(reg_t *reg, u32 value); @@ -74,7 +77,6 @@ int xscale_write_core_reg(struct target_s *target, int num, enum armv4_5_mode mo int xscale_read_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer); int xscale_write_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer); int xscale_bulk_write_memory(target_t *target, u32 address, u32 count, u8 *buffer); -int xscale_checksum_memory(struct target_s *target, u32 address, u32 count, u32* checksum); int xscale_add_breakpoint(struct target_s *target, breakpoint_t *breakpoint); int xscale_remove_breakpoint(struct target_s *target, breakpoint_t *breakpoint); @@ -105,14 +107,14 @@ target_type_t xscale_target = .assert_reset = xscale_assert_reset, .deassert_reset = xscale_deassert_reset, .soft_reset_halt = xscale_soft_reset_halt, - .prepare_reset_halt = xscale_prepare_reset_halt, .get_gdb_reg_list = armv4_5_get_gdb_reg_list, .read_memory = xscale_read_memory, .write_memory = xscale_write_memory, .bulk_write_memory = xscale_bulk_write_memory, - .checksum_memory = xscale_checksum_memory, + .checksum_memory = arm7_9_checksum_memory, + .blank_check_memory = arm7_9_blank_check_memory, .run_algorithm = armv4_5_run_algorithm, @@ -122,10 +124,10 @@ target_type_t xscale_target = .remove_watchpoint = xscale_remove_watchpoint, .register_commands = xscale_register_commands, - .target_command = xscale_target_command, + .target_create = xscale_target_create, .init_target = xscale_init_target, .quit = xscale_quit, - + .virt2phys = xscale_virt2phys, .mmu = xscale_mmu }; @@ -194,13 +196,13 @@ int xscale_get_arch_pointers(target_t *target, armv4_5_common_t **armv4_5_p, xsc if (armv4_5->common_magic != ARMV4_5_COMMON_MAGIC) { - ERROR("target isn't an XScale target"); + LOG_ERROR("target isn't an XScale target"); return -1; } if (xscale->common_magic != XSCALE_COMMON_MAGIC) { - ERROR("target isn't an XScale target"); + LOG_ERROR("target isn't an XScale target"); return -1; } @@ -210,21 +212,22 @@ int xscale_get_arch_pointers(target_t *target, armv4_5_common_t **armv4_5_p, xsc return ERROR_OK; } -int xscale_jtag_set_instr(int chain_pos, u32 new_instr) +int xscale_jtag_set_instr(jtag_tap_t *tap, u32 new_instr) { - jtag_device_t *device = jtag_get_device(chain_pos); + if (tap==NULL) + return ERROR_FAIL; - if (buf_get_u32(device->cur_instr, 0, device->ir_length) != new_instr) + if (buf_get_u32(tap->cur_instr, 0, tap->ir_length) != new_instr) { scan_field_t field; - field.device = chain_pos; - field.num_bits = device->ir_length; + field.tap = tap; + field.num_bits = tap->ir_length; field.out_value = calloc(CEIL(field.num_bits, 8), 1); buf_set_u32(field.out_value, 0, field.num_bits, new_instr); field.out_mask = NULL; field.in_value = NULL; - jtag_set_check_value(&field, device->expected, device->expected_mask, NULL); + jtag_set_check_value(&field, tap->expected, tap->expected_mask, NULL); jtag_add_ir_scan(1, &field, -1); @@ -234,25 +237,6 @@ int xscale_jtag_set_instr(int chain_pos, u32 new_instr) return ERROR_OK; } -int xscale_jtag_callback(enum jtag_event event, void *priv) -{ - switch (event) - { - case JTAG_TRST_ASSERTED: - break; - case JTAG_TRST_RELEASED: - break; - case JTAG_SRST_ASSERTED: - break; - case JTAG_SRST_RELEASED: - break; - default: - WARNING("unhandled JTAG event"); - } - - return ERROR_OK; -} - int xscale_read_dcsr(target_t *target) { armv4_5_common_t *armv4_5 = target->arch_info; @@ -269,19 +253,19 @@ int xscale_read_dcsr(target_t *target) u8 field2_check_mask = 0x1; jtag_add_end_state(TAP_PD); - xscale_jtag_set_instr(xscale->jtag_info.chain_pos, xscale->jtag_info.dcsr); + xscale_jtag_set_instr(xscale->jtag_info.tap, xscale->jtag_info.dcsr); buf_set_u32(&field0, 1, 1, xscale->hold_rst); buf_set_u32(&field0, 2, 1, xscale->external_debug_break); - fields[0].device = xscale->jtag_info.chain_pos; + fields[0].tap = xscale->jtag_info.tap; fields[0].num_bits = 3; fields[0].out_value = &field0; fields[0].out_mask = NULL; fields[0].in_value = NULL; jtag_set_check_value(fields+0, &field0_check_value, &field0_check_mask, NULL); - fields[1].device = xscale->jtag_info.chain_pos; + fields[1].tap = xscale->jtag_info.tap; fields[1].num_bits = 32; fields[1].out_value = NULL; fields[1].out_mask = NULL; @@ -291,7 +275,7 @@ int xscale_read_dcsr(target_t *target) fields[1].in_check_value = NULL; fields[1].in_check_mask = NULL; - fields[2].device = xscale->jtag_info.chain_pos; + fields[2].tap = xscale->jtag_info.tap; fields[2].num_bits = 1; fields[2].out_value = &field2; fields[2].out_mask = NULL; @@ -302,7 +286,7 @@ int xscale_read_dcsr(target_t *target) if ((retval = jtag_execute_queue()) != ERROR_OK) { - ERROR("JTAG error while reading DCSR"); + LOG_ERROR("JTAG error while reading DCSR"); return retval; } @@ -329,7 +313,7 @@ int xscale_receive(target_t *target, u32 *buffer, int num_words) { if (num_words==0) return ERROR_INVALID_ARGUMENTS; - + int retval=ERROR_OK; armv4_5_common_t *armv4_5 = target->arch_info; xscale_common_t *xscale = armv4_5->arch_info; @@ -352,14 +336,14 @@ int xscale_receive(target_t *target, u32 *buffer, int num_words) path[1] = TAP_CD; path[2] = TAP_SD; - fields[0].device = xscale->jtag_info.chain_pos; + fields[0].tap = xscale->jtag_info.tap; fields[0].num_bits = 3; fields[0].out_value = NULL; fields[0].out_mask = NULL; fields[0].in_value = NULL; jtag_set_check_value(fields+0, &field0_check_value, &field0_check_mask, NULL); - fields[1].device = xscale->jtag_info.chain_pos; + fields[1].tap = xscale->jtag_info.tap; fields[1].num_bits = 32; fields[1].out_value = NULL; fields[1].out_mask = NULL; @@ -371,7 +355,7 @@ int xscale_receive(target_t *target, u32 *buffer, int num_words) - fields[2].device = xscale->jtag_info.chain_pos; + fields[2].tap = xscale->jtag_info.tap; fields[2].num_bits = 1; fields[2].out_value = NULL; fields[2].out_mask = NULL; @@ -379,7 +363,7 @@ int xscale_receive(target_t *target, u32 *buffer, int num_words) jtag_set_check_value(fields+2, &field2_check_value, &field2_check_mask, NULL); jtag_add_end_state(TAP_RTI); - xscale_jtag_set_instr(xscale->jtag_info.chain_pos, xscale->jtag_info.dbgtx); + xscale_jtag_set_instr(xscale->jtag_info.tap, xscale->jtag_info.dbgtx); jtag_add_runtest(1, -1); /* ensures that we're in the TAP_RTI state as the above could be a no-op */ /* repeat until all words have been collected */ @@ -401,7 +385,7 @@ int xscale_receive(target_t *target, u32 *buffer, int num_words) if ((retval = jtag_execute_queue()) != ERROR_OK) { - ERROR("JTAG error while receiving data from debug handler"); + LOG_ERROR("JTAG error while receiving data from debug handler"); break; } @@ -424,12 +408,12 @@ int xscale_receive(target_t *target, u32 *buffer, int num_words) { if (attempts++==1000) { - ERROR("Failed to receiving data from debug handler after 1000 attempts"); + LOG_ERROR("Failed to receiving data from debug handler after 1000 attempts"); retval=ERROR_TARGET_TIMEOUT; break; } } - + words_done += words_scheduled; } @@ -446,7 +430,7 @@ int xscale_read_tx(target_t *target, int consume) armv4_5_common_t *armv4_5 = target->arch_info; xscale_common_t *xscale = armv4_5->arch_info; enum tap_state path[3]; - enum tap_state noconsume_path[9]; + enum tap_state noconsume_path[6]; int retval; struct timeval timeout, now; @@ -460,7 +444,7 @@ int xscale_read_tx(target_t *target, int consume) jtag_add_end_state(TAP_RTI); - xscale_jtag_set_instr(xscale->jtag_info.chain_pos, xscale->jtag_info.dbgtx); + xscale_jtag_set_instr(xscale->jtag_info.tap, xscale->jtag_info.dbgtx); path[0] = TAP_SDS; path[1] = TAP_CD; @@ -471,19 +455,16 @@ int xscale_read_tx(target_t *target, int consume) noconsume_path[2] = TAP_E1D; noconsume_path[3] = TAP_PD; noconsume_path[4] = TAP_E2D; - noconsume_path[5] = TAP_UD; - noconsume_path[6] = TAP_SDS; - noconsume_path[7] = TAP_CD; - noconsume_path[8] = TAP_SD; - - fields[0].device = xscale->jtag_info.chain_pos; + noconsume_path[5] = TAP_SD; + + fields[0].tap = xscale->jtag_info.tap; fields[0].num_bits = 3; fields[0].out_value = NULL; fields[0].out_mask = NULL; fields[0].in_value = &field0_in; jtag_set_check_value(fields+0, &field0_check_value, &field0_check_mask, NULL); - fields[1].device = xscale->jtag_info.chain_pos; + fields[1].tap = xscale->jtag_info.tap; fields[1].num_bits = 32; fields[1].out_value = NULL; fields[1].out_mask = NULL; @@ -495,7 +476,7 @@ int xscale_read_tx(target_t *target, int consume) - fields[2].device = xscale->jtag_info.chain_pos; + fields[2].tap = xscale->jtag_info.tap; fields[2].num_bits = 1; fields[2].out_value = NULL; fields[2].out_mask = NULL; @@ -503,7 +484,7 @@ int xscale_read_tx(target_t *target, int consume) jtag_set_check_value(fields+2, &field2_check_value, &field2_check_mask, NULL); gettimeofday(&timeout, NULL); - timeval_add_time(&timeout, 5, 0); + timeval_add_time(&timeout, 1, 0); for (;;) { @@ -514,28 +495,38 @@ int xscale_read_tx(target_t *target, int consume) if (consume) jtag_add_pathmove(3, path); else + { jtag_add_pathmove(sizeof(noconsume_path)/sizeof(*noconsume_path), noconsume_path); + } jtag_add_dr_scan(3, fields, TAP_RTI); if ((retval = jtag_execute_queue()) != ERROR_OK) { - ERROR("JTAG error while reading TX"); + LOG_ERROR("JTAG error while reading TX"); return ERROR_TARGET_TIMEOUT; } gettimeofday(&now, NULL); if ((now.tv_sec > timeout.tv_sec) || ((now.tv_sec == timeout.tv_sec)&& (now.tv_usec > timeout.tv_usec))) { - ERROR("time out reading TX register"); + LOG_ERROR("time out reading TX register"); return ERROR_TARGET_TIMEOUT; } if (!((!(field0_in & 1)) && consume)) { - break; + goto done; } - usleep(500*1000); /* avoid flooding the logs */ - } + if (debug_level>=3) + { + LOG_DEBUG("waiting 100ms"); + alive_sleep(100); /* avoid flooding the logs */ + } else + { + keep_alive(); + } + } + done: if (!(field0_in & 1)) return ERROR_TARGET_RESOURCE_NOT_AVAILABLE; @@ -562,16 +553,16 @@ int xscale_write_rx(target_t *target) jtag_add_end_state(TAP_RTI); - xscale_jtag_set_instr(xscale->jtag_info.chain_pos, xscale->jtag_info.dbgrx); + xscale_jtag_set_instr(xscale->jtag_info.tap, xscale->jtag_info.dbgrx); - fields[0].device = xscale->jtag_info.chain_pos; + fields[0].tap = xscale->jtag_info.tap; fields[0].num_bits = 3; fields[0].out_value = &field0_out; fields[0].out_mask = NULL; fields[0].in_value = &field0_in; jtag_set_check_value(fields+0, &field0_check_value, &field0_check_mask, NULL); - fields[1].device = xscale->jtag_info.chain_pos; + fields[1].tap = xscale->jtag_info.tap; fields[1].num_bits = 32; fields[1].out_value = xscale->reg_cache->reg_list[XSCALE_RX].value; fields[1].out_mask = NULL; @@ -583,7 +574,7 @@ int xscale_write_rx(target_t *target) - fields[2].device = xscale->jtag_info.chain_pos; + fields[2].tap = xscale->jtag_info.tap; fields[2].num_bits = 1; fields[2].out_value = &field2; fields[2].out_mask = NULL; @@ -591,30 +582,38 @@ int xscale_write_rx(target_t *target) jtag_set_check_value(fields+2, &field2_check_value, &field2_check_mask, NULL); gettimeofday(&timeout, NULL); - timeval_add_time(&timeout, 5, 0); + timeval_add_time(&timeout, 1, 0); /* poll until rx_read is low */ - DEBUG("polling RX"); + LOG_DEBUG("polling RX"); for (;;) { jtag_add_dr_scan(3, fields, TAP_RTI); if ((retval = jtag_execute_queue()) != ERROR_OK) { - ERROR("JTAG error while writing RX"); + LOG_ERROR("JTAG error while writing RX"); return retval; } gettimeofday(&now, NULL); if ((now.tv_sec > timeout.tv_sec) || ((now.tv_sec == timeout.tv_sec)&& (now.tv_usec > timeout.tv_usec))) { - ERROR("time out writing RX register"); + LOG_ERROR("time out writing RX register"); return ERROR_TARGET_TIMEOUT; } if (!(field0_in & 1)) - break; - usleep(500*1000); /* wait 500ms to avoid flooding the logs */ + goto done; + if (debug_level>=3) + { + LOG_DEBUG("waiting 100ms"); + alive_sleep(100); /* avoid flooding the logs */ + } else + { + keep_alive(); + } } + done: /* set rx_valid */ field2 = 0x1; @@ -622,7 +621,7 @@ int xscale_write_rx(target_t *target) if ((retval = jtag_execute_queue()) != ERROR_OK) { - ERROR("JTAG error while writing RX"); + LOG_ERROR("JTAG error while writing RX"); return retval; } @@ -634,109 +633,63 @@ int xscale_send(target_t *target, u8 *buffer, int count, int size) { armv4_5_common_t *armv4_5 = target->arch_info; xscale_common_t *xscale = armv4_5->arch_info; + u32 t[3]; + int bits[3]; int retval; int done_count = 0; - u8 output[4] = {0, 0, 0, 0}; - - scan_field_t fields[3]; - u8 field0_out = 0x0; - u8 field0_check_value = 0x2; - u8 field0_check_mask = 0x6; - u8 field2 = 0x1; - u8 field2_check_value = 0x0; - u8 field2_check_mask = 0x1; jtag_add_end_state(TAP_RTI); - xscale_jtag_set_instr(xscale->jtag_info.chain_pos, xscale->jtag_info.dbgrx); - - fields[0].device = xscale->jtag_info.chain_pos; - fields[0].num_bits = 3; - fields[0].out_value = &field0_out; - fields[0].out_mask = NULL; - fields[0].in_handler = NULL; - fields[0].in_value = NULL; - if (!xscale->fast_memory_access) - { - jtag_set_check_value(fields+0, &field0_check_value, &field0_check_mask, NULL); - } - - fields[1].device = xscale->jtag_info.chain_pos; - fields[1].num_bits = 32; - fields[1].out_value = output; - fields[1].out_mask = NULL; - fields[1].in_value = NULL; - fields[1].in_handler = NULL; - fields[1].in_handler_priv = NULL; - fields[1].in_check_value = NULL; - fields[1].in_check_mask = NULL; - + xscale_jtag_set_instr(xscale->jtag_info.tap, xscale->jtag_info.dbgrx); - - fields[2].device = xscale->jtag_info.chain_pos; - fields[2].num_bits = 1; - fields[2].out_value = &field2; - fields[2].out_mask = NULL; - fields[2].in_value = NULL; - fields[2].in_handler = NULL; - if (!xscale->fast_memory_access) - { - jtag_set_check_value(fields+2, &field2_check_value, &field2_check_mask, NULL); - } - - if (size==4) + bits[0]=3; + t[0]=0; + bits[1]=32; + t[2]=1; + bits[2]=1; + int endianness = target->endianness; + while (done_count++ < count) { - int endianness = target->endianness; - while (done_count++ < count) + switch (size) { + case 4: if (endianness == TARGET_LITTLE_ENDIAN) { - output[0]=buffer[0]; - output[1]=buffer[1]; - output[2]=buffer[2]; - output[3]=buffer[3]; + t[1]=le_to_h_u32(buffer); } else { - output[0]=buffer[3]; - output[1]=buffer[2]; - output[2]=buffer[1]; - output[3]=buffer[0]; + t[1]=be_to_h_u32(buffer); } - jtag_add_dr_scan(3, fields, TAP_RTI); - buffer += size; - } - - } else - { - while (done_count++ < count) - { - /* extract sized element from target-endian buffer, and put it - * into little-endian output buffer - */ - switch (size) + break; + case 2: + if (endianness == TARGET_LITTLE_ENDIAN) { - case 2: - buf_set_u32(output, 0, 32, target_buffer_get_u16(target, buffer)); - break; - case 1: - output[0] = *buffer; - break; - default: - ERROR("BUG: size neither 4, 2 nor 1"); - exit(-1); + t[1]=le_to_h_u16(buffer); + } else + { + t[1]=be_to_h_u16(buffer); } - - jtag_add_dr_scan(3, fields, TAP_RTI); - buffer += size; + break; + case 1: + t[1]=buffer[0]; + break; + default: + LOG_ERROR("BUG: size neither 4, 2 nor 1"); + exit(-1); } - + jtag_add_dr_out(xscale->jtag_info.tap, + 3, + bits, + t, + TAP_RTI); + buffer += size; } if ((retval = jtag_execute_queue()) != ERROR_OK) { - ERROR("JTAG error while sending data to debug handler"); + LOG_ERROR("JTAG error while sending data to debug handler"); return retval; } @@ -774,19 +727,19 @@ int xscale_write_dcsr(target_t *target, int hold_rst, int ext_dbg_brk) xscale->external_debug_break = ext_dbg_brk; jtag_add_end_state(TAP_RTI); - xscale_jtag_set_instr(xscale->jtag_info.chain_pos, xscale->jtag_info.dcsr); + xscale_jtag_set_instr(xscale->jtag_info.tap, xscale->jtag_info.dcsr); buf_set_u32(&field0, 1, 1, xscale->hold_rst); buf_set_u32(&field0, 2, 1, xscale->external_debug_break); - fields[0].device = xscale->jtag_info.chain_pos; + fields[0].tap = xscale->jtag_info.tap; fields[0].num_bits = 3; fields[0].out_value = &field0; fields[0].out_mask = NULL; fields[0].in_value = NULL; jtag_set_check_value(fields+0, &field0_check_value, &field0_check_mask, NULL); - fields[1].device = xscale->jtag_info.chain_pos; + fields[1].tap = xscale->jtag_info.tap; fields[1].num_bits = 32; fields[1].out_value = xscale->reg_cache->reg_list[XSCALE_DCSR].value; fields[1].out_mask = NULL; @@ -798,7 +751,7 @@ int xscale_write_dcsr(target_t *target, int hold_rst, int ext_dbg_brk) - fields[2].device = xscale->jtag_info.chain_pos; + fields[2].tap = xscale->jtag_info.tap; fields[2].num_bits = 1; fields[2].out_value = &field2; fields[2].out_mask = NULL; @@ -809,7 +762,7 @@ int xscale_write_dcsr(target_t *target, int hold_rst, int ext_dbg_brk) if ((retval = jtag_execute_queue()) != ERROR_OK) { - ERROR("JTAG error while writing DCSR"); + LOG_ERROR("JTAG error while writing DCSR"); return retval; } @@ -827,7 +780,7 @@ unsigned int parity (unsigned int v) v ^= v >> 8; v ^= v >> 4; v &= 0xf; - DEBUG("parity of 0x%x is %i", ov, (0x6996 >> v) & 1); + LOG_DEBUG("parity of 0x%x is %i", ov, (0x6996 >> v) & 1); return (0x6996 >> v) & 1; } @@ -841,10 +794,10 @@ int xscale_load_ic(target_t *target, int mini, u32 va, u32 buffer[8]) scan_field_t fields[2]; - DEBUG("loading miniIC at 0x%8.8x", va); + LOG_DEBUG("loading miniIC at 0x%8.8x", va); jtag_add_end_state(TAP_RTI); - xscale_jtag_set_instr(xscale->jtag_info.chain_pos, xscale->jtag_info.ldic); /* LDIC */ + xscale_jtag_set_instr(xscale->jtag_info.tap, xscale->jtag_info.ldic); /* LDIC */ /* CMD is b010 for Main IC and b011 for Mini IC */ if (mini) @@ -857,7 +810,7 @@ int xscale_load_ic(target_t *target, int mini, u32 va, u32 buffer[8]) /* virtual address of desired cache line */ buf_set_u32(packet, 0, 27, va >> 5); - fields[0].device = xscale->jtag_info.chain_pos; + fields[0].tap = xscale->jtag_info.tap; fields[0].num_bits = 6; fields[0].out_value = &cmd; fields[0].out_mask = NULL; @@ -867,7 +820,7 @@ int xscale_load_ic(target_t *target, int mini, u32 va, u32 buffer[8]) fields[0].in_handler = NULL; fields[0].in_handler_priv = NULL; - fields[1].device = xscale->jtag_info.chain_pos; + fields[1].tap = xscale->jtag_info.tap; fields[1].num_bits = 27; fields[1].out_value = packet; fields[1].out_mask = NULL; @@ -907,7 +860,7 @@ int xscale_invalidate_ic_line(target_t *target, u32 va) scan_field_t fields[2]; jtag_add_end_state(TAP_RTI); - xscale_jtag_set_instr(xscale->jtag_info.chain_pos, xscale->jtag_info.ldic); /* LDIC */ + xscale_jtag_set_instr(xscale->jtag_info.tap, xscale->jtag_info.ldic); /* LDIC */ /* CMD for invalidate IC line b000, bits [6:4] b000 */ buf_set_u32(&cmd, 0, 6, 0x0); @@ -915,7 +868,7 @@ int xscale_invalidate_ic_line(target_t *target, u32 va) /* virtual address of desired cache line */ buf_set_u32(packet, 0, 27, va >> 5); - fields[0].device = xscale->jtag_info.chain_pos; + fields[0].tap = xscale->jtag_info.tap; fields[0].num_bits = 6; fields[0].out_value = &cmd; fields[0].out_mask = NULL; @@ -925,7 +878,7 @@ int xscale_invalidate_ic_line(target_t *target, u32 va) fields[0].in_handler = NULL; fields[0].in_handler_priv = NULL; - fields[1].device = xscale->jtag_info.chain_pos; + fields[1].tap = xscale->jtag_info.tap; fields[1].num_bits = 27; fields[1].out_value = packet; fields[1].out_mask = NULL; @@ -1022,16 +975,16 @@ int xscale_arch_state(struct target_s *target) if (armv4_5->common_magic != ARMV4_5_COMMON_MAGIC) { - ERROR("BUG: called for a non-ARMv4/5 target"); + LOG_ERROR("BUG: called for a non-ARMv4/5 target"); exit(-1); } - USER("target halted in %s state due to %s, current mode: %s\n" + LOG_USER("target halted in %s state due to %s, current mode: %s\n" "cpsr: 0x%8.8x pc: 0x%8.8x\n" "MMU: %s, D-Cache: %s, I-Cache: %s" "%s", armv4_5_state_strings[armv4_5->core_state], - target_debug_reason_strings[target->debug_reason], + Jim_Nvp_value2name_simple( nvp_target_debug_reason, target->debug_reason )->name , armv4_5_mode_strings[armv4_5_mode_to_number(armv4_5->core_mode)], buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32), buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32), @@ -1065,11 +1018,11 @@ int xscale_poll(target_t *target) } else if (retval != ERROR_TARGET_RESOURCE_NOT_AVAILABLE) { - USER("error while polling TX register, reset CPU"); + LOG_USER("error while polling TX register, reset CPU"); /* here we "lie" so GDB won't get stuck and a reset can be perfomed */ target->state = TARGET_HALTED; } - + /* debug_entry could have overwritten target state (i.e. immediate resume) * don't signal event handlers in that case */ @@ -1102,7 +1055,7 @@ int xscale_debug_entry(target_t *target) xscale->external_debug_break = 0; if ((retval=xscale_read_dcsr(target))!=ERROR_OK) return retval; - + /* get r0, pc, r1 to r7 and cpsr */ if ((retval=xscale_receive(target, buffer, 10))!=ERROR_OK) return retval; @@ -1111,13 +1064,13 @@ int xscale_debug_entry(target_t *target) buf_set_u32(armv4_5->core_cache->reg_list[0].value, 0, 32, buffer[0]); armv4_5->core_cache->reg_list[15].dirty = 1; armv4_5->core_cache->reg_list[15].valid = 1; - DEBUG("r0: 0x%8.8x", buffer[0]); + LOG_DEBUG("r0: 0x%8.8x", buffer[0]); /* move pc from buffer to register cache */ buf_set_u32(armv4_5->core_cache->reg_list[15].value, 0, 32, buffer[1]); armv4_5->core_cache->reg_list[15].dirty = 1; armv4_5->core_cache->reg_list[15].valid = 1; - DEBUG("pc: 0x%8.8x", buffer[1]); + LOG_DEBUG("pc: 0x%8.8x", buffer[1]); /* move data from buffer to register cache */ for (i = 1; i <= 7; i++) @@ -1125,28 +1078,32 @@ int xscale_debug_entry(target_t *target) buf_set_u32(armv4_5->core_cache->reg_list[i].value, 0, 32, buffer[1 + i]); armv4_5->core_cache->reg_list[i].dirty = 1; armv4_5->core_cache->reg_list[i].valid = 1; - DEBUG("r%i: 0x%8.8x", i, buffer[i + 1]); + LOG_DEBUG("r%i: 0x%8.8x", i, buffer[i + 1]); } buf_set_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32, buffer[9]); armv4_5->core_cache->reg_list[ARMV4_5_CPSR].dirty = 1; armv4_5->core_cache->reg_list[ARMV4_5_CPSR].valid = 1; - DEBUG("cpsr: 0x%8.8x", buffer[9]); + LOG_DEBUG("cpsr: 0x%8.8x", buffer[9]); armv4_5->core_mode = buffer[9] & 0x1f; if (armv4_5_mode_to_number(armv4_5->core_mode) == -1) { target->state = TARGET_UNKNOWN; - ERROR("cpsr contains invalid mode value - communication failure"); + LOG_ERROR("cpsr contains invalid mode value - communication failure"); return ERROR_TARGET_FAILURE; } - DEBUG("target entered debug state in %s mode", armv4_5_mode_strings[armv4_5_mode_to_number(armv4_5->core_mode)]); + LOG_DEBUG("target entered debug state in %s mode", armv4_5_mode_strings[armv4_5_mode_to_number(armv4_5->core_mode)]); if (buffer[9] & 0x20) armv4_5->core_state = ARMV4_5_STATE_THUMB; else armv4_5->core_state = ARMV4_5_STATE_ARM; + + if (armv4_5_mode_to_number(armv4_5->core_mode)==-1) + return ERROR_FAIL; + /* get banked registers, r8 to r14, and spsr if not in USR/SYS mode */ if ((armv4_5->core_mode != ARMV4_5_MODE_USR) && (armv4_5->core_mode != ARMV4_5_MODE_SYS)) { @@ -1215,7 +1172,7 @@ int xscale_debug_entry(target_t *target) break; case 0x7: /* Reserved */ default: - ERROR("Method of Entry is 'Reserved'"); + LOG_ERROR("Method of Entry is 'Reserved'"); exit(-1); break; } @@ -1269,22 +1226,23 @@ int xscale_halt(target_t *target) armv4_5_common_t *armv4_5 = target->arch_info; xscale_common_t *xscale = armv4_5->arch_info; - DEBUG("target->state: %s", target_state_strings[target->state]); + LOG_DEBUG("target->state: %s", + Jim_Nvp_value2name_simple( nvp_target_state, target->state )->name); if (target->state == TARGET_HALTED) { - WARNING("target was already halted"); - return ERROR_TARGET_ALREADY_HALTED; + LOG_DEBUG("target was already halted"); + return ERROR_OK; } else if (target->state == TARGET_UNKNOWN) { /* this must not happen for a xscale target */ - ERROR("target was in unknown state when halt was requested"); + LOG_ERROR("target was in unknown state when halt was requested"); return ERROR_TARGET_INVALID; } else if (target->state == TARGET_RESET) { - DEBUG("target->state == TARGET_RESET"); + LOG_DEBUG("target->state == TARGET_RESET"); } else { @@ -1303,6 +1261,7 @@ int xscale_enable_single_step(struct target_s *target, u32 next_pc) armv4_5_common_t *armv4_5 = target->arch_info; xscale_common_t *xscale= armv4_5->arch_info; reg_t *ibcr0 = &xscale->reg_cache->reg_list[XSCALE_IBCR0]; + int retval; if (xscale->ibcr0_used) { @@ -1314,12 +1273,13 @@ int xscale_enable_single_step(struct target_s *target, u32 next_pc) } else { - ERROR("BUG: xscale->ibcr0_used is set, but no breakpoint with that address found"); + LOG_ERROR("BUG: xscale->ibcr0_used is set, but no breakpoint with that address found"); exit(-1); } } - xscale_set_reg_u32(ibcr0, next_pc | 0x1); + if ((retval=xscale_set_reg_u32(ibcr0, next_pc | 0x1))!=ERROR_OK) + return retval; return ERROR_OK; } @@ -1329,8 +1289,10 @@ int xscale_disable_single_step(struct target_s *target) armv4_5_common_t *armv4_5 = target->arch_info; xscale_common_t *xscale= armv4_5->arch_info; reg_t *ibcr0 = &xscale->reg_cache->reg_list[XSCALE_IBCR0]; + int retval; - xscale_set_reg_u32(ibcr0, 0x0); + if ((retval=xscale_set_reg_u32(ibcr0, 0x0))!=ERROR_OK) + return retval; return ERROR_OK; } @@ -1346,11 +1308,11 @@ int xscale_resume(struct target_s *target, int current, u32 address, int handle_ int retval; int i; - DEBUG("-"); + LOG_DEBUG("-"); if (target->state != TARGET_HALTED) { - WARNING("target not halted"); + LOG_WARNING("target not halted"); return ERROR_TARGET_NOT_HALTED; } @@ -1384,7 +1346,7 @@ int xscale_resume(struct target_s *target, int current, u32 address, int handle_ u32 next_pc; /* there's a breakpoint at the current PC, we have to step over it */ - DEBUG("unset breakpoint at 0x%8.8x", breakpoint->address); + LOG_DEBUG("unset breakpoint at 0x%8.8x", breakpoint->address); xscale_unset_breakpoint(target, breakpoint); /* calculate PC of next instruction */ @@ -1392,10 +1354,10 @@ int xscale_resume(struct target_s *target, int current, u32 address, int handle_ { u32 current_opcode; target_read_u32(target, current_pc, ¤t_opcode); - ERROR("BUG: couldn't calculate PC of next instruction, current opcode was 0x%8.8x", current_opcode); + LOG_ERROR("BUG: couldn't calculate PC of next instruction, current opcode was 0x%8.8x", current_opcode); } - DEBUG("enable single-step"); + LOG_DEBUG("enable single-step"); xscale_enable_single_step(target, next_pc); /* restore banked registers */ @@ -1413,26 +1375,26 @@ int xscale_resume(struct target_s *target, int current, u32 address, int handle_ /* send CPSR */ xscale_send_u32(target, buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32)); - DEBUG("writing cpsr with value 0x%8.8x", buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32)); + LOG_DEBUG("writing cpsr with value 0x%8.8x", buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32)); for (i = 7; i >= 0; i--) { /* send register */ xscale_send_u32(target, buf_get_u32(armv4_5->core_cache->reg_list[i].value, 0, 32)); - DEBUG("writing r%i with value 0x%8.8x", i, buf_get_u32(armv4_5->core_cache->reg_list[i].value, 0, 32)); + LOG_DEBUG("writing r%i with value 0x%8.8x", i, buf_get_u32(armv4_5->core_cache->reg_list[i].value, 0, 32)); } /* send PC */ xscale_send_u32(target, buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32)); - DEBUG("writing PC with value 0x%8.8x", buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32)); + LOG_DEBUG("writing PC with value 0x%8.8x", buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32)); /* wait for and process debug entry */ xscale_debug_entry(target); - DEBUG("disable single-step"); + LOG_DEBUG("disable single-step"); xscale_disable_single_step(target); - DEBUG("set breakpoint at 0x%8.8x", breakpoint->address); + LOG_DEBUG("set breakpoint at 0x%8.8x", breakpoint->address); xscale_set_breakpoint(target, breakpoint); } } @@ -1456,18 +1418,18 @@ int xscale_resume(struct target_s *target, int current, u32 address, int handle_ /* send CPSR */ xscale_send_u32(target, buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32)); - DEBUG("writing cpsr with value 0x%8.8x", buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32)); + LOG_DEBUG("writing cpsr with value 0x%8.8x", buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32)); for (i = 7; i >= 0; i--) { /* send register */ xscale_send_u32(target, buf_get_u32(armv4_5->core_cache->reg_list[i].value, 0, 32)); - DEBUG("writing r%i with value 0x%8.8x", i, buf_get_u32(armv4_5->core_cache->reg_list[i].value, 0, 32)); + LOG_DEBUG("writing r%i with value 0x%8.8x", i, buf_get_u32(armv4_5->core_cache->reg_list[i].value, 0, 32)); } /* send PC */ xscale_send_u32(target, buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32)); - DEBUG("writing PC with value 0x%8.8x", buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32)); + LOG_DEBUG("writing PC with value 0x%8.8x", buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32)); target->debug_reason = DBG_REASON_NOTHALTED; @@ -1484,53 +1446,22 @@ int xscale_resume(struct target_s *target, int current, u32 address, int handle_ target_call_event_callbacks(target, TARGET_EVENT_DEBUG_RESUMED); } - DEBUG("target resumed"); + LOG_DEBUG("target resumed"); xscale->handler_running = 1; return ERROR_OK; } -int xscale_step(struct target_s *target, int current, u32 address, int handle_breakpoints) +static int xscale_step_inner(struct target_s *target, int current, u32 address, int handle_breakpoints) { armv4_5_common_t *armv4_5 = target->arch_info; xscale_common_t *xscale = armv4_5->arch_info; - breakpoint_t *breakpoint = target->breakpoints; u32 current_pc, next_pc; - int i; int retval; + int i; - if (target->state != TARGET_HALTED) - { - WARNING("target not halted"); - return ERROR_TARGET_NOT_HALTED; - } - - /* current = 1: continue on current pc, otherwise continue at
*/ - if (!current) - buf_set_u32(armv4_5->core_cache->reg_list[15].value, 0, 32, address); - - current_pc = buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32); - - /* if we're at the reset vector, we have to simulate the step */ - if (current_pc == 0x0) - { - arm_simulate_step(target, NULL); - current_pc = buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32); - - target->debug_reason = DBG_REASON_SINGLESTEP; - target_call_event_callbacks(target, TARGET_EVENT_HALTED); - - return ERROR_OK; - } - - /* the front-end may request us not to handle breakpoints */ - if (handle_breakpoints) - if ((breakpoint = breakpoint_find(target, buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32)))) - { - xscale_unset_breakpoint(target, breakpoint); - } target->debug_reason = DBG_REASON_SINGLESTEP; @@ -1539,59 +1470,117 @@ int xscale_step(struct target_s *target, int current, u32 address, int handle_br { u32 current_opcode; target_read_u32(target, current_pc, ¤t_opcode); - ERROR("BUG: couldn't calculate PC of next instruction, current opcode was 0x%8.8x", current_opcode); + LOG_ERROR("BUG: couldn't calculate PC of next instruction, current opcode was 0x%8.8x", current_opcode); + return retval; } - DEBUG("enable single-step"); - xscale_enable_single_step(target, next_pc); + LOG_DEBUG("enable single-step"); + if ((retval=xscale_enable_single_step(target, next_pc))!=ERROR_OK) + return retval; /* restore banked registers */ - xscale_restore_context(target); + if ((retval=xscale_restore_context(target))!=ERROR_OK) + return retval; /* send resume request (command 0x30 or 0x31) * clean the trace buffer if it is to be enabled (0x62) */ if (xscale->trace.buffer_enabled) { - xscale_send_u32(target, 0x62); - xscale_send_u32(target, 0x31); + if ((retval=xscale_send_u32(target, 0x62))!=ERROR_OK) + return retval; + if ((retval=xscale_send_u32(target, 0x31))!=ERROR_OK) + return retval; } else - xscale_send_u32(target, 0x30); + if ((retval=xscale_send_u32(target, 0x30))!=ERROR_OK) + return retval; /* send CPSR */ - xscale_send_u32(target, buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32)); - DEBUG("writing cpsr with value 0x%8.8x", buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32)); + if ((retval=xscale_send_u32(target, buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32)))!=ERROR_OK) + return retval; + LOG_DEBUG("writing cpsr with value 0x%8.8x", buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32)); for (i = 7; i >= 0; i--) { /* send register */ - xscale_send_u32(target, buf_get_u32(armv4_5->core_cache->reg_list[i].value, 0, 32)); - DEBUG("writing r%i with value 0x%8.8x", i, buf_get_u32(armv4_5->core_cache->reg_list[i].value, 0, 32)); + if ((retval=xscale_send_u32(target, buf_get_u32(armv4_5->core_cache->reg_list[i].value, 0, 32)))!=ERROR_OK) + return retval; + LOG_DEBUG("writing r%i with value 0x%8.8x", i, buf_get_u32(armv4_5->core_cache->reg_list[i].value, 0, 32)); } /* send PC */ - xscale_send_u32(target, buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32)); - DEBUG("writing PC with value 0x%8.8x", buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32)); + if ((retval=xscale_send_u32(target, buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32)))!=ERROR_OK) + return retval; + LOG_DEBUG("writing PC with value 0x%8.8x", buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32)); target_call_event_callbacks(target, TARGET_EVENT_RESUMED); /* registers are now invalid */ - armv4_5_invalidate_core_regs(target); + if ((retval=armv4_5_invalidate_core_regs(target))!=ERROR_OK) + return retval; /* wait for and process debug entry */ - xscale_debug_entry(target); + if ((retval=xscale_debug_entry(target))!=ERROR_OK) + return retval; - DEBUG("disable single-step"); - xscale_disable_single_step(target); + LOG_DEBUG("disable single-step"); + if ((retval=xscale_disable_single_step(target))!=ERROR_OK) + return retval; target_call_event_callbacks(target, TARGET_EVENT_HALTED); + return ERROR_OK; +} + +int xscale_step(struct target_s *target, int current, u32 address, int handle_breakpoints) +{ + armv4_5_common_t *armv4_5 = target->arch_info; + breakpoint_t *breakpoint = target->breakpoints; + + u32 current_pc; + int retval; + + if (target->state != TARGET_HALTED) + { + LOG_WARNING("target not halted"); + return ERROR_TARGET_NOT_HALTED; + } + + /* current = 1: continue on current pc, otherwise continue at
*/ + if (!current) + buf_set_u32(armv4_5->core_cache->reg_list[15].value, 0, 32, address); + + current_pc = buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32); + + /* if we're at the reset vector, we have to simulate the step */ + if (current_pc == 0x0) + { + if ((retval=arm_simulate_step(target, NULL))!=ERROR_OK) + return retval; + current_pc = buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32); + + target->debug_reason = DBG_REASON_SINGLESTEP; + target_call_event_callbacks(target, TARGET_EVENT_HALTED); + + return ERROR_OK; + } + + /* the front-end may request us not to handle breakpoints */ + if (handle_breakpoints) + if ((breakpoint = breakpoint_find(target, buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32)))) + { + if ((retval=xscale_unset_breakpoint(target, breakpoint))!=ERROR_OK) + return retval; + } + + retval = xscale_step_inner(target, current, address, handle_breakpoints); + if (breakpoint) { xscale_set_breakpoint(target, breakpoint); } - DEBUG("target stepped"); + LOG_DEBUG("target stepped"); return ERROR_OK; @@ -1602,13 +1591,14 @@ int xscale_assert_reset(target_t *target) armv4_5_common_t *armv4_5 = target->arch_info; xscale_common_t *xscale = armv4_5->arch_info; - DEBUG("target->state: %s", target_state_strings[target->state]); + LOG_DEBUG("target->state: %s", + Jim_Nvp_value2name_simple( nvp_target_state, target->state )->name); /* select DCSR instruction (set endstate to R-T-I to ensure we don't * end up in T-L-R, which would reset JTAG */ jtag_add_end_state(TAP_RTI); - xscale_jtag_set_instr(xscale->jtag_info.chain_pos, xscale->jtag_info.dcsr); + xscale_jtag_set_instr(xscale->jtag_info.tap, xscale->jtag_info.dcsr); /* set Hold reset, Halt mode and Trap Reset */ buf_set_u32(xscale->reg_cache->reg_list[XSCALE_DCSR].value, 30, 1, 0x1); @@ -1616,7 +1606,7 @@ int xscale_assert_reset(target_t *target) xscale_write_dcsr(target, 1, 0); /* select BYPASS, because having DCSR selected caused problems on the PXA27x */ - xscale_jtag_set_instr(xscale->jtag_info.chain_pos, 0x7f); + xscale_jtag_set_instr(xscale->jtag_info.tap, 0x7f); jtag_execute_queue(); /* assert reset */ @@ -1628,6 +1618,13 @@ int xscale_assert_reset(target_t *target) target->state = TARGET_RESET; + if (target->reset_halt) + { + int retval; + if ((retval = target_halt(target))!=ERROR_OK) + return retval; + } + return ERROR_OK; } @@ -1646,7 +1643,7 @@ int xscale_deassert_reset(target_t *target) breakpoint_t *breakpoint = target->breakpoints; - DEBUG("-"); + LOG_DEBUG("-"); xscale->ibcr_available = 2; xscale->ibcr0_used = 0; @@ -1690,13 +1687,13 @@ int xscale_deassert_reset(target_t *target) if ((binary_size = debug_handler.size) % 4) { - ERROR("debug_handler.bin: size not a multiple of 4"); + LOG_ERROR("debug_handler.bin: size not a multiple of 4"); exit(-1); } if (binary_size > 0x800) { - ERROR("debug_handler.bin: larger than 2kb"); + LOG_ERROR("debug_handler.bin: larger than 2kb"); exit(-1); } @@ -1710,7 +1707,7 @@ int xscale_deassert_reset(target_t *target) if ((retval = fileio_read(&debug_handler, 32, buffer, &buf_cnt)) != ERROR_OK) { - + } for (i = 0; i < buf_cnt; i += 4) @@ -1750,7 +1747,7 @@ int xscale_deassert_reset(target_t *target) xscale_write_dcsr(target, 0, 1); target->state = TARGET_RUNNING; - if ((target->reset_mode != RESET_HALT) && (target->reset_mode != RESET_INIT)) + if (!target->reset_halt) { jtag_add_sleep(10000); @@ -1779,14 +1776,6 @@ int xscale_soft_reset_halt(struct target_s *target) return ERROR_OK; } -int xscale_prepare_reset_halt(struct target_s *target) -{ - /* nothing to be done for reset_halt on XScale targets - * we always halt after a reset to upload the debug handler - */ - return ERROR_OK; -} - int xscale_read_core_reg(struct target_s *target, int num, enum armv4_5_mode mode) { @@ -1807,11 +1796,11 @@ int xscale_full_context(target_t *target) int i, j; - DEBUG("-"); + LOG_DEBUG("-"); if (target->state != TARGET_HALTED) { - WARNING("target not halted"); + LOG_WARNING("target not halted"); return ERROR_TARGET_NOT_HALTED; } @@ -1881,11 +1870,11 @@ int xscale_restore_context(target_t *target) int i, j; - DEBUG("-"); + LOG_DEBUG("-"); if (target->state != TARGET_HALTED) { - WARNING("target not halted"); + LOG_WARNING("target not halted"); return ERROR_TARGET_NOT_HALTED; } @@ -1952,11 +1941,11 @@ int xscale_read_memory(struct target_s *target, u32 address, u32 size, u32 count int i; int retval; - DEBUG("address: 0x%8.8x, size: 0x%8.8x, count: 0x%8.8x", address, size, count); + LOG_DEBUG("address: 0x%8.8x, size: 0x%8.8x, count: 0x%8.8x", address, size, count); if (target->state != TARGET_HALTED) { - WARNING("target not halted"); + LOG_WARNING("target not halted"); return ERROR_TARGET_NOT_HALTED; } @@ -2001,7 +1990,7 @@ int xscale_read_memory(struct target_s *target, u32 address, u32 size, u32 count *buffer++ = buf32[i] & 0xff; break; default: - ERROR("should never get here"); + LOG_ERROR("should never get here"); exit(-1); } } @@ -2029,11 +2018,11 @@ int xscale_write_memory(struct target_s *target, u32 address, u32 size, u32 coun xscale_common_t *xscale = armv4_5->arch_info; int retval; - DEBUG("address: 0x%8.8x, size: 0x%8.8x, count: 0x%8.8x", address, size, count); + LOG_DEBUG("address: 0x%8.8x, size: 0x%8.8x, count: 0x%8.8x", address, size, count); if (target->state != TARGET_HALTED) { - WARNING("target not halted"); + LOG_WARNING("target not halted"); return ERROR_TARGET_NOT_HALTED; } @@ -2078,7 +2067,7 @@ int xscale_write_memory(struct target_s *target, u32 address, u32 size, u32 coun buffer += 1; break; default: - ERROR("should never get here"); + LOG_ERROR("should never get here"); exit(-1); } } @@ -2106,11 +2095,6 @@ int xscale_bulk_write_memory(target_t *target, u32 address, u32 count, u8 *buffe return xscale_write_memory(target, address, 4, count, buffer); } -int xscale_checksum_memory(struct target_s *target, u32 address, u32 count, u32* checksum) -{ - return ERROR_TARGET_RESOURCE_NOT_AVAILABLE; -} - u32 xscale_get_ttb(target_t *target) { armv4_5_common_t *armv4_5 = target->arch_info; @@ -2190,21 +2174,19 @@ void xscale_enable_mmu_caches(target_t *target, int mmu, int d_u_cache, int i_ca int xscale_set_breakpoint(struct target_s *target, breakpoint_t *breakpoint) { + int retval; armv4_5_common_t *armv4_5 = target->arch_info; xscale_common_t *xscale = armv4_5->arch_info; if (target->state != TARGET_HALTED) { - WARNING("target not halted"); + LOG_WARNING("target not halted"); return ERROR_TARGET_NOT_HALTED; } - if (xscale->force_hw_bkpts) - breakpoint->type = BKPT_HARD; - if (breakpoint->set) { - WARNING("breakpoint already set"); + LOG_WARNING("breakpoint already set"); return ERROR_OK; } @@ -2225,7 +2207,7 @@ int xscale_set_breakpoint(struct target_s *target, breakpoint_t *breakpoint) } else { - ERROR("BUG: no hardware comparator available"); + LOG_ERROR("BUG: no hardware comparator available"); return ERROR_OK; } } @@ -2234,16 +2216,28 @@ int xscale_set_breakpoint(struct target_s *target, breakpoint_t *breakpoint) if (breakpoint->length == 4) { /* keep the original instruction in target endianness */ - target->type->read_memory(target, breakpoint->address, 4, 1, breakpoint->orig_instr); + if((retval = target->type->read_memory(target, breakpoint->address, 4, 1, breakpoint->orig_instr)) != ERROR_OK) + { + return retval; + } /* write the original instruction in target endianness (arm7_9->arm_bkpt is host endian) */ - target_write_u32(target, breakpoint->address, xscale->arm_bkpt); + if((retval = target_write_u32(target, breakpoint->address, xscale->arm_bkpt)) != ERROR_OK) + { + return retval; + } } else { /* keep the original instruction in target endianness */ - target->type->read_memory(target, breakpoint->address, 2, 1, breakpoint->orig_instr); + if((retval = target->type->read_memory(target, breakpoint->address, 2, 1, breakpoint->orig_instr)) != ERROR_OK) + { + return retval; + } /* write the original instruction in target endianness (arm7_9->arm_bkpt is host endian) */ - target_write_u32(target, breakpoint->address, xscale->thumb_bkpt); + if((retval = target_write_u32(target, breakpoint->address, xscale->thumb_bkpt)) != ERROR_OK) + { + return retval; + } } breakpoint->set = 1; } @@ -2259,19 +2253,13 @@ int xscale_add_breakpoint(struct target_s *target, breakpoint_t *breakpoint) if (target->state != TARGET_HALTED) { - WARNING("target not halted"); + LOG_WARNING("target not halted"); return ERROR_TARGET_NOT_HALTED; } - if (xscale->force_hw_bkpts) - { - DEBUG("forcing use of hardware breakpoint at address 0x%8.8x", breakpoint->address); - breakpoint->type = BKPT_HARD; - } - if ((breakpoint->type == BKPT_HARD) && (xscale->ibcr_available < 1)) { - INFO("no breakpoint unit available for hardware breakpoint"); + LOG_INFO("no breakpoint unit available for hardware breakpoint"); return ERROR_TARGET_RESOURCE_NOT_AVAILABLE; } else @@ -2281,7 +2269,7 @@ int xscale_add_breakpoint(struct target_s *target, breakpoint_t *breakpoint) if ((breakpoint->length != 2) && (breakpoint->length != 4)) { - INFO("only breakpoints of two (Thumb) or four (ARM) bytes length supported"); + LOG_INFO("only breakpoints of two (Thumb) or four (ARM) bytes length supported"); return ERROR_TARGET_RESOURCE_NOT_AVAILABLE; } @@ -2290,18 +2278,19 @@ int xscale_add_breakpoint(struct target_s *target, breakpoint_t *breakpoint) int xscale_unset_breakpoint(struct target_s *target, breakpoint_t *breakpoint) { + int retval; armv4_5_common_t *armv4_5 = target->arch_info; xscale_common_t *xscale = armv4_5->arch_info; if (target->state != TARGET_HALTED) { - WARNING("target not halted"); + LOG_WARNING("target not halted"); return ERROR_TARGET_NOT_HALTED; } if (!breakpoint->set) { - WARNING("breakpoint not set"); + LOG_WARNING("breakpoint not set"); return ERROR_OK; } @@ -2324,11 +2313,17 @@ int xscale_unset_breakpoint(struct target_s *target, breakpoint_t *breakpoint) /* restore original instruction (kept in target endianness) */ if (breakpoint->length == 4) { - target->type->write_memory(target, breakpoint->address, 4, 1, breakpoint->orig_instr); + if((retval = target->type->write_memory(target, breakpoint->address, 4, 1, breakpoint->orig_instr)) != ERROR_OK) + { + return retval; + } } else { - target->type->write_memory(target, breakpoint->address, 2, 1, breakpoint->orig_instr); + if((retval = target->type->write_memory(target, breakpoint->address, 2, 1, breakpoint->orig_instr)) != ERROR_OK) + { + return retval; + } } breakpoint->set = 0; } @@ -2343,7 +2338,7 @@ int xscale_remove_breakpoint(struct target_s *target, breakpoint_t *breakpoint) if (target->state != TARGET_HALTED) { - WARNING("target not halted"); + LOG_WARNING("target not halted"); return ERROR_TARGET_NOT_HALTED; } @@ -2368,7 +2363,7 @@ int xscale_set_watchpoint(struct target_s *target, watchpoint_t *watchpoint) if (target->state != TARGET_HALTED) { - WARNING("target not halted"); + LOG_WARNING("target not halted"); return ERROR_TARGET_NOT_HALTED; } @@ -2386,7 +2381,7 @@ int xscale_set_watchpoint(struct target_s *target, watchpoint_t *watchpoint) enable = 0x1; break; default: - ERROR("BUG: watchpoint->rw neither read, write nor access"); + LOG_ERROR("BUG: watchpoint->rw neither read, write nor access"); } if (!xscale->dbr0_used) @@ -2407,7 +2402,7 @@ int xscale_set_watchpoint(struct target_s *target, watchpoint_t *watchpoint) } else { - ERROR("BUG: no hardware comparator available"); + LOG_ERROR("BUG: no hardware comparator available"); return ERROR_OK; } @@ -2421,7 +2416,7 @@ int xscale_add_watchpoint(struct target_s *target, watchpoint_t *watchpoint) if (target->state != TARGET_HALTED) { - WARNING("target not halted"); + LOG_WARNING("target not halted"); return ERROR_TARGET_NOT_HALTED; } @@ -2449,13 +2444,13 @@ int xscale_unset_watchpoint(struct target_s *target, watchpoint_t *watchpoint) if (target->state != TARGET_HALTED) { - WARNING("target not halted"); + LOG_WARNING("target not halted"); return ERROR_TARGET_NOT_HALTED; } if (!watchpoint->set) { - WARNING("breakpoint not set"); + LOG_WARNING("breakpoint not set"); return ERROR_OK; } @@ -2483,7 +2478,7 @@ int xscale_remove_watchpoint(struct target_s *target, watchpoint_t *watchpoint) if (target->state != TARGET_HALTED) { - WARNING("target not halted"); + LOG_WARNING("target not halted"); return ERROR_TARGET_NOT_HALTED; } @@ -2661,7 +2656,7 @@ int xscale_read_trace(target_t *target) if (target->state != TARGET_HALTED) { - WARNING("target must be stopped to read trace data"); + LOG_WARNING("target must be stopped to read trace data"); return ERROR_TARGET_NOT_HALTED; } @@ -2696,7 +2691,7 @@ int xscale_read_trace(target_t *target) if (j == 256) { - DEBUG("no trace data collected"); + LOG_DEBUG("no trace data collected"); return ERROR_XSCALE_NO_TRACE_DATA; } @@ -2761,7 +2756,7 @@ int xscale_read_instruction(target_t *target, arm_instruction_t *instruction) xscale->trace.current_pc - xscale->trace.image->sections[section].base_address, 4, buf, &size_read)) != ERROR_OK) { - ERROR("error while reading instruction: %i", retval); + LOG_ERROR("error while reading instruction: %i", retval); return ERROR_TRACE_INSTRUCTION_UNAVAILABLE; } opcode = target_buffer_get_u32(target, buf); @@ -2774,7 +2769,7 @@ int xscale_read_instruction(target_t *target, arm_instruction_t *instruction) xscale->trace.current_pc - xscale->trace.image->sections[section].base_address, 2, buf, &size_read)) != ERROR_OK) { - ERROR("error while reading instruction: %i", retval); + LOG_ERROR("error while reading instruction: %i", retval); return ERROR_TRACE_INSTRUCTION_UNAVAILABLE; } opcode = target_buffer_get_u16(target, buf); @@ -2782,7 +2777,7 @@ int xscale_read_instruction(target_t *target, arm_instruction_t *instruction) } else { - ERROR("BUG: unknown core state encountered"); + LOG_ERROR("BUG: unknown core state encountered"); exit(-1); } @@ -2865,7 +2860,7 @@ int xscale_analyze_trace(target_t *target, command_context_t *cmd_ctx) next_pc_ok = 1; if (((chkpt == 0) && (next_pc != trace_data->chkpt0)) || ((chkpt == 1) && (next_pc != trace_data->chkpt1))) - WARNING("checkpointed indirect branch target address doesn't match checkpoint"); + LOG_WARNING("checkpointed indirect branch target address doesn't match checkpoint"); } /* explicit fall-through */ case 12: /* Checkpointed Direct Branch */ @@ -2884,7 +2879,7 @@ int xscale_analyze_trace(target_t *target, command_context_t *cmd_ctx) } else { - WARNING("more than two checkpointed branches encountered"); + LOG_WARNING("more than two checkpointed branches encountered"); } break; case 15: /* Roll-over */ @@ -2892,7 +2887,7 @@ int xscale_analyze_trace(target_t *target, command_context_t *cmd_ctx) continue; default: /* Reserved */ command_print(cmd_ctx, "--- reserved trace message ---"); - ERROR("BUG: trace message %i is reserved", (trace_data->entries[i].data & 0xf0) >> 4); + LOG_ERROR("BUG: trace message %i is reserved", (trace_data->entries[i].data & 0xf0) >> 4); return ERROR_OK; } @@ -3040,28 +3035,16 @@ void xscale_build_reg_cache(target_t *target) int xscale_init_target(struct command_context_s *cmd_ctx, struct target_s *target) { - if (startup_mode != DAEMON_RESET) - { - ERROR("XScale target requires a reset"); - ERROR("Reset target to enable debug"); - } - - /* assert TRST once during startup */ - jtag_add_reset(1, 0); - jtag_add_sleep(5000); - jtag_add_reset(0, 0); - jtag_execute_queue(); - return ERROR_OK; } -int xscale_quit() +int xscale_quit(void) { return ERROR_OK; } -int xscale_init_arch_info(target_t *target, xscale_common_t *xscale, int chain_pos, char *variant) +int xscale_init_arch_info(target_t *target, xscale_common_t *xscale, jtag_tap_t *tap, const char *variant) { armv4_5_common_t *armv4_5; u32 high_reset_branch, low_reset_branch; @@ -3077,8 +3060,7 @@ int xscale_init_arch_info(target_t *target, xscale_common_t *xscale, int chain_p xscale->variant = strdup(variant); /* prepare JTAG information for the new target */ - xscale->jtag_info.chain_pos = chain_pos; - jtag_register_event_callback(xscale_jtag_callback, target); + xscale->jtag_info.tap = tap; xscale->jtag_info.dbgrx = 0x02; xscale->jtag_info.dbgtx = 0x10; @@ -3131,8 +3113,6 @@ int xscale_init_arch_info(target_t *target, xscale_common_t *xscale, int chain_p xscale->hold_rst = 0; xscale->external_debug_break = 0; - xscale->force_hw_bkpts = 1; - xscale->ibcr_available = 2; xscale->ibcr0_used = 0; xscale->ibcr1_used = 0; @@ -3168,31 +3148,16 @@ int xscale_init_arch_info(target_t *target, xscale_common_t *xscale, int chain_p xscale->armv4_5_mmu.enable_mmu_caches = xscale_enable_mmu_caches; xscale->armv4_5_mmu.has_tiny_pages = 1; xscale->armv4_5_mmu.mmu_enabled = 0; - - xscale->fast_memory_access = 0; return ERROR_OK; } /* target xscale */ -int xscale_target_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct target_s *target) +int xscale_target_create(struct target_s *target, Jim_Interp *interp) { - int chain_pos; - char *variant = NULL; - xscale_common_t *xscale = malloc(sizeof(xscale_common_t)); - memset(xscale, 0, sizeof(*xscale)); - - if (argc < 5) - { - ERROR("'target xscale' requires four arguments: "); - return ERROR_OK; - } - - chain_pos = strtoul(args[3], NULL, 0); - - variant = args[4]; + xscale_common_t *xscale = calloc(1,sizeof(xscale_common_t)); - xscale_init_arch_info(target, xscale, chain_pos, variant); + xscale_init_arch_info(target, xscale, target->tap, target->variant); xscale_build_reg_cache(target); return ERROR_OK; @@ -3208,19 +3173,19 @@ int xscale_handle_debug_handler_command(struct command_context_s *cmd_ctx, char if (argc < 2) { - ERROR("'xscale debug_handler
' command takes two required operands"); + LOG_ERROR("'xscale debug_handler
' command takes two required operands"); return ERROR_OK; } if ((target = get_target_by_num(strtoul(args[0], NULL, 0))) == NULL) { - ERROR("no target '%s' configured", args[0]); - return ERROR_OK; + LOG_ERROR("no target '%s' configured", args[0]); + return ERROR_FAIL; } if (xscale_get_arch_pointers(target, &armv4_5, &xscale) != ERROR_OK) { - return ERROR_OK; + return ERROR_FAIL; } handler_address = strtoul(args[1], NULL, 0); @@ -3232,7 +3197,8 @@ int xscale_handle_debug_handler_command(struct command_context_s *cmd_ctx, char } else { - ERROR("xscale debug_handler
must be between 0x800 and 0x1fef800 or between 0xfe000800 and 0xfffff800"); + LOG_ERROR("xscale debug_handler
must be between 0x800 and 0x1fef800 or between 0xfe000800 and 0xfffff800"); + return ERROR_FAIL; } return ERROR_OK; @@ -3248,26 +3214,25 @@ int xscale_handle_cache_clean_address_command(struct command_context_s *cmd_ctx, if (argc < 2) { - ERROR("'xscale cache_clean_address
' command takes two required operands"); - return ERROR_OK; + return ERROR_COMMAND_SYNTAX_ERROR; } if ((target = get_target_by_num(strtoul(args[0], NULL, 0))) == NULL) { - ERROR("no target '%s' configured", args[0]); - return ERROR_OK; + LOG_ERROR("no target '%s' configured", args[0]); + return ERROR_FAIL; } if (xscale_get_arch_pointers(target, &armv4_5, &xscale) != ERROR_OK) { - return ERROR_OK; + return ERROR_FAIL; } cache_clean_address = strtoul(args[1], NULL, 0); if (cache_clean_address & 0xffff) { - ERROR("xscale cache_clean_address
must be 64kb aligned"); + LOG_ERROR("xscale cache_clean_address
must be 64kb aligned"); } else { @@ -3300,8 +3265,8 @@ static int xscale_virt2phys(struct target_s *target, u32 virtual, u32 *physical) u32 cb; int domain; u32 ap; - - + + if ((retval = xscale_get_arch_pointers(target, &armv4_5, &xscale)) != ERROR_OK) { return retval; @@ -3319,10 +3284,10 @@ static int xscale_mmu(struct target_s *target, int *enabled) { armv4_5_common_t *armv4_5 = target->arch_info; xscale_common_t *xscale = armv4_5->arch_info; - + if (target->state != TARGET_HALTED) { - ERROR("Target not halted"); + LOG_ERROR("Target not halted"); return ERROR_TARGET_INVALID; } *enabled = xscale->armv4_5_mmu.mmu_enabled; @@ -3447,34 +3412,6 @@ int xscale_handle_vector_catch_command(command_context_t *cmd_ctx, char *cmd, ch return ERROR_OK; } -int xscale_handle_force_hw_bkpts_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc) -{ - target_t *target = get_current_target(cmd_ctx); - armv4_5_common_t *armv4_5; - xscale_common_t *xscale; - - if (xscale_get_arch_pointers(target, &armv4_5, &xscale) != ERROR_OK) - { - return ERROR_OK; - } - - if ((argc >= 1) && (strcmp("enable", args[0]) == 0)) - { - xscale->force_hw_bkpts = 1; - } - else if ((argc >= 1) && (strcmp("disable", args[0]) == 0)) - { - xscale->force_hw_bkpts = 0; - } - else - { - command_print(cmd_ctx, "usage: xscale force_hw_bkpts "); - } - - command_print(cmd_ctx, "force hardware breakpoints %s", (xscale->force_hw_bkpts) ? "enabled" : "disabled"); - - return ERROR_OK; -} int xscale_handle_trace_buffer_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc) { @@ -3685,12 +3622,12 @@ int xscale_handle_cp15(command_context_t *cmd_ctx, char *cmd, char **args, int a target_t *target = get_current_target(cmd_ctx); armv4_5_common_t *armv4_5; xscale_common_t *xscale; - + if (xscale_get_arch_pointers(target, &armv4_5, &xscale) != ERROR_OK) { return ERROR_OK; } - + if (target->state != TARGET_HALTED) { command_print(cmd_ctx, "target must be stopped for \"%s\" command", cmd); @@ -3712,7 +3649,7 @@ int xscale_handle_cp15(command_context_t *cmd_ctx, char *cmd, char **args, int a break; case 2: reg_no = XSCALE_TTB; - break; + break; case 3: reg_no = XSCALE_DAC; break; @@ -3733,73 +3670,38 @@ int xscale_handle_cp15(command_context_t *cmd_ctx, char *cmd, char **args, int a return ERROR_INVALID_ARGUMENTS; } reg = &xscale->reg_cache->reg_list[reg_no]; - + } if(argc == 1) { u32 value; - + /* read cp15 control register */ xscale_get_reg(reg); value = buf_get_u32(reg->value, 0, 32); command_print(cmd_ctx, "%s (/%i): 0x%x", reg->name, reg->size, value); } else if(argc == 2) - { + { u32 value = strtoul(args[1], NULL, 0); - + /* send CP write request (command 0x41) */ xscale_send_u32(target, 0x41); - + /* send CP register number */ xscale_send_u32(target, reg_no); - + /* send CP register value */ xscale_send_u32(target, value); - + /* execute cpwait to ensure outstanding operations complete */ xscale_send_u32(target, 0x53); } else { - command_print(cmd_ctx, "usage: cp15 [register]<, [value]>"); - } - - return ERROR_OK; -} - -int handle_xscale_fast_memory_access_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc) -{ - target_t *target = get_current_target(cmd_ctx); - armv4_5_common_t *armv4_5; - xscale_common_t *xscale; - - if (xscale_get_arch_pointers(target, &armv4_5, &xscale) != ERROR_OK) - { - return ERROR_OK; - } - - if (argc == 1) - { - if (strcmp("enable", args[0]) == 0) - { - xscale->fast_memory_access = 1; - } - else if (strcmp("disable", args[0]) == 0) - { - xscale->fast_memory_access = 0; - } - else - { - return ERROR_COMMAND_SYNTAX_ERROR; - } - } else if (argc!=0) - { - return ERROR_COMMAND_SYNTAX_ERROR; + command_print(cmd_ctx, "usage: cp15 [register]<, [value]>"); } - - command_print(cmd_ctx, "fast memory access is %s", (xscale->fast_memory_access) ? "enabled" : "disabled"); return ERROR_OK; } @@ -3828,10 +3730,7 @@ int xscale_register_commands(struct command_context_s *cmd_ctx) COMMAND_EXEC, "load image from [base address]"); register_command(cmd_ctx, xscale_cmd, "cp15", xscale_handle_cp15, COMMAND_EXEC, "access coproc 15 [value]"); - register_command(cmd_ctx, xscale_cmd, "fast_memory_access", handle_xscale_fast_memory_access_command, - COMMAND_ANY, "use fast memory accesses instead of slower but potentially unsafe slow accesses "); - armv4_5_register_commands(cmd_ctx); return ERROR_OK;