X-Git-Url: https://review.openocd.org/gitweb?p=openocd.git;a=blobdiff_plain;f=src%2Ftarget%2Fmips_m4k.c;h=b84783b1ab0c2113c6b21fc220d53fe0405ed86e;hp=10d3c7da4d0b448ef8bdb7b61527fe38f581da08;hb=bad3ee87ac170150a9a8a72c731aa631a1ad8cf5;hpb=2615bf4398f393ee1e387128064093dcd44749c8 diff --git a/src/target/mips_m4k.c b/src/target/mips_m4k.c index 10d3c7da4d..b84783b1ab 100644 --- a/src/target/mips_m4k.c +++ b/src/target/mips_m4k.c @@ -120,7 +120,9 @@ static int mips_m4k_poll(struct target *target) /* read ejtag control reg */ mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL); - mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl); + retval = mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl); + if (retval != ERROR_OK) + return retval; /* clear this bit before handling polling * as after reset registers will read zero */ @@ -131,7 +133,9 @@ static int mips_m4k_poll(struct target *target) ejtag_ctrl = ejtag_info->ejtag_ctrl & ~EJTAG_CTRL_ROCC; mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL); - mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl); + retval = mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl); + if (retval != ERROR_OK) + return retval; LOG_DEBUG("Reset Detected"); } @@ -254,18 +258,14 @@ static int mips_m4k_assert_reset(struct target *target) { if (mips_m4k->is_pic32mx) { - uint32_t mchip_cmd; - LOG_DEBUG("Using MTAP reset to reset processor..."); /* use microchip specific MTAP reset */ mips_ejtag_set_instr(ejtag_info, MTAP_SW_MTAP); mips_ejtag_set_instr(ejtag_info, MTAP_COMMAND); - mchip_cmd = MCHP_ASERT_RST; - mips_ejtag_drscan_8(ejtag_info, &mchip_cmd); - mchip_cmd = MCHP_DE_ASSERT_RST; - mips_ejtag_drscan_8(ejtag_info, &mchip_cmd); + mips_ejtag_drscan_8_out(ejtag_info, MCHP_ASERT_RST); + mips_ejtag_drscan_8_out(ejtag_info, MCHP_DE_ASSERT_RST); mips_ejtag_set_instr(ejtag_info, MTAP_SW_ETAP); } else @@ -274,7 +274,7 @@ static int mips_m4k_assert_reset(struct target *target) uint32_t ejtag_ctrl = ejtag_info->ejtag_ctrl | EJTAG_CTRL_PRRST | EJTAG_CTRL_PERRST; LOG_DEBUG("Using EJTAG reset (PRRST) to reset processor..."); mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL); - mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl); + mips_ejtag_drscan_32_out(ejtag_info, ejtag_ctrl); } } @@ -616,6 +616,14 @@ static int mips_m4k_unset_breakpoint(struct target *target, { return retval; } + + /** + * target_read_memory() gets us data in _target_ endianess. + * If we want to use this data on the host for comparisons with some macros + * we must first transform it to _host_ endianess using target_buffer_get_u32(). + */ + current_instr = target_buffer_get_u32(target, (uint8_t *)¤t_instr); + if (current_instr == MIPS32_SDBBP) { if ((retval = target_write_memory(target, breakpoint->address, 4, 1, @@ -868,6 +876,25 @@ static int mips_m4k_read_memory(struct target *target, uint32_t address, if (ERROR_OK != retval) return retval; + /* mips32_..._read_mem with size 4/2 returns uint32_t/uint16_t in host */ + /* endianness, but byte array should represent target endianness */ + uint32_t i, t32; + uint16_t t16; + for(i = 0; i < (count*size); i += size) + { + switch(size) + { + case 4: + t32 = le_to_h_u32(&buffer[i]); + target_buffer_set_u32(target,&buffer[i], t32); + break; + case 2: + t16 = le_to_h_u16(&buffer[i]); + target_buffer_set_u16(target,&buffer[i], t16); + break; + } + } + return ERROR_OK; } @@ -893,11 +920,48 @@ static int mips_m4k_write_memory(struct target *target, uint32_t address, if (((size == 4) && (address & 0x3u)) || ((size == 2) && (address & 0x1u))) return ERROR_TARGET_UNALIGNED_ACCESS; + /* mips32_..._write_mem with size 4/2 requires uint32_t/uint16_t in host */ + /* endianness, but byte array represents target endianness */ + uint8_t * t = NULL; + t = malloc(count * sizeof(uint32_t)); + if (t == NULL) + { + LOG_ERROR("Out of memory"); + return ERROR_FAIL; + } + + uint32_t i, t32; + uint16_t t16; + for(i = 0; i < (count*size); i += size) + { + switch(size) + { + case 4: + t32 = target_buffer_get_u32(target,&buffer[i]); + h_u32_to_le(&t[i], t32); + break; + case 2: + t16 = target_buffer_get_u16(target,&buffer[i]); + h_u16_to_le(&t[i], t16); + break; + } + } + buffer = t; + /* if noDMA off, use DMAACC mode for memory write */ + int retval; if (ejtag_info->impcode & EJTAG_IMP_NODMA) - return mips32_pracc_write_mem(ejtag_info, address, size, count, (void *)buffer); + retval = mips32_pracc_write_mem(ejtag_info, address, size, count, (void *)buffer); else - return mips32_dmaacc_write_mem(ejtag_info, address, size, count, (void *)buffer); + retval = mips32_dmaacc_write_mem(ejtag_info, address, size, count, (void *)buffer); + + if (t != NULL) + free(t); + + if (ERROR_OK != retval) + return retval; + + return ERROR_OK; } static int mips_m4k_init_target(struct command_context *cmd_ctx, @@ -1004,30 +1068,25 @@ static int mips_m4k_bulk_write_memory(struct target *target, uint32_t address, ejtag_info->fast_access_save = -1; } + /* mips32_pracc_fastdata_xfer requires uint32_t in host endianness, */ + /* but byte array represents target endianness */ uint8_t * t = NULL; - - /* TAP data register is loaded LSB first (little endian) */ - if (target->endianness == TARGET_BIG_ENDIAN) + t = malloc(count * sizeof(uint32_t)); + if (t == NULL) { - t = malloc(count * sizeof(uint32_t)); - if (t == NULL) - { - LOG_ERROR("Out of memory"); - return ERROR_FAIL; - } - - uint32_t i, t32; - for(i = 0; i < (count * 4); i += 4) - { - t32 = be_to_h_u32((uint8_t *) &buffer[i]); - h_u32_to_le(&t[i], t32); - } - - buffer = t; + LOG_ERROR("Out of memory"); + return ERROR_FAIL; } + uint32_t i, t32; + for(i = 0; i < (count*4); i += 4) + { + t32 = target_buffer_get_u32(target,&buffer[i]); + h_u32_to_le(&t[i], t32); + } + retval = mips32_pracc_fastdata_xfer(ejtag_info, mips32->fast_data_area, write_t, address, - count, (uint32_t*) (void *)buffer); + count, (uint32_t*) (void *)t); if (t != NULL) free(t);