X-Git-Url: https://review.openocd.org/gitweb?p=openocd.git;a=blobdiff_plain;f=src%2Ftarget%2Fmips_m4k.c;h=7530cbd0bc7841c9e881001a9a1f0c40da71d0d4;hp=10d3c7da4d0b448ef8bdb7b61527fe38f581da08;hb=378567da4e40a31efed349fbe68deebd14079b94;hpb=2615bf4398f393ee1e387128064093dcd44749c8

diff --git a/src/target/mips_m4k.c b/src/target/mips_m4k.c
index 10d3c7da4d..7530cbd0bc 100644
--- a/src/target/mips_m4k.c
+++ b/src/target/mips_m4k.c
@@ -254,18 +254,14 @@ static int mips_m4k_assert_reset(struct target *target)
 	{
 		if (mips_m4k->is_pic32mx)
 		{
-			uint32_t mchip_cmd;
-
 			LOG_DEBUG("Using MTAP reset to reset processor...");
 
 			/* use microchip specific MTAP reset */
 			mips_ejtag_set_instr(ejtag_info, MTAP_SW_MTAP);
 			mips_ejtag_set_instr(ejtag_info, MTAP_COMMAND);
 
-			mchip_cmd = MCHP_ASERT_RST;
-			mips_ejtag_drscan_8(ejtag_info, &mchip_cmd);
-			mchip_cmd = MCHP_DE_ASSERT_RST;
-			mips_ejtag_drscan_8(ejtag_info, &mchip_cmd);
+			mips_ejtag_drscan_8_out(ejtag_info, MCHP_ASERT_RST);
+			mips_ejtag_drscan_8_out(ejtag_info, MCHP_DE_ASSERT_RST);
 			mips_ejtag_set_instr(ejtag_info, MTAP_SW_ETAP);
 		}
 		else