X-Git-Url: https://review.openocd.org/gitweb?p=openocd.git;a=blobdiff_plain;f=src%2Ftarget%2Fmips_ejtag.h;h=a6ed95a509b5bdc9c287ecbe4ed98ade5ccec42d;hp=d74d808bb191bd9998daf95d6a9581eaa3252430;hb=719f9ecde32ab60bcb65913454a9340c5754cee4;hpb=337017d626f9641fdafc50da5769e5bd14cfe30f

diff --git a/src/target/mips_ejtag.h b/src/target/mips_ejtag.h
index d74d808bb1..a6ed95a509 100644
--- a/src/target/mips_ejtag.h
+++ b/src/target/mips_ejtag.h
@@ -23,7 +23,7 @@
 #ifndef MIPS_EJTAG
 #define MIPS_EJTAG
 
-#include "jtag.h"
+#include <jtag/jtag.h>
 
 /* tap instructions */
 #define EJTAG_INST_IDCODE		0x01
@@ -40,7 +40,18 @@
 #define EJTAG_INST_TCBDATA		0x12
 #define EJTAG_INST_BYPASS		0xFF
 
-/* debug control register bits ECR */
+/* microchip PIC32MX specific instructions */
+#define MTAP_SW_MTAP			0x04
+#define MTAP_SW_ETAP			0x05
+#define MTAP_COMMAND			0x07
+
+/* microchip specific cmds */
+#define MCHP_ASERT_RST			0xd1
+#define MCHP_DE_ASSERT_RST		0xd0
+#define MCHP_ERASE				0xfc
+#define MCHP_STATUS				0x00
+
+/* ejtag control register bits ECR */
 #define EJTAG_CTRL_TOF			(1 << 1)
 #define EJTAG_CTRL_TIF			(1 << 2)
 #define EJTAG_CTRL_BRKST		(1 << 3)
@@ -87,34 +98,52 @@
 #define EJTAG_DEBUG_DBD			(1 << 31)
 
 /* implementaion register bits */
+#define EJTAG_IMP_R3K			(1 << 28)
+#define EJTAG_IMP_DINT			(1 << 24)
 #define EJTAG_IMP_NODMA			(1 << 14)
 #define EJTAG_IMP_MIPS16		(1 << 16)
+#define EJTAG_DCR_MIPS64		(1 << 0)
 
-/* breakpoint support */
+/* Debug Control Register DCR */
 #define EJTAG_DCR				0xFF300000
+#define EJTAG_DCR_ENM			(1 << 29)
+#define EJTAG_DCR_DB			(1 << 17)
+#define EJTAG_DCR_IB			(1 << 16)
+#define EJTAG_DCR_INTE			(1 << 4)
+
+/* breakpoint support */
 #define EJTAG_IBS				0xFF301000
 #define EJTAG_IBA1				0xFF301100
 #define EJTAG_DBS				0xFF302000
 #define EJTAG_DBA1				0xFF302100
+#define	EJTAG_DBCn_NOSB			(1 << 13)
+#define	EJTAG_DBCn_NOLB			(1 << 12)
+#define	EJTAG_DBCn_BLM_MASK		0xff
+#define	EJTAG_DBCn_BLM_SHIFT	4
+#define	EJTAG_DBCn_BE			(1 << 0)
 
-typedef struct mips_ejtag_s
+struct mips_ejtag
 {
-	jtag_tap_t *tap;
-	u32 impcode;
-	u32 idcode;
-	/*int use_dma;*/
-	u32 ejtag_ctrl;
-} mips_ejtag_t;
+	struct jtag_tap *tap;
+	uint32_t impcode;
+	uint32_t idcode;
+	uint32_t ejtag_ctrl;
+	int fast_access_save;
+};
 
-extern int mips_ejtag_set_instr(mips_ejtag_t *ejtag_info, int new_instr, void *delete_me_and_submit_patch);
-extern int mips_ejtag_enter_debug(mips_ejtag_t *ejtag_info);
-extern int mips_ejtag_exit_debug(mips_ejtag_t *ejtag_info);
-extern int mips_ejtag_get_impcode(mips_ejtag_t *ejtag_info, u32 *impcode);
-extern int mips_ejtag_get_idcode(mips_ejtag_t *ejtag_info, u32 *idcode);
-extern int mips_ejtag_drscan_32(mips_ejtag_t *ejtag_info, u32 *data);
+void mips_ejtag_set_instr(struct mips_ejtag *ejtag_info,
+		int new_instr);
+int mips_ejtag_enter_debug(struct mips_ejtag *ejtag_info);
+int mips_ejtag_exit_debug(struct mips_ejtag *ejtag_info);
+int mips_ejtag_get_idcode(struct mips_ejtag *ejtag_info, uint32_t *idcode);
+void mips_ejtag_drscan_32_out(struct mips_ejtag *ejtag_info, uint32_t data);
+int mips_ejtag_drscan_32(struct mips_ejtag *ejtag_info, uint32_t *data);
+void mips_ejtag_drscan_8_out(struct mips_ejtag *ejtag_info, uint8_t data);
+int mips_ejtag_drscan_8(struct mips_ejtag *ejtag_info, uint32_t *data);
+int mips_ejtag_fastdata_scan(struct mips_ejtag *ejtag_info, int write_t, uint32_t *data);
 
-extern int mips_ejtag_init(mips_ejtag_t *ejtag_info);
-extern int mips_ejtag_config_step(mips_ejtag_t *ejtag_info, int enable_step);
-extern int mips_ejtag_read_debug(mips_ejtag_t *ejtag_info, u32* debug_reg);
+int mips_ejtag_init(struct mips_ejtag *ejtag_info);
+int mips_ejtag_config_step(struct mips_ejtag *ejtag_info, int enable_step);
+int mips_ejtag_read_debug(struct mips_ejtag *ejtag_info, uint32_t* debug_reg);
 
 #endif /* MIPS_EJTAG */