X-Git-Url: https://review.openocd.org/gitweb?p=openocd.git;a=blobdiff_plain;f=src%2Ftarget%2Fmips_ejtag.c;h=cea8fa804c1fdd9e8027aa468d7d3f349eb78a27;hp=c169c6f0682bb2f191fa6281e1e906313eb867e4;hb=e7e9bfde47768b22be8b15c30c027dc8fb67c778;hpb=c0787b699496080d48174713a0b30e81ef5db3be

diff --git a/src/target/mips_ejtag.c b/src/target/mips_ejtag.c
index c169c6f068..cea8fa804c 100644
--- a/src/target/mips_ejtag.c
+++ b/src/target/mips_ejtag.c
@@ -4,6 +4,8 @@
  *                                                                         *
  *   Copyright (C) 2008 by David T.L. Wong                                 *
  *                                                                         *
+ *   Copyright (C) 2009 by David N. Claffey <dnclaffey@gmail.com>          *
+ *                                                                         *
  *   This program is free software; you can redistribute it and/or modify  *
  *   it under the terms of the GNU General Public License as published by  *
  *   the Free Software Foundation; either version 2 of the License, or     *
@@ -26,241 +28,250 @@
 #include "mips32.h"
 #include "mips_ejtag.h"
 
-#include "binarybuffer.h"
-#include "log.h"
-#include "jtag.h"
+int mips_ejtag_set_instr(struct mips_ejtag *ejtag_info, int new_instr, void *delete_me_and_submit_patch)
+{
+	struct jtag_tap *tap;
 
-#include <stdlib.h>
+	tap = ejtag_info->tap;
+	if (tap == NULL)
+		return ERROR_FAIL;
 
-int mips_ejtag_set_instr(mips_ejtag_t *ejtag_info, int new_instr, in_handler_t handler)
-{
-	jtag_device_t *device = jtag_get_device(ejtag_info->chain_pos);
-	
-	if (buf_get_u32(device->cur_instr, 0, device->ir_length) != new_instr)
+	if (buf_get_u32(tap->cur_instr, 0, tap->ir_length) != (uint32_t)new_instr)
 	{
-		scan_field_t field;
-		u8 t[4];
-		
-		field.device = ejtag_info->chain_pos;
-		field.num_bits = device->ir_length;
+		struct scan_field field;
+		uint8_t t[4];
+
+		field.num_bits = tap->ir_length;
 		field.out_value = t;
 		buf_set_u32(field.out_value, 0, field.num_bits, new_instr);
-		field.out_mask = NULL;
 		field.in_value = NULL;
-		field.in_check_value = NULL;
-		field.in_check_mask = NULL;
-		field.in_handler = handler;
-		field.in_handler_priv = NULL;
-		jtag_add_ir_scan(1, &field, -1);
+
+		jtag_add_ir_scan(tap, &field, jtag_get_end_state());
 	}
-	
+
 	return ERROR_OK;
 }
 
-int mips_ejtag_get_idcode(mips_ejtag_t *ejtag_info, u32 *idcode, in_handler_t handler)
+int mips_ejtag_get_idcode(struct mips_ejtag *ejtag_info, uint32_t *idcode)
 {
-	scan_field_t field;
-	
-	jtag_add_end_state(TAP_RTI);
-	
+	struct scan_field field;
+
+	jtag_set_end_state(TAP_IDLE);
+
 	mips_ejtag_set_instr(ejtag_info, EJTAG_INST_IDCODE, NULL);
-	
-	field.device = ejtag_info->chain_pos;
+
 	field.num_bits = 32;
 	field.out_value = NULL;
-	field.out_mask = NULL;
 	field.in_value = (void*)idcode;
-	field.in_check_value = NULL;
-	field.in_check_mask = NULL;
-	field.in_handler = NULL;
-	field.in_handler_priv = NULL;
-	jtag_add_dr_scan(1, &field, -1);
-	
+
+	jtag_add_dr_scan(ejtag_info->tap, 1, &field, jtag_get_end_state());
+
 	if (jtag_execute_queue() != ERROR_OK)
 	{
 		LOG_ERROR("register read failed");
 	}
-	
+
 	return ERROR_OK;
 }
 
-int mips_ejtag_get_impcode(mips_ejtag_t *ejtag_info, u32 *impcode, in_handler_t handler)
+int mips_ejtag_get_impcode(struct mips_ejtag *ejtag_info, uint32_t *impcode)
 {
-	scan_field_t field;
-	
-	jtag_add_end_state(TAP_RTI);
-	
+	struct scan_field field;
+
+	jtag_set_end_state(TAP_IDLE);
+
 	mips_ejtag_set_instr(ejtag_info, EJTAG_INST_IMPCODE, NULL);
-	
-	field.device = ejtag_info->chain_pos;
+
 	field.num_bits = 32;
 	field.out_value = NULL;
-	field.out_mask = NULL;
 	field.in_value = (void*)impcode;
-	field.in_check_value = NULL;
-	field.in_check_mask = NULL;
-	field.in_handler = NULL;
-	field.in_handler_priv = NULL;
-	jtag_add_dr_scan(1, &field, -1);
-	
+
+	jtag_add_dr_scan(ejtag_info->tap, 1, &field, jtag_get_end_state());
+
 	if (jtag_execute_queue() != ERROR_OK)
 	{
 		LOG_ERROR("register read failed");
 	}
-	
+
 	return ERROR_OK;
 }
 
-int mips_ejtag_drscan_32(mips_ejtag_t *ejtag_info, u32 *data)
+int mips_ejtag_drscan_32(struct mips_ejtag *ejtag_info, uint32_t *data)
 {
-	jtag_device_t *device;
-	device = jtag_get_device(ejtag_info->chain_pos);
-	scan_field_t field;
-	u8 t[4];
+	struct jtag_tap *tap;
+	tap  = ejtag_info->tap;
+
+	if (tap == NULL)
+		return ERROR_FAIL;
+	struct scan_field field;
+	uint8_t t[4], r[4];
 	int retval;
-	
-	field.device = ejtag_info->chain_pos;
+
 	field.num_bits = 32;
 	field.out_value = t;
 	buf_set_u32(field.out_value, 0, field.num_bits, *data);
-	field.out_mask = NULL;
-	field.in_value = (u8*)data;
-	field.in_check_value = NULL;
-	field.in_check_mask = NULL;
-	field.in_handler = NULL;
-	field.in_handler_priv = NULL;
-	jtag_add_dr_scan(1, &field, -1);
-	
+	field.in_value = r;
+
+	jtag_add_dr_scan(tap, 1, &field, jtag_get_end_state());
+
+	if ((retval = jtag_execute_queue()) != ERROR_OK)
+	{
+		LOG_ERROR("register read failed");
+		return retval;
+	}
+
+	*data = buf_get_u32(field.in_value, 0, 32);
+
+	keep_alive();
+
+	return ERROR_OK;
+}
+
+int mips_ejtag_drscan_8(struct mips_ejtag *ejtag_info, uint32_t *data)
+{
+	struct jtag_tap *tap;
+	tap  = ejtag_info->tap;
+
+	if (tap == NULL)
+		return ERROR_FAIL;
+	struct scan_field field;
+	uint8_t t[4], r[4];
+	int retval;
+
+	field.num_bits = 8;
+	field.out_value = t;
+	buf_set_u32(field.out_value, 0, field.num_bits, *data);
+	field.in_value = r;
+
+	jtag_add_dr_scan(tap, 1, &field, jtag_get_end_state());
+
 	if ((retval = jtag_execute_queue()) != ERROR_OK)
 	{
 		LOG_ERROR("register read failed");
 		return retval;
 	}
-	
+
+	*data = buf_get_u32(field.in_value, 0, 32);
+
+	keep_alive();
+
 	return ERROR_OK;
 }
 
-int mips_ejtag_step_enable(mips_ejtag_t *ejtag_info)
-{	
-	u32 code[] = {
+int mips_ejtag_step_enable(struct mips_ejtag *ejtag_info)
+{
+	static const uint32_t code[] = {
 			MIPS32_MTC0(1,31,0),			/* move $1 to COP0 DeSave */
 			MIPS32_MFC0(1,23,0),			/* move COP0 Debug to $1 */
 			MIPS32_ORI(1,1,0x0100),			/* set SSt bit in debug reg */
 			MIPS32_MTC0(1,23,0),			/* move $1 to COP0 Debug */
+			MIPS32_B(NEG16(5)),
 			MIPS32_MFC0(1,31,0),			/* move COP0 DeSave to $1 */
-			MIPS32_NOP,
-			MIPS32_B(NEG16(7)),
-			MIPS32_NOP,
 	};
-	
-	mips32_pracc_exec(ejtag_info, sizeof(code)/sizeof(code[0]), code, \
+
+	mips32_pracc_exec(ejtag_info, ARRAY_SIZE(code), code, \
 		0, NULL, 0, NULL, 1);
-	
+
 	return ERROR_OK;
 }
-int mips_ejtag_step_disable(mips_ejtag_t *ejtag_info)
+int mips_ejtag_step_disable(struct mips_ejtag *ejtag_info)
 {
-	u32 code[] = {
+	static const uint32_t code[] = {
 			MIPS32_MTC0(15,31,0),							/* move $15 to COP0 DeSave */
-			MIPS32_LUI(15,UPPER16(MIPS32_PRACC_STACK)), 	/* $15 = MIPS32_PRACC_STACK */
+			MIPS32_LUI(15,UPPER16(MIPS32_PRACC_STACK)),		/* $15 = MIPS32_PRACC_STACK */
 			MIPS32_ORI(15,15,LOWER16(MIPS32_PRACC_STACK)),
-			MIPS32_SW(1,0,15), 								/* sw $1,($15) */
-			MIPS32_SW(2,0,15), 								/* sw $2,($15) */
+			MIPS32_SW(1,0,15),								/* sw $1,($15) */
+			MIPS32_SW(2,0,15),								/* sw $2,($15) */
 			MIPS32_MFC0(1,23,0),							/* move COP0 Debug to $1 */
-			MIPS32_LUI(2,0xFFFF), 							/* $2 = 0xfffffeff */
+			MIPS32_LUI(2,0xFFFF),							/* $2 = 0xfffffeff */
 			MIPS32_ORI(2,2,0xFEFF),
 			MIPS32_AND(1,1,2),
 			MIPS32_MTC0(1,23,0),							/* move $1 to COP0 Debug */
 			MIPS32_LW(2,0,15),
 			MIPS32_LW(1,0,15),
+			MIPS32_B(NEG16(13)),
 			MIPS32_MFC0(15,31,0),							/* move COP0 DeSave to $15 */
-			MIPS32_NOP,
-			MIPS32_B(NEG16(15)),
-			MIPS32_NOP,
 	};
-	
-	mips32_pracc_exec(ejtag_info, sizeof(code)/sizeof(code[0]), code, \
+
+	mips32_pracc_exec(ejtag_info, ARRAY_SIZE(code), code, \
 		0, NULL, 0, NULL, 1);
-	
+
 	return ERROR_OK;
 }
 
-int mips_ejtag_config_step(mips_ejtag_t *ejtag_info, int enable_step)
-{	
+int mips_ejtag_config_step(struct mips_ejtag *ejtag_info, int enable_step)
+{
 	if (enable_step)
-		return mips_ejtag_step_enable(ejtag_info);	
+		return mips_ejtag_step_enable(ejtag_info);
 	return mips_ejtag_step_disable(ejtag_info);
 }
 
-int mips_ejtag_enter_debug(mips_ejtag_t *ejtag_info)
+int mips_ejtag_enter_debug(struct mips_ejtag *ejtag_info)
 {
-	u32 ejtag_ctrl;
-	jtag_add_end_state(TAP_RTI);
+	uint32_t ejtag_ctrl;
+	jtag_set_end_state(TAP_IDLE);
 	mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL);
-	
+
 	/* set debug break bit */
 	ejtag_ctrl = ejtag_info->ejtag_ctrl | EJTAG_CTRL_JTAGBRK;
 	mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
-	
+
 	/* break bit will be cleared by hardware */
 	ejtag_ctrl = ejtag_info->ejtag_ctrl;
 	mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
-	LOG_DEBUG("ejtag_ctrl: 0x%8.8x", ejtag_ctrl);
-	if((ejtag_ctrl & EJTAG_CTRL_BRKST) == 0)
+	LOG_DEBUG("ejtag_ctrl: 0x%8.8" PRIx32 "", ejtag_ctrl);
+	if ((ejtag_ctrl & EJTAG_CTRL_BRKST) == 0)
 		LOG_DEBUG("Failed to enter Debug Mode!");
-	
+
 	return ERROR_OK;
 }
 
-int mips_ejtag_exit_debug(mips_ejtag_t *ejtag_info, int enable_interrupts)
+int mips_ejtag_exit_debug(struct mips_ejtag *ejtag_info)
 {
-	u32 inst;
+	uint32_t inst;
 	inst = MIPS32_DRET;
-	
-	/* TODO : enable/disable interrrupts */
-	
+
 	/* execute our dret instruction */
 	mips32_pracc_exec(ejtag_info, 1, &inst, 0, NULL, 0, NULL, 0);
-	
+
 	return ERROR_OK;
 }
 
-int mips_ejtag_read_debug(mips_ejtag_t *ejtag_info, u32* debug_reg)
+int mips_ejtag_read_debug(struct mips_ejtag *ejtag_info, uint32_t* debug_reg)
 {
-	u32 code[] = {
+	/* read ejtag ECR */
+	static const uint32_t code[] = {
 			MIPS32_MTC0(15,31,0),							/* move $15 to COP0 DeSave */
-			MIPS32_LUI(15,UPPER16(MIPS32_PRACC_STACK)), 	/* $15 = MIPS32_PRACC_STACK */
+			MIPS32_LUI(15,UPPER16(MIPS32_PRACC_STACK)),		/* $15 = MIPS32_PRACC_STACK */
 			MIPS32_ORI(15,15,LOWER16(MIPS32_PRACC_STACK)),
-			MIPS32_SW(1,0,15), 								/* sw $1,($15) */
-			MIPS32_SW(2,0,15), 								/* sw $2,($15) */
-			MIPS32_LUI(1,UPPER16(MIPS32_PRACC_PARAM_OUT)), 	/* $1 = MIPS32_PRACC_PARAM_OUT */
+			MIPS32_SW(1,0,15),								/* sw $1,($15) */
+			MIPS32_SW(2,0,15),								/* sw $2,($15) */
+			MIPS32_LUI(1,UPPER16(MIPS32_PRACC_PARAM_OUT)),	/* $1 = MIPS32_PRACC_PARAM_OUT */
 			MIPS32_ORI(1,1,LOWER16(MIPS32_PRACC_PARAM_OUT)),
 			MIPS32_MFC0(2,23,0),							/* move COP0 Debug to $2 */
 			MIPS32_SW(2,0,1),
 			MIPS32_LW(2,0,15),
 			MIPS32_LW(1,0,15),
+			MIPS32_B(NEG16(12)),
 			MIPS32_MFC0(15,31,0),							/* move COP0 DeSave to $15 */
-			MIPS32_NOP,
-			MIPS32_B(NEG16(14)),
-			MIPS32_NOP,
 	};
-	
-	mips32_pracc_exec(ejtag_info, sizeof(code)/sizeof(code[0]), code, \
+
+	mips32_pracc_exec(ejtag_info, ARRAY_SIZE(code), code, \
 		0, NULL, 1, debug_reg, 1);
-	
+
 	return ERROR_OK;
 }
 
-int mips_ejtag_init(mips_ejtag_t *ejtag_info)
+int mips_ejtag_init(struct mips_ejtag *ejtag_info)
 {
-	u32 ejtag_version;
-	
-	mips_ejtag_get_impcode(ejtag_info, &ejtag_info->impcode, NULL);
-	LOG_DEBUG("impcode: 0x%8.8x", ejtag_info->impcode);
-	
+	uint32_t ejtag_version;
+
+	mips_ejtag_get_impcode(ejtag_info, &ejtag_info->impcode);
+	LOG_DEBUG("impcode: 0x%8.8" PRIx32 "", ejtag_info->impcode);
+
 	/* get ejtag version */
 	ejtag_version = ((ejtag_info->impcode >> 29) & 0x07);
-	
+
 	switch (ejtag_version)
 	{
 		case 0:
@@ -280,19 +291,56 @@ int mips_ejtag_init(mips_ejtag_t *ejtag_info)
 			break;
 	}
 	LOG_DEBUG("EJTAG: features:%s%s%s%s%s%s%s",
-		ejtag_info->impcode & (1<<28) ? " R3k":    " R4k",
-		ejtag_info->impcode & (1<<24) ? " DINT":   "",
-		ejtag_info->impcode & (1<<22) ? " ASID_8": "",
-		ejtag_info->impcode & (1<<21) ? " ASID_6": "",
-		ejtag_info->impcode & (1<<16) ? " MIPS16": "",
-		ejtag_info->impcode & (1<<14) ? " noDMA":  " DMA",
-		ejtag_info->impcode & (1<<0)  ? " MIPS64": " MIPS32"
-	);
-	if((ejtag_info->impcode & (1<<14)) == 0)
+		ejtag_info->impcode & EJTAG_IMP_R3K ? " R3k" : " R4k",
+		ejtag_info->impcode & EJTAG_IMP_DINT ? " DINT" : "",
+		ejtag_info->impcode & (1 << 22) ? " ASID_8" : "",
+		ejtag_info->impcode & (1 << 21) ? " ASID_6" : "",
+		ejtag_info->impcode & EJTAG_IMP_MIPS16 ? " MIPS16" : "",
+		ejtag_info->impcode & EJTAG_IMP_NODMA ? " noDMA" : " DMA",
+		ejtag_info->impcode & EJTAG_DCR_MIPS64  ? " MIPS64" : " MIPS32");
+
+	if ((ejtag_info->impcode & EJTAG_IMP_NODMA) == 0)
 		LOG_DEBUG("EJTAG: DMA Access Mode Support Enabled");
-	
+
 	/* set initial state for ejtag control reg */
 	ejtag_info->ejtag_ctrl = EJTAG_CTRL_ROCC | EJTAG_CTRL_PRACC | EJTAG_CTRL_PROBEN | EJTAG_CTRL_SETDEV;
-	
+
+	return ERROR_OK;
+}
+
+int mips_ejtag_fastdata_scan(struct mips_ejtag *ejtag_info, int write, uint32_t *data)
+{
+	struct jtag_tap *tap;
+	tap = ejtag_info->tap;
+
+	if (tap == NULL)
+		return ERROR_FAIL;
+
+	struct scan_field fields[2];
+	uint8_t spracc = 0;
+	uint8_t t[4] = {0, 0, 0, 0};
+
+	/* fastdata 1-bit register */
+	fields[0].num_bits = 1;
+	fields[0].out_value = &spracc;
+	fields[0].in_value = NULL;
+
+	/* processor access data register 32 bit */
+	fields[1].num_bits = 32;
+	fields[1].out_value = t;
+
+	if (write)
+	{
+		fields[1].in_value = NULL;
+		buf_set_u32(t, 0, 32, *data);
+	}
+	else
+	{
+		fields[1].in_value = (uint8_t *) data;
+	}
+
+	jtag_add_dr_scan(tap, 2, fields, jtag_get_end_state());
+	keep_alive();
+
 	return ERROR_OK;
 }