X-Git-Url: https://review.openocd.org/gitweb?p=openocd.git;a=blobdiff_plain;f=src%2Ftarget%2Fmips32_pracc.h;h=e31ba63e29540e000c6745d483a83e1cfdb3c9ba;hp=c200e93d51d7e512366c97c609805685a828733f;hb=HEAD;hpb=374127301ec1d72033b9d573b72c7abdfd61990d diff --git a/src/target/mips32_pracc.h b/src/target/mips32_pracc.h index c200e93d51..f78f89153f 100644 --- a/src/target/mips32_pracc.h +++ b/src/target/mips32_pracc.h @@ -1,3 +1,5 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + /*************************************************************************** * Copyright (C) 2008 by Spencer Oliver * * spen@spen-soft.co.uk * @@ -6,57 +8,68 @@ * * * Copyright (C) 2011 by Drasko DRASKOVIC * * drasko.draskovic@gmail.com * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. * - * * - * This program is distributed in the hope that it will be useful, * - * but WITHOUT ANY WARRANTY; without even the implied warranty of * - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * - * GNU General Public License for more details. * - * * - * You should have received a copy of the GNU General Public License * - * along with this program; if not, write to the * - * Free Software Foundation, Inc., * - * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. * ***************************************************************************/ -#ifndef MIPS32_PRACC_H -#define MIPS32_PRACC_H +#ifndef OPENOCD_TARGET_MIPS32_PRACC_H +#define OPENOCD_TARGET_MIPS32_PRACC_H #include #include #define MIPS32_PRACC_FASTDATA_AREA 0xFF200000 #define MIPS32_PRACC_FASTDATA_SIZE 16 -#define MIPS32_PRACC_TEXT 0xFF200200 -#define MIPS32_PRACC_STACK 0xFF204000 -#define MIPS32_PRACC_PARAM_IN 0xFF201000 -#define MIPS32_PRACC_PARAM_IN_SIZE 0x1000 -#define MIPS32_PRACC_PARAM_OUT (MIPS32_PRACC_PARAM_IN + MIPS32_PRACC_PARAM_IN_SIZE) -#define MIPS32_PRACC_PARAM_OUT_SIZE 0x1000 - -#define MIPS32_FASTDATA_HANDLER_SIZE 0x80 -#define UPPER16(uint32_t) (uint32_t >> 16) -#define LOWER16(uint32_t) (uint32_t & 0xFFFF) -#define NEG16(v) (((~(v)) + 1) & 0xFFFF) +#define MIPS32_PRACC_BASE_ADDR 0xFF200000 +#define MIPS32_PRACC_TEXT 0xFF200200 +#define MIPS32_PRACC_PARAM_OUT 0xFF202000 + +#define PRACC_UPPER_BASE_ADDR (MIPS32_PRACC_BASE_ADDR >> 16) +#define PRACC_MAX_CODE (MIPS32_PRACC_PARAM_OUT - MIPS32_PRACC_TEXT) +#define PRACC_MAX_INSTRUCTIONS (PRACC_MAX_CODE / 4) +#define PRACC_OUT_OFFSET (MIPS32_PRACC_PARAM_OUT - MIPS32_PRACC_BASE_ADDR) + +#define MIPS32_FASTDATA_HANDLER_SIZE 0x80 +#define UPPER16(addr) ((addr) >> 16) +#define LOWER16(addr) ((addr) & 0xFFFF) +#define NEG16(v) (((~(v)) + 1) & 0xFFFF) +#define SWAP16(v) ((LOWER16(v) << 16) | (UPPER16(v))) /*#define NEG18(v) (((~(v)) + 1) & 0x3FFFF)*/ +#define PRACC_BLOCK 128 /* 1 Kbyte */ + +struct mips32_common; + +struct pa_list { + uint32_t instr; + uint32_t addr; +}; + +struct pracc_queue_info { + struct mips_ejtag *ejtag_info; + unsigned isa; + int retval; + int code_count; + int store_count; + int max_code; /* max instructions with currently allocated memory */ + struct pa_list *pracc_list; /* Code and store addresses at dmseg */ +}; + +struct mips32_common; + +void pracc_queue_init(struct pracc_queue_info *ctx); +void pracc_add(struct pracc_queue_info *ctx, uint32_t addr, uint32_t instr); +void pracc_queue_free(struct pracc_queue_info *ctx); +int mips32_pracc_queue_exec(struct mips_ejtag *ejtag_info, + struct pracc_queue_info *ctx, uint32_t *buf, bool check_last); + int mips32_pracc_read_mem(struct mips_ejtag *ejtag_info, uint32_t addr, int size, int count, void *buf); int mips32_pracc_write_mem(struct mips_ejtag *ejtag_info, - uint32_t addr, int size, int count, void *buf); + uint32_t addr, int size, int count, const void *buf); int mips32_pracc_fastdata_xfer(struct mips_ejtag *ejtag_info, struct working_area *source, int write_t, uint32_t addr, int count, uint32_t *buf); -int mips32_pracc_read_regs(struct mips_ejtag *ejtag_info, uint32_t *regs); -int mips32_pracc_write_regs(struct mips_ejtag *ejtag_info, uint32_t *regs); - -int mips32_pracc_exec(struct mips_ejtag *ejtag_info, int code_len, const uint32_t *code, - int num_param_in, uint32_t *param_in, - int num_param_out, uint32_t *param_out, int cycle); +int mips32_pracc_read_regs(struct mips32_common *mips32); +int mips32_pracc_write_regs(struct mips32_common *mips32); /** * \b mips32_cp0_read @@ -69,7 +82,7 @@ int mips32_pracc_exec(struct mips_ejtag *ejtag_info, int code_len, const uint32_ * @param[in] cp0_reg Number of copro C0 register we want to read * @param[in] cp0_sel Select for the given C0 register * - * @return ERROR_OK on Sucess, ERROR_FAIL otherwise + * @return ERROR_OK on Success, ERROR_FAIL otherwise */ int mips32_cp0_read(struct mips_ejtag *ejtag_info, uint32_t *val, uint32_t cp0_reg, uint32_t cp0_sel); @@ -85,9 +98,31 @@ int mips32_cp0_read(struct mips_ejtag *ejtag_info, * @param[in] cp0_reg Number of copro C0 register we want to write to * @param[in] cp0_sel Select for the given C0 register * - * @return ERROR_OK on Sucess, ERROR_FAIL otherwise + * @return ERROR_OK on Success, ERROR_FAIL otherwise */ int mips32_cp0_write(struct mips_ejtag *ejtag_info, uint32_t val, uint32_t cp0_reg, uint32_t cp0_sel); -#endif +/** + * mips32_cp1_control_read + * + * @brief Simulates cfc1 ASM instruction (Move Control Word From Floating Point), + * i.e. implements copro C1 Control Register read. + * + * @param[in] ejtag_info + * @param[in] val Storage to hold read value + * @param[in] cp1_c_reg Number of copro C1 control register we want to read + * + * @return ERROR_OK on Success, ERROR_FAIL otherwise + */ +int mips32_cp1_control_read(struct mips_ejtag *ejtag_info, + uint32_t *val, uint32_t cp1_c_reg); + +static inline void pracc_swap16_array(struct mips_ejtag *ejtag_info, uint32_t *buf, int count) +{ + if (ejtag_info->isa && ejtag_info->endianness) + for (int i = 0; i != count; i++) + buf[i] = SWAP16(buf[i]); +} + +#endif /* OPENOCD_TARGET_MIPS32_PRACC_H */