X-Git-Url: https://review.openocd.org/gitweb?p=openocd.git;a=blobdiff_plain;f=src%2Ftarget%2Fmips32_dmaacc.c;h=220ea94f92405dc0671b1b84c2f7643397341591;hp=aa36d2cf6e05ad653d97e770f0b19d142090f33b;hb=HEAD;hpb=a8141cafdef162d52e128cd2ab51702b9800fda2 diff --git a/src/target/mips32_dmaacc.c b/src/target/mips32_dmaacc.c index aa36d2cf6e..beffbf51ee 100644 --- a/src/target/mips32_dmaacc.c +++ b/src/target/mips32_dmaacc.c @@ -1,3 +1,5 @@ +// SPDX-License-Identifier: GPL-2.0-or-later + /*************************************************************************** * Copyright (C) 2008 by John McCarthy * * jgmcc@magma.ca * @@ -6,28 +8,28 @@ * spen@spen-soft.co.uk * * * * Copyright (C) 2008 by David T.L. Wong * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. * - * * - * This program is distributed in the hope that it will be useful, * - * but WITHOUT ANY WARRANTY; without even the implied warranty of * - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * - * GNU General Public License for more details. * - * * - * You should have received a copy of the GNU General Public License * - * along with this program; if not, write to the * - * Free Software Foundation, Inc., * - * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. * ***************************************************************************/ + #ifdef HAVE_CONFIG_H #include "config.h" #endif #include "mips32_dmaacc.h" - +#include + +static int mips32_dmaacc_read_mem8(struct mips_ejtag *ejtag_info, + uint32_t addr, int count, uint8_t *buf); +static int mips32_dmaacc_read_mem16(struct mips_ejtag *ejtag_info, + uint32_t addr, int count, uint16_t *buf); +static int mips32_dmaacc_read_mem32(struct mips_ejtag *ejtag_info, + uint32_t addr, int count, uint32_t *buf); + +static int mips32_dmaacc_write_mem8(struct mips_ejtag *ejtag_info, + uint32_t addr, int count, const uint8_t *buf); +static int mips32_dmaacc_write_mem16(struct mips_ejtag *ejtag_info, + uint32_t addr, int count, const uint16_t *buf); +static int mips32_dmaacc_write_mem32(struct mips_ejtag *ejtag_info, + uint32_t addr, int count, const uint32_t *buf); /* * The following logic shamelessly cloned from HairyDairyMaid's wrt54g_debrick @@ -39,6 +41,22 @@ * displaying/modifying memory and memory mapped registers. */ +static int ejtag_dma_dstrt_poll(struct mips_ejtag *ejtag_info) +{ + uint32_t ejtag_ctrl; + int64_t start = timeval_ms(); + + do { + if (timeval_ms() - start > 1000) { + LOG_ERROR("DMA time out"); + return -ETIMEDOUT; + } + ejtag_ctrl = EJTAG_CTRL_DMAACC | ejtag_info->ejtag_ctrl; + mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl); + } while (ejtag_ctrl & EJTAG_CTRL_DSTRT); + return 0; +} + static int ejtag_dma_read(struct mips_ejtag *ejtag_info, uint32_t addr, uint32_t *data) { uint32_t v; @@ -49,36 +67,31 @@ begin_ejtag_dma_read: /* Setup Address */ v = addr; - mips_ejtag_set_instr(ejtag_info, EJTAG_INST_ADDRESS, NULL); + mips_ejtag_set_instr(ejtag_info, EJTAG_INST_ADDRESS); mips_ejtag_drscan_32(ejtag_info, &v); /* Initiate DMA Read & set DSTRT */ - mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL); + mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL); ejtag_ctrl = EJTAG_CTRL_DMAACC | EJTAG_CTRL_DRWN | EJTAG_CTRL_DMA_WORD | EJTAG_CTRL_DSTRT | ejtag_info->ejtag_ctrl; mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl); /* Wait for DSTRT to Clear */ - do { - ejtag_ctrl = EJTAG_CTRL_DMAACC | ejtag_info->ejtag_ctrl; - mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl); - } while (ejtag_ctrl & EJTAG_CTRL_DSTRT); + ejtag_dma_dstrt_poll(ejtag_info); /* Read Data */ - mips_ejtag_set_instr(ejtag_info, EJTAG_INST_DATA, NULL); + mips_ejtag_set_instr(ejtag_info, EJTAG_INST_DATA); mips_ejtag_drscan_32(ejtag_info, data); /* Clear DMA & Check DERR */ - mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL); + mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL); ejtag_ctrl = ejtag_info->ejtag_ctrl; mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl); - if (ejtag_ctrl & EJTAG_CTRL_DERR) - { + if (ejtag_ctrl & EJTAG_CTRL_DERR) { if (retries--) { - LOG_ERROR("DMA Read Addr = %08" PRIx32 " Data = ERROR ON READ (retrying)\n", addr); + LOG_ERROR("DMA Read Addr = %08" PRIx32 " Data = ERROR ON READ (retrying)", addr); goto begin_ejtag_dma_read; - } - else - LOG_ERROR("DMA Read Addr = %08" PRIx32 " Data = ERROR ON READ\n", addr); + } else + LOG_ERROR("DMA Read Addr = %08" PRIx32 " Data = ERROR ON READ", addr); return ERROR_JTAG_DEVICE_ERROR; } @@ -95,36 +108,32 @@ begin_ejtag_dma_read_h: /* Setup Address */ v = addr; - mips_ejtag_set_instr(ejtag_info, EJTAG_INST_ADDRESS, NULL); + mips_ejtag_set_instr(ejtag_info, EJTAG_INST_ADDRESS); mips_ejtag_drscan_32(ejtag_info, &v); /* Initiate DMA Read & set DSTRT */ - mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL); - ejtag_ctrl = EJTAG_CTRL_DMAACC | EJTAG_CTRL_DRWN | EJTAG_CTRL_DMA_HALFWORD | EJTAG_CTRL_DSTRT | ejtag_info->ejtag_ctrl; + mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL); + ejtag_ctrl = EJTAG_CTRL_DMAACC | EJTAG_CTRL_DRWN | EJTAG_CTRL_DMA_HALFWORD | + EJTAG_CTRL_DSTRT | ejtag_info->ejtag_ctrl; mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl); /* Wait for DSTRT to Clear */ - do { - ejtag_ctrl = EJTAG_CTRL_DMAACC | ejtag_info->ejtag_ctrl; - mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl); - } while (ejtag_ctrl & EJTAG_CTRL_DSTRT); + ejtag_dma_dstrt_poll(ejtag_info); /* Read Data */ - mips_ejtag_set_instr(ejtag_info, EJTAG_INST_DATA, NULL); + mips_ejtag_set_instr(ejtag_info, EJTAG_INST_DATA); mips_ejtag_drscan_32(ejtag_info, &v); /* Clear DMA & Check DERR */ - mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL); + mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL); ejtag_ctrl = ejtag_info->ejtag_ctrl; mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl); - if (ejtag_ctrl & EJTAG_CTRL_DERR) - { + if (ejtag_ctrl & EJTAG_CTRL_DERR) { if (retries--) { - LOG_ERROR("DMA Read Addr = %08" PRIx32 " Data = ERROR ON READ (retrying)\n", addr); + LOG_ERROR("DMA Read Addr = %08" PRIx32 " Data = ERROR ON READ (retrying)", addr); goto begin_ejtag_dma_read_h; - } - else - LOG_ERROR("DMA Read Addr = %08" PRIx32 " Data = ERROR ON READ\n", addr); + } else + LOG_ERROR("DMA Read Addr = %08" PRIx32 " Data = ERROR ON READ", addr); return ERROR_JTAG_DEVICE_ERROR; } @@ -147,36 +156,31 @@ begin_ejtag_dma_read_b: /* Setup Address */ v = addr; - mips_ejtag_set_instr(ejtag_info, EJTAG_INST_ADDRESS, NULL); + mips_ejtag_set_instr(ejtag_info, EJTAG_INST_ADDRESS); mips_ejtag_drscan_32(ejtag_info, &v); /* Initiate DMA Read & set DSTRT */ - mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL); + mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL); ejtag_ctrl = EJTAG_CTRL_DMAACC | EJTAG_CTRL_DRWN | EJTAG_CTRL_DMA_BYTE | EJTAG_CTRL_DSTRT | ejtag_info->ejtag_ctrl; mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl); /* Wait for DSTRT to Clear */ - do { - ejtag_ctrl = EJTAG_CTRL_DMAACC | ejtag_info->ejtag_ctrl; - mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl); - } while (ejtag_ctrl & EJTAG_CTRL_DSTRT); + ejtag_dma_dstrt_poll(ejtag_info); /* Read Data */ - mips_ejtag_set_instr(ejtag_info, EJTAG_INST_DATA, NULL); + mips_ejtag_set_instr(ejtag_info, EJTAG_INST_DATA); mips_ejtag_drscan_32(ejtag_info, &v); /* Clear DMA & Check DERR */ - mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL); + mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL); ejtag_ctrl = ejtag_info->ejtag_ctrl; mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl); - if (ejtag_ctrl & EJTAG_CTRL_DERR) - { + if (ejtag_ctrl & EJTAG_CTRL_DERR) { if (retries--) { - LOG_ERROR("DMA Read Addr = %08" PRIx32 " Data = ERROR ON READ (retrying)\n", addr); + LOG_ERROR("DMA Read Addr = %08" PRIx32 " Data = ERROR ON READ (retrying)", addr); goto begin_ejtag_dma_read_b; - } - else - LOG_ERROR("DMA Read Addr = %08" PRIx32 " Data = ERROR ON READ\n", addr); + } else + LOG_ERROR("DMA Read Addr = %08" PRIx32 " Data = ERROR ON READ", addr); return ERROR_JTAG_DEVICE_ERROR; } @@ -209,37 +213,32 @@ begin_ejtag_dma_write: /* Setup Address */ v = addr; - mips_ejtag_set_instr(ejtag_info, EJTAG_INST_ADDRESS, NULL); + mips_ejtag_set_instr(ejtag_info, EJTAG_INST_ADDRESS); mips_ejtag_drscan_32(ejtag_info, &v); /* Setup Data */ v = data; - mips_ejtag_set_instr(ejtag_info, EJTAG_INST_DATA, NULL); + mips_ejtag_set_instr(ejtag_info, EJTAG_INST_DATA); mips_ejtag_drscan_32(ejtag_info, &v); /* Initiate DMA Write & set DSTRT */ - mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL); + mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL); ejtag_ctrl = EJTAG_CTRL_DMAACC | EJTAG_CTRL_DMA_WORD | EJTAG_CTRL_DSTRT | ejtag_info->ejtag_ctrl; mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl); /* Wait for DSTRT to Clear */ - do { - ejtag_ctrl = EJTAG_CTRL_DMAACC | ejtag_info->ejtag_ctrl; - mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl); - } while (ejtag_ctrl & EJTAG_CTRL_DSTRT); + ejtag_dma_dstrt_poll(ejtag_info); /* Clear DMA & Check DERR */ - mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL); + mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL); ejtag_ctrl = ejtag_info->ejtag_ctrl; mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl); - if (ejtag_ctrl & EJTAG_CTRL_DERR) - { + if (ejtag_ctrl & EJTAG_CTRL_DERR) { if (retries--) { - LOG_ERROR("DMA Write Addr = %08" PRIx32 " Data = ERROR ON WRITE (retrying)\n", addr); + LOG_ERROR("DMA Write Addr = %08" PRIx32 " Data = ERROR ON WRITE (retrying)", addr); goto begin_ejtag_dma_write; - } - else - LOG_ERROR("DMA Write Addr = %08" PRIx32 " Data = ERROR ON WRITE\n", addr); + } else + LOG_ERROR("DMA Write Addr = %08" PRIx32 " Data = ERROR ON WRITE", addr); return ERROR_JTAG_DEVICE_ERROR; } @@ -260,37 +259,32 @@ begin_ejtag_dma_write_h: /* Setup Address */ v = addr; - mips_ejtag_set_instr(ejtag_info, EJTAG_INST_ADDRESS, NULL); + mips_ejtag_set_instr(ejtag_info, EJTAG_INST_ADDRESS); mips_ejtag_drscan_32(ejtag_info, &v); /* Setup Data */ v = data; - mips_ejtag_set_instr(ejtag_info, EJTAG_INST_DATA, NULL); + mips_ejtag_set_instr(ejtag_info, EJTAG_INST_DATA); mips_ejtag_drscan_32(ejtag_info, &v); /* Initiate DMA Write & set DSTRT */ - mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL); + mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL); ejtag_ctrl = EJTAG_CTRL_DMAACC | EJTAG_CTRL_DMA_HALFWORD | EJTAG_CTRL_DSTRT | ejtag_info->ejtag_ctrl; mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl); /* Wait for DSTRT to Clear */ - do { - ejtag_ctrl = EJTAG_CTRL_DMAACC | ejtag_info->ejtag_ctrl; - mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl); - } while (ejtag_ctrl & EJTAG_CTRL_DSTRT); + ejtag_dma_dstrt_poll(ejtag_info); /* Clear DMA & Check DERR */ - mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL); + mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL); ejtag_ctrl = ejtag_info->ejtag_ctrl; mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl); - if (ejtag_ctrl & EJTAG_CTRL_DERR) - { + if (ejtag_ctrl & EJTAG_CTRL_DERR) { if (retries--) { - LOG_ERROR("DMA Write Addr = %08" PRIx32 " Data = ERROR ON WRITE (retrying)\n", addr); + LOG_ERROR("DMA Write Addr = %08" PRIx32 " Data = ERROR ON WRITE (retrying)", addr); goto begin_ejtag_dma_write_h; - } - else - LOG_ERROR("DMA Write Addr = %08" PRIx32 " Data = ERROR ON WRITE\n", addr); + } else + LOG_ERROR("DMA Write Addr = %08" PRIx32 " Data = ERROR ON WRITE", addr); return ERROR_JTAG_DEVICE_ERROR; } @@ -312,37 +306,32 @@ begin_ejtag_dma_write_b: /* Setup Address*/ v = addr; - mips_ejtag_set_instr(ejtag_info, EJTAG_INST_ADDRESS, NULL); + mips_ejtag_set_instr(ejtag_info, EJTAG_INST_ADDRESS); mips_ejtag_drscan_32(ejtag_info, &v); /* Setup Data */ v = data; - mips_ejtag_set_instr(ejtag_info, EJTAG_INST_DATA, NULL); + mips_ejtag_set_instr(ejtag_info, EJTAG_INST_DATA); mips_ejtag_drscan_32(ejtag_info, &v); /* Initiate DMA Write & set DSTRT */ - mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL); + mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL); ejtag_ctrl = EJTAG_CTRL_DMAACC | EJTAG_CTRL_DMA_BYTE | EJTAG_CTRL_DSTRT | ejtag_info->ejtag_ctrl; mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl); /* Wait for DSTRT to Clear */ - do { - ejtag_ctrl = EJTAG_CTRL_DMAACC | ejtag_info->ejtag_ctrl; - mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl); - } while (ejtag_ctrl & EJTAG_CTRL_DSTRT); + ejtag_dma_dstrt_poll(ejtag_info); /* Clear DMA & Check DERR */ - mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL); + mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL); ejtag_ctrl = ejtag_info->ejtag_ctrl; mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl); - if (ejtag_ctrl & EJTAG_CTRL_DERR) - { + if (ejtag_ctrl & EJTAG_CTRL_DERR) { if (retries--) { - LOG_ERROR("DMA Write Addr = %08" PRIx32 " Data = ERROR ON WRITE (retrying)\n", addr); + LOG_ERROR("DMA Write Addr = %08" PRIx32 " Data = ERROR ON WRITE (retrying)", addr); goto begin_ejtag_dma_write_b; - } - else - LOG_ERROR("DMA Write Addr = %08" PRIx32 " Data = ERROR ON WRITE\n", addr); + } else + LOG_ERROR("DMA Write Addr = %08" PRIx32 " Data = ERROR ON WRITE", addr); return ERROR_JTAG_DEVICE_ERROR; } @@ -351,106 +340,110 @@ begin_ejtag_dma_write_b: int mips32_dmaacc_read_mem(struct mips_ejtag *ejtag_info, uint32_t addr, int size, int count, void *buf) { - switch (size) - { + switch (size) { case 1: - return mips32_dmaacc_read_mem8(ejtag_info, addr, count, (uint8_t*)buf); + return mips32_dmaacc_read_mem8(ejtag_info, addr, count, (uint8_t *)buf); case 2: - return mips32_dmaacc_read_mem16(ejtag_info, addr, count, (uint16_t*)buf); + return mips32_dmaacc_read_mem16(ejtag_info, addr, count, (uint16_t *)buf); case 4: - return mips32_dmaacc_read_mem32(ejtag_info, addr, count, (uint32_t*)buf); + return mips32_dmaacc_read_mem32(ejtag_info, addr, count, (uint32_t *)buf); } return ERROR_OK; } -int mips32_dmaacc_read_mem32(struct mips_ejtag *ejtag_info, uint32_t addr, int count, uint32_t *buf) +static int mips32_dmaacc_read_mem32(struct mips_ejtag *ejtag_info, uint32_t addr, int count, uint32_t *buf) { int i; int retval; for (i = 0; i < count; i++) { - if ((retval = ejtag_dma_read(ejtag_info, addr + i*sizeof(*buf), &buf[i])) != ERROR_OK) + retval = ejtag_dma_read(ejtag_info, addr + i * sizeof(*buf), &buf[i]); + if (retval != ERROR_OK) return retval; } return ERROR_OK; } -int mips32_dmaacc_read_mem16(struct mips_ejtag *ejtag_info, uint32_t addr, int count, uint16_t *buf) +static int mips32_dmaacc_read_mem16(struct mips_ejtag *ejtag_info, uint32_t addr, int count, uint16_t *buf) { int i; int retval; for (i = 0; i < count; i++) { - if ((retval = ejtag_dma_read_h(ejtag_info, addr + i*sizeof(*buf), &buf[i])) != ERROR_OK) + retval = ejtag_dma_read_h(ejtag_info, addr + i * sizeof(*buf), &buf[i]); + if (retval != ERROR_OK) return retval; } return ERROR_OK; } -int mips32_dmaacc_read_mem8(struct mips_ejtag *ejtag_info, uint32_t addr, int count, uint8_t *buf) +static int mips32_dmaacc_read_mem8(struct mips_ejtag *ejtag_info, uint32_t addr, int count, uint8_t *buf) { int i; int retval; for (i = 0; i < count; i++) { - if ((retval = ejtag_dma_read_b(ejtag_info, addr + i*sizeof(*buf), &buf[i])) != ERROR_OK) + retval = ejtag_dma_read_b(ejtag_info, addr + i * sizeof(*buf), &buf[i]); + if (retval != ERROR_OK) return retval; } return ERROR_OK; } -int mips32_dmaacc_write_mem(struct mips_ejtag *ejtag_info, uint32_t addr, int size, int count, void *buf) +int mips32_dmaacc_write_mem(struct mips_ejtag *ejtag_info, uint32_t addr, int size, int count, const void *buf) { - switch (size) - { + switch (size) { case 1: - return mips32_dmaacc_write_mem8(ejtag_info, addr, count, (uint8_t*)buf); + return mips32_dmaacc_write_mem8(ejtag_info, addr, count, buf); case 2: - return mips32_dmaacc_write_mem16(ejtag_info, addr, count,(uint16_t*)buf); + return mips32_dmaacc_write_mem16(ejtag_info, addr, count, buf); case 4: - return mips32_dmaacc_write_mem32(ejtag_info, addr, count, (uint32_t*)buf); + return mips32_dmaacc_write_mem32(ejtag_info, addr, count, buf); } return ERROR_OK; } -int mips32_dmaacc_write_mem32(struct mips_ejtag *ejtag_info, uint32_t addr, int count, uint32_t *buf) +static int mips32_dmaacc_write_mem32(struct mips_ejtag *ejtag_info, uint32_t addr, int count, const uint32_t *buf) { int i; int retval; for (i = 0; i < count; i++) { - if ((retval = ejtag_dma_write(ejtag_info, addr + i*sizeof(*buf), buf[i])) != ERROR_OK) + retval = ejtag_dma_write(ejtag_info, addr + i * sizeof(*buf), buf[i]); + if (retval != ERROR_OK) return retval; } return ERROR_OK; } -int mips32_dmaacc_write_mem16(struct mips_ejtag *ejtag_info, uint32_t addr, int count, uint16_t *buf) +static int mips32_dmaacc_write_mem16(struct mips_ejtag *ejtag_info, uint32_t addr, int count, const uint16_t *buf) { int i; int retval; for (i = 0; i < count; i++) { - if ((retval = ejtag_dma_write_h(ejtag_info, addr + i*sizeof(*buf), buf[i])) != ERROR_OK) + retval = ejtag_dma_write_h(ejtag_info, addr + i * sizeof(*buf), buf[i]); + if (retval != ERROR_OK) return retval; } return ERROR_OK; } -int mips32_dmaacc_write_mem8(struct mips_ejtag *ejtag_info, uint32_t addr, int count, uint8_t *buf) +static int mips32_dmaacc_write_mem8(struct mips_ejtag *ejtag_info, uint32_t addr, int count, const uint8_t *buf) { int i; int retval; for (i = 0; i < count; i++) { - if ((retval = ejtag_dma_write_b(ejtag_info, addr + i*sizeof(*buf), buf[i])) != ERROR_OK) + retval = ejtag_dma_write_b(ejtag_info, addr + i * sizeof(*buf), buf[i]); + if (retval != ERROR_OK) return retval; }